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Wed, 20 Nov 2024 08:47:12 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 20 Nov 2024 08:47:12 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 20 Nov 2024 08:47:12 -0600 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4AKElCLp004675; Wed, 20 Nov 2024 08:47:12 -0600 Date: Wed, 20 Nov 2024 08:47:12 -0600 From: Bryan Brattlof To: Andrew Davis CC: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , Subject: Re: [PATCH 2/2] arm64: dts: ti: k3-am62l: add initial reference board file Message-ID: <20241120144712.dxiu34ocv7xdv5rm@bryanbrattlof.com> X-PGP-Fingerprint: D3D1 77E4 0A38 DF4D 1853 FEEF 41B9 0D5D 71D5 6CE0 References: <20241117-am62lx-v1-0-4e71e42d781d@ti.com> <20241117-am62lx-v1-2-4e71e42d781d@ti.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea On November 18, 2024 thus sayeth Andrew Davis: > On 11/17/24 11:34 PM, Bryan Brattlof wrote: > > From: Vignesh Raghavendra > > > > Add the initial board file for the AM62L3's Evaluation Module. > > > > Signed-off-by: Vignesh Raghavendra > > Signed-off-by: Bryan Brattlof > > --- > > arch/arm64/boot/dts/ti/k3-am62l3-evm.dts | 54 ++++++++++++++++++++++++++++++++ > > 1 file changed, 54 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts b/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts > > new file mode 100644 > > index 0000000000000..2d59389765cab > > --- /dev/null > > +++ b/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts > > @@ -0,0 +1,54 @@ > > +// SPDX-License-Identifier: GPL-2.0-only or MIT > > +/* > > + * Device Tree file for the AM62L3 Evaluation Module > > + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ > > + * > > + * Technical Reference Manual: https://www.ti.com/lit/ug/sprujb4/sprujb4.pdf > > + */ > > + > > +/dts-v1/; > > + > > +#include "k3-am62l3.dtsi" > > + > > +/ { > > + compatible = "ti,am62l3-evm", "ti,am62l3"; > > + model = "Texas Instruments AM62L3 Evaluation Module"; > > + > > + aliases { > > + serial2 = &main_uart0; > > We usually have WKUP and MCU UARTs as serial0 and serial1, we don't > have that many, so we would never have serial1, only 0 and 2. Might > be time we drop this odd numbering convention, at least for AM62L > class parts.. > Good point. I'll see what I can come up with > > + }; > > + > > + chosen { > > + stdout-path = &main_uart0; > > + }; > > + > > + memory@80000000 { > > + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; > > + device_type = "memory"; > > + bootph-all; > > + }; > > + > > + reserved-memory { > > Not needed until you have something to reserve. > Ah I agree. I'll drop this next time. > > + ranges; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + }; > > +}; > > + > > +&pmx0 { > > + main_uart0_pins_default: main_uart0-default-pins { > > + pinctrl-single,pins = < > > + AM62LX_IOPAD(0x01d4, PIN_INPUT, 1) /* (D7) UART0_RXD */ > > + AM62LX_IOPAD(0x01d8, PIN_OUTPUT, 1) /* (A6) UART0_TXD */ > > + >; > > + bootph-all; > > + }; > > +}; > > + > > +&main_uart0 { > > + current-speed = <115200>; > > current-speed is only for UARTs that can't detect their current speed, > our UART and driver can, so this line isn't needed. > Nice! I'll drop this property as well ~Bryan