From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 872BB2500C9; Sun, 24 Nov 2024 17:24:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732469084; cv=none; b=E3GyKPymsp971ZMlzRzm+qYE6sSiiFZp7nf+cAKKPd49lz//1Fa2C0yL0yf0zVLErVo/jnuugyJ6zRuXxwxUrqRFThVWp9FYbcBnMrDecUN1dHXCVQ2NZBj/2FkPfbUmJXeYsorJr+y/eFoGDedHEwnPhTeENBo55lsrlDTH6ic= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732469084; c=relaxed/simple; bh=gBS9Xb9J9aUTspgdk8YKdUceNEXMi87MEJY9qeNPAok=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qqt0Oov4uukaWPdnEmCfq5n5nHGt7vt62KM3gYzzkiEe0qF09KoqSIIYCiXgPa43w9kRelVrYCoAiaBWnyaYnzMksJtKAXkQg/Cz+oV7GTCjobOAuj0hf2DmOfHKMaxVdapc7kPuP9tSkzEQIyPC3FYieORRhsFoobGTrp+WZ1M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=T2it6MTE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="T2it6MTE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8E091C4CECC; Sun, 24 Nov 2024 17:24:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732469084; bh=gBS9Xb9J9aUTspgdk8YKdUceNEXMi87MEJY9qeNPAok=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=T2it6MTEWkKftEs8ueslPHX9WP2/Vz5Aas4YWxOyRhB1xfRm5cU1jZunQz5PDCbBa /FqN4dbzriaKVB6HQwxsLAtLKoIWdPzRues6FXvEckJicaktWHVXyyNg4NN8jj5erf ItVpUhT0FCDxzhubVPTBtrWWDC9EBjws4xpsiFsoEfVYck04uu9nCw+aScEEvXO8XY qmmrad3EnGkrqZcC3j/e8LWfY6wOQYyHjZeFTA5jjicaXptQaC9R72FXTxYWOKF0C1 BKmyEAykZqT2gM24uMcxXNpz2OQtbuQZwLkMRG6XSX/9tE8EV7YRWVpbEbUqqM/LP7 pZoi4OxzUyp1Q== Date: Sun, 24 Nov 2024 17:24:33 +0000 From: Jonathan Cameron To: David Lechner Cc: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nuno =?UTF-8?B?U8Oh?= , Uwe =?UTF-8?B?S2xlaW5lLUvDtm5pZw==?= , Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org Subject: Re: [PATCH v5 12/16] iio: adc: ad7944: add support for SPI offload Message-ID: <20241124172433.78079a9c@jic23-huawei> In-Reply-To: <20241115-dlech-mainline-spi-engine-offload-2-v5-12-bea815bd5ea5@baylibre.com> References: <20241115-dlech-mainline-spi-engine-offload-2-v5-0-bea815bd5ea5@baylibre.com> <20241115-dlech-mainline-spi-engine-offload-2-v5-12-bea815bd5ea5@baylibre.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.43; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Fri, 15 Nov 2024 14:18:51 -0600 David Lechner wrote: > This adds support for SPI offload to the ad7944 driver. This allows > reading data at the max sample rate of 2.5 MSPS. > > Signed-off-by: David Lechner One request for some documentation on the storagebits value. Otherwise looks good to me. Reviewed-by: Jonathan Cameron Note I'm giving tags because it might not all go through my tree + it's big and complex so they have the advantage I won't read things again if I've already tagged them (probably!) Jonathan > @@ -129,13 +144,33 @@ static const struct ad7944_chip_info _name##_chip_info = { \ > }, \ > IIO_CHAN_SOFT_TIMESTAMP(1), \ > }, \ > + /* basically the same minus soft timestamp plus sampling freq */\ > + .offload_channels = { \ > + { \ > + .type = IIO_VOLTAGE, \ > + .indexed = 1, \ > + .differential = _diff, \ > + .channel = 0, \ > + .channel2 = _diff ? 1 : 0, \ > + .scan_index = 0, \ > + .scan_type.sign = _diff ? 's' : 'u', \ > + .scan_type.realbits = _bits, \ > + .scan_type.storagebits = 32, \ Add a comment somewhere here on why it jumps up to 32 bits. > + .scan_type.endianness = IIO_CPU, \ > + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ > + | BIT(IIO_CHAN_INFO_SCALE) \ > + | BIT(IIO_CHAN_INFO_SAMP_FREQ), \ > + .info_mask_separate_available = \ > + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ > + }, \ > + }, \ > }