* [PATCH v3 0/3] riscv: Add bfloat16 instruction support
@ 2024-12-06 5:58 Inochi Amaoto
2024-12-06 5:58 ` [PATCH v3 1/3] dt-bindings: riscv: add bfloat16 ISA extension description Inochi Amaoto
` (3 more replies)
0 siblings, 4 replies; 15+ messages in thread
From: Inochi Amaoto @ 2024-12-06 5:58 UTC (permalink / raw)
To: Chen Wang, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Clément Léger, Evan Green, Charlie Jenkins,
Andrew Jones, Jesse Taube, Andy Chiu, Alexandre Ghiti,
Inochi Amaoto, Samuel Holland, Yong-Xuan Wang
Cc: linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan,
Longbin Li
Add description for the BFloat16 precision Floating-Point ISA extension,
(Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62
("Added Chapter title to BF16") of the riscv-isa-manual.
Changed from v2:
1. rebase for v6.13-rc1
Changed from v1:
1. add missing code in sys_hwprobe.c
Inochi Amaoto (3):
dt-bindings: riscv: add bfloat16 ISA extension description
riscv: add ISA extension parsing for bfloat16 ISA extension
riscv: hwprobe: export bfloat16 ISA extension
Documentation/arch/riscv/hwprobe.rst | 12 +++++
.../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++
arch/riscv/include/asm/hwcap.h | 3 ++
arch/riscv/include/uapi/asm/hwprobe.h | 3 ++
arch/riscv/kernel/cpufeature.c | 3 ++
arch/riscv/kernel/sys_hwprobe.c | 3 ++
6 files changed, 69 insertions(+)
--
2.47.1
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v3 1/3] dt-bindings: riscv: add bfloat16 ISA extension description 2024-12-06 5:58 [PATCH v3 0/3] riscv: Add bfloat16 instruction support Inochi Amaoto @ 2024-12-06 5:58 ` Inochi Amaoto 2024-12-16 22:00 ` Samuel Holland 2024-12-06 5:58 ` [PATCH v3 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension Inochi Amaoto ` (2 subsequent siblings) 3 siblings, 1 reply; 15+ messages in thread From: Inochi Amaoto @ 2024-12-06 5:58 UTC (permalink / raw) To: Chen Wang, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Clément Léger, Evan Green, Charlie Jenkins, Andrew Jones, Jesse Taube, Andy Chiu, Alexandre Ghiti, Inochi Amaoto, Samuel Holland, Yong-Xuan Wang Cc: linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan, Longbin Li, Conor Dooley Add description for the BFloat16 precision Floating-Point ISA extension, (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62 ("Added Chapter title to BF16") of the riscv-isa-manual. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- .../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 9c7dd7e75e0c..0a1f1a76d129 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -329,6 +329,12 @@ properties: instructions, as ratified in commit 056b6ff ("Zfa is ratified") of riscv-isa-manual. + - const: zfbfmin + description: + The standard Zfbfmin extension which provides minimal support for + 16-bit half-precision brain floating-point instructions, as ratified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. + - const: zfh description: The standard Zfh extension for 16-bit half-precision binary @@ -525,6 +531,18 @@ properties: in commit 6f702a2 ("Vector extensions are now ratified") of riscv-v-spec. + - const: zvfbfmin + description: + The standard Zvfbfmin extension for minimal support for vectored + 16-bit half-precision brain floating-point instructions, as ratified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. + + - const: zvfbfwma + description: + The standard Zvfbfwma extension for vectored half-precision brain + floating-point widening multiply-accumulate instructions, as ratified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. + - const: zvfh description: The standard Zvfh extension for vectored half-precision @@ -663,6 +681,33 @@ properties: then: contains: const: zca + # Zfbfmin depends on F + - if: + contains: + const: zfbfmin + then: + contains: + const: f + # Zvfbfmin depends on V or Zve32f + - if: + contains: + const: zvfbfmin + then: + oneOf: + - contains: + const: v + - contains: + const: zve32f + # Zvfbfwma depends on Zfbfmin and Zvfbfmin + - if: + contains: + const: zvfbfwma + then: + allOf: + - contains: + const: zfbfmin + - contains: + const: zvfbfmin allOf: # Zcf extension does not exist on rv64 -- 2.47.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: riscv: add bfloat16 ISA extension description 2024-12-06 5:58 ` [PATCH v3 1/3] dt-bindings: riscv: add bfloat16 ISA extension description Inochi Amaoto @ 2024-12-16 22:00 ` Samuel Holland 2024-12-16 22:51 ` Jessica Clarke 0 siblings, 1 reply; 15+ messages in thread From: Samuel Holland @ 2024-12-16 22:00 UTC (permalink / raw) To: Inochi Amaoto Cc: linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan, Longbin Li, Conor Dooley, Chen Wang, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Clément Léger, Evan Green, Charlie Jenkins, Andrew Jones, Jesse Taube, Andy Chiu, Alexandre Ghiti, Yong-Xuan Wang On 2024-12-05 11:58 PM, Inochi Amaoto wrote: > Add description for the BFloat16 precision Floating-Point ISA extension, > (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62 > ("Added Chapter title to BF16") of the riscv-isa-manual. > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 9c7dd7e75e0c..0a1f1a76d129 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -329,6 +329,12 @@ properties: > instructions, as ratified in commit 056b6ff ("Zfa is ratified") of > riscv-isa-manual. > > + - const: zfbfmin > + description: > + The standard Zfbfmin extension which provides minimal support for > + 16-bit half-precision brain floating-point instructions, as ratified I think you mean "binary" here and in the entries below, not "brain". > + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. > + > - const: zfh > description: > The standard Zfh extension for 16-bit half-precision binary > @@ -525,6 +531,18 @@ properties: > in commit 6f702a2 ("Vector extensions are now ratified") of > riscv-v-spec. > > + - const: zvfbfmin > + description: > + The standard Zvfbfmin extension for minimal support for vectored > + 16-bit half-precision brain floating-point instructions, as ratified > + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. > + > + - const: zvfbfwma > + description: > + The standard Zvfbfwma extension for vectored half-precision brain > + floating-point widening multiply-accumulate instructions, as ratified > + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. > + > - const: zvfh > description: > The standard Zvfh extension for vectored half-precision > @@ -663,6 +681,33 @@ properties: > then: > contains: > const: zca > + # Zfbfmin depends on F > + - if: > + contains: > + const: zfbfmin > + then: > + contains: > + const: f > + # Zvfbfmin depends on V or Zve32f > + - if: > + contains: > + const: zvfbfmin > + then: > + oneOf: > + - contains: > + const: v > + - contains: > + const: zve32f > + # Zvfbfwma depends on Zfbfmin and Zvfbfmin > + - if: > + contains: > + const: zvfbfwma > + then: > + allOf: > + - contains: > + const: zfbfmin > + - contains: > + const: zvfbfmin > > allOf: > # Zcf extension does not exist on rv64 ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: riscv: add bfloat16 ISA extension description 2024-12-16 22:00 ` Samuel Holland @ 2024-12-16 22:51 ` Jessica Clarke 2024-12-19 0:36 ` Samuel Holland 0 siblings, 1 reply; 15+ messages in thread From: Jessica Clarke @ 2024-12-16 22:51 UTC (permalink / raw) To: Samuel Holland Cc: Inochi Amaoto, linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan, Longbin Li, Conor Dooley, Chen Wang, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Clément Léger, Evan Green, Charlie Jenkins, Andrew Jones, Jesse Taube, Andy Chiu, Alexandre Ghiti, Yong-Xuan Wang On 16 Dec 2024, at 22:00, Samuel Holland <samuel.holland@sifive.com> wrote: > > On 2024-12-05 11:58 PM, Inochi Amaoto wrote: >> Add description for the BFloat16 precision Floating-Point ISA extension, >> (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62 >> ("Added Chapter title to BF16") of the riscv-isa-manual. >> >> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> >> Acked-by: Conor Dooley <conor.dooley@microchip.com> >> --- >> .../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++ >> 1 file changed, 45 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml >> index 9c7dd7e75e0c..0a1f1a76d129 100644 >> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml >> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml >> @@ -329,6 +329,12 @@ properties: >> instructions, as ratified in commit 056b6ff ("Zfa is ratified") of >> riscv-isa-manual. >> >> + - const: zfbfmin >> + description: >> + The standard Zfbfmin extension which provides minimal support for >> + 16-bit half-precision brain floating-point instructions, as ratified > > I think you mean "binary" here and in the entries below, not "brain”. No, that’s Zfhmin / FP16 / binary16, not Zfbfmin / BF16 / BFloat16? The B is for Brain as it came out of Google Brain. https://en.wikipedia.org/wiki/Bfloat16_floating-point_format Jess ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: riscv: add bfloat16 ISA extension description 2024-12-16 22:51 ` Jessica Clarke @ 2024-12-19 0:36 ` Samuel Holland 0 siblings, 0 replies; 15+ messages in thread From: Samuel Holland @ 2024-12-19 0:36 UTC (permalink / raw) To: Jessica Clarke, Inochi Amaoto Cc: linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan, Longbin Li, Conor Dooley, Chen Wang, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Clément Léger, Evan Green, Charlie Jenkins, Andrew Jones, Jesse Taube, Andy Chiu, Alexandre Ghiti, Yong-Xuan Wang On 2024-12-16 4:51 PM, Jessica Clarke wrote: > On 16 Dec 2024, at 22:00, Samuel Holland <samuel.holland@sifive.com> wrote: >> >> On 2024-12-05 11:58 PM, Inochi Amaoto wrote: >>> Add description for the BFloat16 precision Floating-Point ISA extension, >>> (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62 >>> ("Added Chapter title to BF16") of the riscv-isa-manual. >>> >>> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> >>> Acked-by: Conor Dooley <conor.dooley@microchip.com> >>> --- >>> .../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++ >>> 1 file changed, 45 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml >>> index 9c7dd7e75e0c..0a1f1a76d129 100644 >>> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml >>> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml >>> @@ -329,6 +329,12 @@ properties: >>> instructions, as ratified in commit 056b6ff ("Zfa is ratified") of >>> riscv-isa-manual. >>> >>> + - const: zfbfmin >>> + description: >>> + The standard Zfbfmin extension which provides minimal support for >>> + 16-bit half-precision brain floating-point instructions, as ratified >> >> I think you mean "binary" here and in the entries below, not "brain”. > > No, that’s Zfhmin / FP16 / binary16, not Zfbfmin / BF16 / BFloat16? The > B is for Brain as it came out of Google Brain. > > https://en.wikipedia.org/wiki/Bfloat16_floating-point_format Ah, yes, I was the confused one here. Sorry for the noise. ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension 2024-12-06 5:58 [PATCH v3 0/3] riscv: Add bfloat16 instruction support Inochi Amaoto 2024-12-06 5:58 ` [PATCH v3 1/3] dt-bindings: riscv: add bfloat16 ISA extension description Inochi Amaoto @ 2024-12-06 5:58 ` Inochi Amaoto 2025-02-10 14:38 ` Clément Léger 2024-12-06 5:58 ` [PATCH v3 3/3] riscv: hwprobe: export " Inochi Amaoto 2025-03-27 3:24 ` [PATCH v3 0/3] riscv: Add bfloat16 instruction support patchwork-bot+linux-riscv 3 siblings, 1 reply; 15+ messages in thread From: Inochi Amaoto @ 2024-12-06 5:58 UTC (permalink / raw) To: Chen Wang, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Clément Léger, Evan Green, Charlie Jenkins, Andrew Jones, Jesse Taube, Andy Chiu, Alexandre Ghiti, Inochi Amaoto, Samuel Holland, Yong-Xuan Wang Cc: linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan, Longbin Li Add parsing for Zfbmin, Zvfbfmin, Zvfbfwma ISA extension which were ratified in 4dc23d62 ("Added Chapter title to BF16") of the riscv-isa-manual. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> --- arch/riscv/include/asm/hwcap.h | 3 +++ arch/riscv/kernel/cpufeature.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 869da082252a..14cc29f2a723 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -100,6 +100,9 @@ #define RISCV_ISA_EXT_ZICCRSE 91 #define RISCV_ISA_EXT_SVADE 92 #define RISCV_ISA_EXT_SVADU 93 +#define RISCV_ISA_EXT_ZFBFMIN 94 +#define RISCV_ISA_EXT_ZVFBFMIN 95 +#define RISCV_ISA_EXT_ZVFBFWMA 96 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c0916ed318c2..5cfcab139568 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -341,6 +341,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS), __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), + __RISCV_ISA_EXT_DATA(zfbfmin, RISCV_ISA_EXT_ZFBFMIN), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA), @@ -373,6 +374,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), + __RISCV_ISA_EXT_DATA(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN), + __RISCV_ISA_EXT_DATA(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA), __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), -- 2.47.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension 2024-12-06 5:58 ` [PATCH v3 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension Inochi Amaoto @ 2025-02-10 14:38 ` Clément Léger 2025-02-11 0:42 ` Inochi Amaoto 0 siblings, 1 reply; 15+ messages in thread From: Clément Léger @ 2025-02-10 14:38 UTC (permalink / raw) Cc: linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan, Longbin Li, Jesse Taube, Yong-Xuan Wang, Samuel Holland, Krzysztof Kozlowski, Evan Green, Andrew Jones, Alexandre Ghiti, Andy Chiu, Charlie Jenkins, Conor Dooley, Rob Herring, Albert Ou, Palmer Dabbelt, Paul Walmsley, Jonathan Corbet, Chen Wang, Inochi Amaoto On 06/12/2024 06:58, Inochi Amaoto wrote: > Add parsing for Zfbmin, Zvfbfmin, Zvfbfwma ISA extension which > were ratified in 4dc23d62 ("Added Chapter title to BF16") of > the riscv-isa-manual. > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > --- > arch/riscv/include/asm/hwcap.h | 3 +++ > arch/riscv/kernel/cpufeature.c | 3 +++ > 2 files changed, 6 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 869da082252a..14cc29f2a723 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -100,6 +100,9 @@ > #define RISCV_ISA_EXT_ZICCRSE 91 > #define RISCV_ISA_EXT_SVADE 92 > #define RISCV_ISA_EXT_SVADU 93 > +#define RISCV_ISA_EXT_ZFBFMIN 94 > +#define RISCV_ISA_EXT_ZVFBFMIN 95 > +#define RISCV_ISA_EXT_ZVFBFWMA 96 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index c0916ed318c2..5cfcab139568 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -341,6 +341,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), > __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS), > __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), > + __RISCV_ISA_EXT_DATA(zfbfmin, RISCV_ISA_EXT_ZFBFMIN), Hi Inochi, You could add a validation callback to that extension: static int riscv_ext_f_depends(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) return 0; return -EPROBE_DEFER; } ... __RISCV_ISA_EXT_DATA_VALIDATE(zfbfmin, RISCV_ISA_EXT_ZFBFMIN, riscv_ext_f_depends), But I'm ok with the current state of that patch since I have the same thing coming for other extensions as well. So with or without my previous comment fixed: Reviewed-by: Clément Léger <cleger@rivosinc.com> Thanks, Clément > __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), > __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), > __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA), > @@ -373,6 +374,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), > __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), > __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), > + __RISCV_ISA_EXT_DATA(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN), > + __RISCV_ISA_EXT_DATA(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA), > __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), > __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), > __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension 2025-02-10 14:38 ` Clément Léger @ 2025-02-11 0:42 ` Inochi Amaoto 2025-02-11 13:45 ` Conor Dooley 0 siblings, 1 reply; 15+ messages in thread From: Inochi Amaoto @ 2025-02-11 0:42 UTC (permalink / raw) To: Clément Léger Cc: linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan, Longbin Li, Jesse Taube, Yong-Xuan Wang, Samuel Holland, Krzysztof Kozlowski, Evan Green, Andrew Jones, Alexandre Ghiti, Andy Chiu, Charlie Jenkins, Conor Dooley, Rob Herring, Albert Ou, Palmer Dabbelt, Paul Walmsley, Jonathan Corbet, Chen Wang, Inochi Amaoto On Mon, Feb 10, 2025 at 03:38:58PM +0100, Clément Léger wrote: > > > On 06/12/2024 06:58, Inochi Amaoto wrote: > > Add parsing for Zfbmin, Zvfbfmin, Zvfbfwma ISA extension which > > were ratified in 4dc23d62 ("Added Chapter title to BF16") of > > the riscv-isa-manual. > > > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > > --- > > arch/riscv/include/asm/hwcap.h | 3 +++ > > arch/riscv/kernel/cpufeature.c | 3 +++ > > 2 files changed, 6 insertions(+) > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index 869da082252a..14cc29f2a723 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -100,6 +100,9 @@ > > #define RISCV_ISA_EXT_ZICCRSE 91 > > #define RISCV_ISA_EXT_SVADE 92 > > #define RISCV_ISA_EXT_SVADU 93 > > +#define RISCV_ISA_EXT_ZFBFMIN 94 > > +#define RISCV_ISA_EXT_ZVFBFMIN 95 > > +#define RISCV_ISA_EXT_ZVFBFWMA 96 > > > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index c0916ed318c2..5cfcab139568 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -341,6 +341,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > > __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), > > __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS), > > __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), > > + __RISCV_ISA_EXT_DATA(zfbfmin, RISCV_ISA_EXT_ZFBFMIN), > > Hi Inochi, > > You could add a validation callback to that extension: > > static int riscv_ext_f_depends(const struct riscv_isa_ext_data *data, > const unsigned long *isa_bitmap) > { > if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) > return 0; > > return -EPROBE_DEFER; > } > > ... > __RISCV_ISA_EXT_DATA_VALIDATE(zfbfmin, RISCV_ISA_EXT_ZFBFMIN, > riscv_ext_f_depends), > > > But I'm ok with the current state of that patch since I have the same > thing coming for other extensions as well. I think it is good for me to add the check, and I wonder it is possible to add the extra check for zvfbfmin and zvfbfwma like this: static int riscv_ext_zvfbfmin_validate(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_v)) return 0; if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVE32F)) return 0; return -EPROBE_DEFER; } static int riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZFBFMIN) && __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVFBFMIN)) return 0; return -EPROBE_DEFER; } > So with or without my previous comment fixed: > > Reviewed-by: Clément Léger <cleger@rivosinc.com> > > Thanks, > > Clément > Thanks, Regards, Inochi > > __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), > > __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), > > __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA), > > @@ -373,6 +374,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > > __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), > > __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), > > __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), > > + __RISCV_ISA_EXT_DATA(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN), > > + __RISCV_ISA_EXT_DATA(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA), > > __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), > > __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), > > __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension 2025-02-11 0:42 ` Inochi Amaoto @ 2025-02-11 13:45 ` Conor Dooley 2025-02-11 23:26 ` Inochi Amaoto 0 siblings, 1 reply; 15+ messages in thread From: Conor Dooley @ 2025-02-11 13:45 UTC (permalink / raw) To: Inochi Amaoto Cc: Clément Léger, linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan, Longbin Li, Jesse Taube, Yong-Xuan Wang, Samuel Holland, Krzysztof Kozlowski, Evan Green, Andrew Jones, Alexandre Ghiti, Andy Chiu, Charlie Jenkins, Conor Dooley, Rob Herring, Albert Ou, Palmer Dabbelt, Paul Walmsley, Jonathan Corbet, Chen Wang [-- Attachment #1: Type: text/plain, Size: 4447 bytes --] On Tue, Feb 11, 2025 at 08:42:39AM +0800, Inochi Amaoto wrote: > On Mon, Feb 10, 2025 at 03:38:58PM +0100, Clément Léger wrote: > > > > > > On 06/12/2024 06:58, Inochi Amaoto wrote: > > > Add parsing for Zfbmin, Zvfbfmin, Zvfbfwma ISA extension which > > > were ratified in 4dc23d62 ("Added Chapter title to BF16") of > > > the riscv-isa-manual. > > > > > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > > > --- > > > arch/riscv/include/asm/hwcap.h | 3 +++ > > > arch/riscv/kernel/cpufeature.c | 3 +++ > > > 2 files changed, 6 insertions(+) > > > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > > index 869da082252a..14cc29f2a723 100644 > > > --- a/arch/riscv/include/asm/hwcap.h > > > +++ b/arch/riscv/include/asm/hwcap.h > > > @@ -100,6 +100,9 @@ > > > #define RISCV_ISA_EXT_ZICCRSE 91 > > > #define RISCV_ISA_EXT_SVADE 92 > > > #define RISCV_ISA_EXT_SVADU 93 > > > +#define RISCV_ISA_EXT_ZFBFMIN 94 > > > +#define RISCV_ISA_EXT_ZVFBFMIN 95 > > > +#define RISCV_ISA_EXT_ZVFBFWMA 96 > > > > > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > > index c0916ed318c2..5cfcab139568 100644 > > > --- a/arch/riscv/kernel/cpufeature.c > > > +++ b/arch/riscv/kernel/cpufeature.c > > > @@ -341,6 +341,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > > > __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), > > > __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS), > > > __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), > > > + __RISCV_ISA_EXT_DATA(zfbfmin, RISCV_ISA_EXT_ZFBFMIN), > > > > Hi Inochi, > > > > You could add a validation callback to that extension: > > > > static int riscv_ext_f_depends(const struct riscv_isa_ext_data *data, > > const unsigned long *isa_bitmap) > > { > > if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) > > return 0; > > > > return -EPROBE_DEFER; > > } > > > > ... > > __RISCV_ISA_EXT_DATA_VALIDATE(zfbfmin, RISCV_ISA_EXT_ZFBFMIN, > > riscv_ext_f_depends), > > > > > > But I'm ok with the current state of that patch since I have the same > > thing coming for other extensions as well. > > > I think it is good for me to add the check, and I wonder it is possible > to add the extra check for zvfbfmin and zvfbfwma like this: > > static int riscv_ext_zvfbfmin_validate(const struct riscv_isa_ext_data *data, > const unsigned long *isa_bitmap) > { > if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_v)) > return 0; This is not needed I think, V "turns on" Zve32f. If anything, you should be checking for CONFIG_RISCV_ISA_V here ^^ You /could/ call the resulting riscv_vector_f_validate(), since this is nothing specific to Zvfvfmin, and could be used for another extension that requires a Zve32f or Zve64 minimum base. > > if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVE32F)) > return 0; > > return -EPROBE_DEFER; > } > > static int riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data *data, > const unsigned long *isa_bitmap) > { > if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZFBFMIN) && > __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVFBFMIN)) > return 0; > > return -EPROBE_DEFER; > } > > > So with or without my previous comment fixed: > > > > Reviewed-by: Clément Léger <cleger@rivosinc.com> > > > > Thanks, > > > > Clément > > > > Thanks, > > Regards, > Inochi > > > > __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), > > > __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), > > > __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA), > > > @@ -373,6 +374,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > > > __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), > > > __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), > > > __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), > > > + __RISCV_ISA_EXT_DATA(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN), > > > + __RISCV_ISA_EXT_DATA(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA), > > > __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), > > > __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), > > > __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), > > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension 2025-02-11 13:45 ` Conor Dooley @ 2025-02-11 23:26 ` Inochi Amaoto 0 siblings, 0 replies; 15+ messages in thread From: Inochi Amaoto @ 2025-02-11 23:26 UTC (permalink / raw) To: Conor Dooley, Inochi Amaoto Cc: Clément Léger, linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan, Longbin Li, Jesse Taube, Yong-Xuan Wang, Samuel Holland, Krzysztof Kozlowski, Evan Green, Andrew Jones, Alexandre Ghiti, Andy Chiu, Charlie Jenkins, Conor Dooley, Rob Herring, Albert Ou, Palmer Dabbelt, Paul Walmsley, Jonathan Corbet, Chen Wang On Tue, Feb 11, 2025 at 01:45:06PM +0000, Conor Dooley wrote: > On Tue, Feb 11, 2025 at 08:42:39AM +0800, Inochi Amaoto wrote: > > On Mon, Feb 10, 2025 at 03:38:58PM +0100, Clément Léger wrote: > > > > > > > > > On 06/12/2024 06:58, Inochi Amaoto wrote: > > > > Add parsing for Zfbmin, Zvfbfmin, Zvfbfwma ISA extension which > > > > were ratified in 4dc23d62 ("Added Chapter title to BF16") of > > > > the riscv-isa-manual. > > > > > > > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > > > > --- > > > > arch/riscv/include/asm/hwcap.h | 3 +++ > > > > arch/riscv/kernel/cpufeature.c | 3 +++ > > > > 2 files changed, 6 insertions(+) > > > > > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > > > index 869da082252a..14cc29f2a723 100644 > > > > --- a/arch/riscv/include/asm/hwcap.h > > > > +++ b/arch/riscv/include/asm/hwcap.h > > > > @@ -100,6 +100,9 @@ > > > > #define RISCV_ISA_EXT_ZICCRSE 91 > > > > #define RISCV_ISA_EXT_SVADE 92 > > > > #define RISCV_ISA_EXT_SVADU 93 > > > > +#define RISCV_ISA_EXT_ZFBFMIN 94 > > > > +#define RISCV_ISA_EXT_ZVFBFMIN 95 > > > > +#define RISCV_ISA_EXT_ZVFBFWMA 96 > > > > > > > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > > > > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > > > index c0916ed318c2..5cfcab139568 100644 > > > > --- a/arch/riscv/kernel/cpufeature.c > > > > +++ b/arch/riscv/kernel/cpufeature.c > > > > @@ -341,6 +341,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > > > > __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), > > > > __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS), > > > > __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), > > > > + __RISCV_ISA_EXT_DATA(zfbfmin, RISCV_ISA_EXT_ZFBFMIN), > > > > > > Hi Inochi, > > > > > > You could add a validation callback to that extension: > > > > > > static int riscv_ext_f_depends(const struct riscv_isa_ext_data *data, > > > const unsigned long *isa_bitmap) > > > { > > > if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) > > > return 0; > > > > > > return -EPROBE_DEFER; > > > } > > > > > > ... > > > __RISCV_ISA_EXT_DATA_VALIDATE(zfbfmin, RISCV_ISA_EXT_ZFBFMIN, > > > riscv_ext_f_depends), > > > > > > > > > But I'm ok with the current state of that patch since I have the same > > > thing coming for other extensions as well. > > > > > > I think it is good for me to add the check, and I wonder it is possible > > to add the extra check for zvfbfmin and zvfbfwma like this: > > > > static int riscv_ext_zvfbfmin_validate(const struct riscv_isa_ext_data *data, > > const unsigned long *isa_bitmap) > > { > > if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_v)) > > return 0; > > This is not needed I think, V "turns on" Zve32f. If anything, you should > be checking for CONFIG_RISCV_ISA_V here ^^ > Thanks for pointing it. I will change the check. > You /could/ call the resulting riscv_vector_f_validate(), since this is > nothing specific to Zvfvfmin, and could be used for another extension > that requires a Zve32f or Zve64 minimum base. > It is OK for me, I will change its name. Regards, Inochi ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 3/3] riscv: hwprobe: export bfloat16 ISA extension 2024-12-06 5:58 [PATCH v3 0/3] riscv: Add bfloat16 instruction support Inochi Amaoto 2024-12-06 5:58 ` [PATCH v3 1/3] dt-bindings: riscv: add bfloat16 ISA extension description Inochi Amaoto 2024-12-06 5:58 ` [PATCH v3 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension Inochi Amaoto @ 2024-12-06 5:58 ` Inochi Amaoto 2024-12-16 16:00 ` Yangyu Chen 2025-03-27 3:24 ` [PATCH v3 0/3] riscv: Add bfloat16 instruction support patchwork-bot+linux-riscv 3 siblings, 1 reply; 15+ messages in thread From: Inochi Amaoto @ 2024-12-06 5:58 UTC (permalink / raw) To: Chen Wang, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Clément Léger, Evan Green, Charlie Jenkins, Andrew Jones, Jesse Taube, Andy Chiu, Alexandre Ghiti, Inochi Amaoto, Samuel Holland, Yong-Xuan Wang Cc: linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan, Longbin Li Export Zfbmin, Zvfbfmin, Zvfbfwma ISA extension through hwprobe. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Reviewed-by: Clément Léger <cleger@rivosinc.com> --- Documentation/arch/riscv/hwprobe.rst | 12 ++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 3 +++ arch/riscv/kernel/sys_hwprobe.c | 3 +++ 3 files changed, 18 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 955fbcd19ce9..a9cb40e407a4 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -242,6 +242,18 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as defined in version 1.0 of the RISC-V Pointer Masking extensions. + * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as + defined in the RISC-V ISA manual starting from commit 4dc23d6229de + ("Added Chapter title to BF16"). + + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as + defined in the RISC-V ISA manual starting from commit 4dc23d6229de + ("Added Chapter title to BF16"). + + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as + defined in the RISC-V ISA manual starting from commit 4dc23d6229de + ("Added Chapter title to BF16"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 3af142b99f77..aecc1c800d54 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -73,6 +73,9 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) #define RISCV_HWPROBE_EXT_SUPM (1ULL << 49) +#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 50) +#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 51) +#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 52) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index cb93adfffc48..bd215f58bd1b 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -131,6 +131,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZVE64D); EXT_KEY(ZVE64F); EXT_KEY(ZVE64X); + EXT_KEY(ZVFBFMIN); + EXT_KEY(ZVFBFWMA); EXT_KEY(ZVFH); EXT_KEY(ZVFHMIN); EXT_KEY(ZVKB); @@ -147,6 +149,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZCD); EXT_KEY(ZCF); EXT_KEY(ZFA); + EXT_KEY(ZFBFMIN); EXT_KEY(ZFH); EXT_KEY(ZFHMIN); } -- 2.47.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 3/3] riscv: hwprobe: export bfloat16 ISA extension 2024-12-06 5:58 ` [PATCH v3 3/3] riscv: hwprobe: export " Inochi Amaoto @ 2024-12-16 16:00 ` Yangyu Chen 2024-12-17 0:40 ` Inochi Amaoto 0 siblings, 1 reply; 15+ messages in thread From: Yangyu Chen @ 2024-12-16 16:00 UTC (permalink / raw) To: Inochi Amaoto, Chen Wang, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Clément Léger, Evan Green, Charlie Jenkins, Andrew Jones, Jesse Taube, Andy Chiu, Alexandre Ghiti, Samuel Holland, Yong-Xuan Wang Cc: linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan, Longbin Li Possible conflict with: https://lore.kernel.org/linux-riscv/20241111-v5_user_cfi_series-v8-22-dce14aa30207@rivosinc.com/ On 12/6/24 13:58, Inochi Amaoto wrote: > Export Zfbmin, Zvfbfmin, Zvfbfwma ISA extension through hwprobe. > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > Reviewed-by: Clément Léger <cleger@rivosinc.com> > --- > Documentation/arch/riscv/hwprobe.rst | 12 ++++++++++++ > arch/riscv/include/uapi/asm/hwprobe.h | 3 +++ > arch/riscv/kernel/sys_hwprobe.c | 3 +++ > 3 files changed, 18 insertions(+) > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > index 955fbcd19ce9..a9cb40e407a4 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -242,6 +242,18 @@ The following keys are defined: > * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as > defined in version 1.0 of the RISC-V Pointer Masking extensions. > > + * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as > + defined in the RISC-V ISA manual starting from commit 4dc23d6229de > + ("Added Chapter title to BF16"). > + > + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as > + defined in the RISC-V ISA manual starting from commit 4dc23d6229de > + ("Added Chapter title to BF16"). > + > + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as > + defined in the RISC-V ISA manual starting from commit 4dc23d6229de > + ("Added Chapter title to BF16"). > + > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to > :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was > mistakenly classified as a bitmask rather than a value. > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 3af142b99f77..aecc1c800d54 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -73,6 +73,9 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) > #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) > #define RISCV_HWPROBE_EXT_SUPM (1ULL << 49) > +#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 50) > +#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 51) > +#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 52) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > index cb93adfffc48..bd215f58bd1b 100644 > --- a/arch/riscv/kernel/sys_hwprobe.c > +++ b/arch/riscv/kernel/sys_hwprobe.c > @@ -131,6 +131,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > EXT_KEY(ZVE64D); > EXT_KEY(ZVE64F); > EXT_KEY(ZVE64X); > + EXT_KEY(ZVFBFMIN); > + EXT_KEY(ZVFBFWMA); > EXT_KEY(ZVFH); > EXT_KEY(ZVFHMIN); > EXT_KEY(ZVKB); > @@ -147,6 +149,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > EXT_KEY(ZCD); > EXT_KEY(ZCF); > EXT_KEY(ZFA); > + EXT_KEY(ZFBFMIN); > EXT_KEY(ZFH); > EXT_KEY(ZFHMIN); > } ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 3/3] riscv: hwprobe: export bfloat16 ISA extension 2024-12-16 16:00 ` Yangyu Chen @ 2024-12-17 0:40 ` Inochi Amaoto 2024-12-17 12:11 ` Conor Dooley 0 siblings, 1 reply; 15+ messages in thread From: Inochi Amaoto @ 2024-12-17 0:40 UTC (permalink / raw) To: Yangyu Chen, Inochi Amaoto, Chen Wang, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Clément Léger, Evan Green, Charlie Jenkins, Andrew Jones, Jesse Taube, Andy Chiu, Alexandre Ghiti, Samuel Holland, Yong-Xuan Wang Cc: linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan, Longbin Li On Tue, Dec 17, 2024 at 12:00:23AM +0800, Yangyu Chen wrote: > Possible conflict with: https://lore.kernel.org/linux-riscv/20241111-v5_user_cfi_series-v8-22-dce14aa30207@rivosinc.com/ > Yeah, I know the conflict. As the time of merging these patch is uncertain, what I can do now is to match the upstream code. Regards, Inochi > On 12/6/24 13:58, Inochi Amaoto wrote: > > Export Zfbmin, Zvfbfmin, Zvfbfwma ISA extension through hwprobe. > > > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com> > > Reviewed-by: Clément Léger <cleger@rivosinc.com> > > --- > > Documentation/arch/riscv/hwprobe.rst | 12 ++++++++++++ > > arch/riscv/include/uapi/asm/hwprobe.h | 3 +++ > > arch/riscv/kernel/sys_hwprobe.c | 3 +++ > > 3 files changed, 18 insertions(+) > > > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > > index 955fbcd19ce9..a9cb40e407a4 100644 > > --- a/Documentation/arch/riscv/hwprobe.rst > > +++ b/Documentation/arch/riscv/hwprobe.rst > > @@ -242,6 +242,18 @@ The following keys are defined: > > * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as > > defined in version 1.0 of the RISC-V Pointer Masking extensions. > > + * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as > > + defined in the RISC-V ISA manual starting from commit 4dc23d6229de > > + ("Added Chapter title to BF16"). > > + > > + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as > > + defined in the RISC-V ISA manual starting from commit 4dc23d6229de > > + ("Added Chapter title to BF16"). > > + > > + * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as > > + defined in the RISC-V ISA manual starting from commit 4dc23d6229de > > + ("Added Chapter title to BF16"). > > + > > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to > > :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was > > mistakenly classified as a bitmask rather than a value. > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > > index 3af142b99f77..aecc1c800d54 100644 > > --- a/arch/riscv/include/uapi/asm/hwprobe.h > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > > @@ -73,6 +73,9 @@ struct riscv_hwprobe { > > #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) > > #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) > > #define RISCV_HWPROBE_EXT_SUPM (1ULL << 49) > > +#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 50) > > +#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 51) > > +#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 52) > > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > > index cb93adfffc48..bd215f58bd1b 100644 > > --- a/arch/riscv/kernel/sys_hwprobe.c > > +++ b/arch/riscv/kernel/sys_hwprobe.c > > @@ -131,6 +131,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > > EXT_KEY(ZVE64D); > > EXT_KEY(ZVE64F); > > EXT_KEY(ZVE64X); > > + EXT_KEY(ZVFBFMIN); > > + EXT_KEY(ZVFBFWMA); > > EXT_KEY(ZVFH); > > EXT_KEY(ZVFHMIN); > > EXT_KEY(ZVKB); > > @@ -147,6 +149,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > > EXT_KEY(ZCD); > > EXT_KEY(ZCF); > > EXT_KEY(ZFA); > > + EXT_KEY(ZFBFMIN); > > EXT_KEY(ZFH); > > EXT_KEY(ZFHMIN); > > } > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 3/3] riscv: hwprobe: export bfloat16 ISA extension 2024-12-17 0:40 ` Inochi Amaoto @ 2024-12-17 12:11 ` Conor Dooley 0 siblings, 0 replies; 15+ messages in thread From: Conor Dooley @ 2024-12-17 12:11 UTC (permalink / raw) To: Inochi Amaoto Cc: Yangyu Chen, Chen Wang, Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Clément Léger, Evan Green, Charlie Jenkins, Andrew Jones, Jesse Taube, Andy Chiu, Alexandre Ghiti, Samuel Holland, Yong-Xuan Wang, linux-doc, linux-riscv, linux-kernel, devicetree, Yixun Lan, Longbin Li [-- Attachment #1: Type: text/plain, Size: 496 bytes --] On Tue, Dec 17, 2024 at 08:40:37AM +0800, Inochi Amaoto wrote: > On Tue, Dec 17, 2024 at 12:00:23AM +0800, Yangyu Chen wrote: > > Possible conflict with: https://lore.kernel.org/linux-riscv/20241111-v5_user_cfi_series-v8-22-dce14aa30207@rivosinc.com/ > > > > Yeah, I know the conflict. As the time of merging these patch is > uncertain, what I can do now is to match the upstream code. The solution is to not worry about it. Palmer can resolve trivial numerical conflicts like this. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 0/3] riscv: Add bfloat16 instruction support 2024-12-06 5:58 [PATCH v3 0/3] riscv: Add bfloat16 instruction support Inochi Amaoto ` (2 preceding siblings ...) 2024-12-06 5:58 ` [PATCH v3 3/3] riscv: hwprobe: export " Inochi Amaoto @ 2025-03-27 3:24 ` patchwork-bot+linux-riscv 3 siblings, 0 replies; 15+ messages in thread From: patchwork-bot+linux-riscv @ 2025-03-27 3:24 UTC (permalink / raw) To: Inochi Amaoto Cc: linux-riscv, unicorn_wang, corbet, paul.walmsley, palmer, aou, robh, krzk+dt, conor+dt, cleger, evan, charlie, ajones, jesse, andybnac, alexghiti, samuel.holland, yongxuan.wang, linux-doc, linux-kernel, devicetree, dlan, looong.bin Hello: This series was applied to riscv/linux.git (for-next) by Alexandre Ghiti <alexghiti@rivosinc.com>: On Fri, 6 Dec 2024 13:58:26 +0800 you wrote: > Add description for the BFloat16 precision Floating-Point ISA extension, > (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62 > ("Added Chapter title to BF16") of the riscv-isa-manual. > > Changed from v2: > 1. rebase for v6.13-rc1 > > [...] Here is the summary with links: - [v3,1/3] dt-bindings: riscv: add bfloat16 ISA extension description https://git.kernel.org/riscv/c/35bc1883733c - [v3,2/3] riscv: add ISA extension parsing for bfloat16 ISA extension (no matching commit) - [v3,3/3] riscv: hwprobe: export bfloat16 ISA extension https://git.kernel.org/riscv/c/a4863e002cf0 You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2025-03-27 3:24 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-12-06 5:58 [PATCH v3 0/3] riscv: Add bfloat16 instruction support Inochi Amaoto 2024-12-06 5:58 ` [PATCH v3 1/3] dt-bindings: riscv: add bfloat16 ISA extension description Inochi Amaoto 2024-12-16 22:00 ` Samuel Holland 2024-12-16 22:51 ` Jessica Clarke 2024-12-19 0:36 ` Samuel Holland 2024-12-06 5:58 ` [PATCH v3 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension Inochi Amaoto 2025-02-10 14:38 ` Clément Léger 2025-02-11 0:42 ` Inochi Amaoto 2025-02-11 13:45 ` Conor Dooley 2025-02-11 23:26 ` Inochi Amaoto 2024-12-06 5:58 ` [PATCH v3 3/3] riscv: hwprobe: export " Inochi Amaoto 2024-12-16 16:00 ` Yangyu Chen 2024-12-17 0:40 ` Inochi Amaoto 2024-12-17 12:11 ` Conor Dooley 2025-03-27 3:24 ` [PATCH v3 0/3] riscv: Add bfloat16 instruction support patchwork-bot+linux-riscv
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