Re: [PATCH 12/14] iio: adc: rzg2l_adc: Add support for Renesas RZ/G3S

Jonathan Cameron
2024-12-03T22:08:16Z

On Tue, 3 Dec 2024 13:13:12 +0200
Claudiu <claudiu.beznea@tuxon.dev> wrote:

> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add ADC support for the Renesas RZ/G3S SoC. The key features of this IP
> include:
> - 9 channels, with one dedicated to reading the temperature reported by the
> Thermal Sensor Unit (TSU)
> - A different default ADCMP value, which is written to the ADM3 register.
> - Different default sampling rates
> - ADM3.ADSMP field is 8 bits wide
> - ADINT.INTEN field is 11 bits wide
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Hi Claudia,

This one and the others I haven't comment on look good to me.

Thanks,

Jonathan

> ---
> drivers/iio/adc/rzg2l_adc.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/iio/adc/rzg2l_adc.c b/drivers/iio/adc/rzg2l_adc.c
> index 634073e7241f..dd2ef8203966 100644
> --- a/drivers/iio/adc/rzg2l_adc.c
> +++ b/drivers/iio/adc/rzg2l_adc.c
> @@ -525,7 +525,16 @@ static const struct rzg2l_adc_hw_params rzg2l_hw_params = {
> .adivc = true
> };
>
> +static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
> + .num_channels = 9,
> + .default_adcmp = 0x1d,
> + .default_adsmp = { 0x7f, 0xff },
> + .adsmp_mask = GENMASK(7, 0),
> + .adint_inten_mask = GENMASK(11, 0),
> +};
> +
> static const struct of_device_id rzg2l_adc_match[] = {
> + { .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params },
> { .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params },
> { /* sentinel */ }
> };