[PATCH v2 1/1] dt-bindings: PCI: mobiveil: convert mobiveil-pcie.txt to yaml format

[PATCH v2 1/1] dt-bindings: PCI: mobiveil: convert mobiveil-pcie.txt to yaml format

[Frank Li]

Convert device tree binding doc mobiveil-pcie.txt to yaml format. Merge
layerscape-pcie-gen4.txt into this file.

Additional change:
- interrupt-names: "aer", "pme", "intr", which align order in examples.
- reg-names: csr_axi_slave, config_axi_slave, which align existed dts file.

Fix below CHECK_DTBS warning:
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dtb: /soc/pcie@3400000: failed to match any schema with compatible: ['fsl,lx2160a-pcie']

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Change from v1 to v2
- update MAINTEAINER file to fix below
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202412070127.BkBJhnZ4-lkp@intel.com/

>> Warning: MAINTAINERS references a file that doesn't exist: Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
>> Warning: MAINTAINERS references a file that doesn't exist: Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt

lx2160a r2 already don't use this IP. But someone still complain when I
try to remove old r1 support.

So convert to yaml file to avoid annoised CHECK_DTBS warnings.
---
 .../bindings/pci/layerscape-pcie-gen4.txt     |  52 ------
 .../bindings/pci/mbvl,gpex40-pcie.yaml        | 167 ++++++++++++++++++
 .../devicetree/bindings/pci/mobiveil-pcie.txt |  72 --------
 MAINTAINERS                                   |   3 +-
 4 files changed, 168 insertions(+), 126 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
 create mode 100644 Documentation/devicetree/bindings/pci/mbvl,gpex40-pcie.yaml
 delete mode 100644 Documentation/devicetree/bindings/pci/mobiveil-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
deleted file mode 100644
index b40fb5d15d3d9..0000000000000
--- a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-NXP Layerscape PCIe Gen4 controller
-
-This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
-the common properties defined in mobiveil-pcie.txt.
-
-Required properties:
-- compatible: should contain the platform identifier such as:
-  "fsl,lx2160a-pcie"
-- reg: base addresses and lengths of the PCIe controller register blocks.
-  "csr_axi_slave": Bridge config registers
-  "config_axi_slave": PCIe controller registers
-- interrupts: A list of interrupt outputs of the controller. Must contain an
-  entry for each entry in the interrupt-names property.
-- interrupt-names: It could include the following entries:
-  "intr": The interrupt that is asserted for controller interrupts
-  "aer": Asserted for aer interrupt when chip support the aer interrupt with
-	 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
-  "pme": Asserted for pme interrupt when chip support the pme interrupt with
-	 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
-- dma-coherent: Indicates that the hardware IP block can ensure the coherency
-  of the data transferred from/to the IP block. This can avoid the software
-  cache flush/invalid actions, and improve the performance significantly.
-- msi-parent : See the generic MSI binding described in
-  Documentation/devicetree/bindings/interrupt-controller/msi.txt.
-
-Example:
-
-	pcie@3400000 {
-		compatible = "fsl,lx2160a-pcie";
-		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
-		       0x80 0x00000000 0x0 0x00001000>; /* configuration space */
-		reg-names = "csr_axi_slave", "config_axi_slave";
-		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
-			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
-			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-		interrupt-names = "aer", "pme", "intr";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		apio-wins = <8>;
-		ppio-wins = <8>;
-		dma-coherent;
-		bus-range = <0x0 0xff>;
-		msi-parent = <&its>;
-		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-				<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-				<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-				<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-	};
diff --git a/Documentation/devicetree/bindings/pci/mbvl,gpex40-pcie.yaml b/Documentation/devicetree/bindings/pci/mbvl,gpex40-pcie.yaml
new file mode 100644
index 0000000000000..160ddc4bc45bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mbvl,gpex40-pcie.yaml
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mbvl,gpex40-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobiveil AXI PCIe Root Port Bridge
+
+maintainers:
+  - Frank Li <Frank Li@nxp.com>
+
+description:
+  Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
+  has up to 8 outbound and inbound windows for the address translation.
+
+  NXP Layerscape PCIe Gen4 controller (Deprecated) base on Mobiveil's GPEX 4.0.
+
+properties:
+  compatible:
+    enum:
+      - mbvl,gpex40-pcie
+      - fsl,lx2160a-pcie
+
+  reg:
+    items:
+      - description: PCIe controller registers
+      - description: Bridge config registers
+      - description: GPIO registers to control slot power
+      - description: MSI registers
+    minItems: 2
+
+  reg-names:
+    items:
+      - const: csr_axi_slave
+      - const: config_axi_slave
+      - const: gpio_slave
+      - const: apb_csr
+    minItems: 2
+
+  apio-wins:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      numbers of requested apio outbound windows
+        1. Config window
+        2. Memory window
+    default: 2
+    maximum: 256
+
+  ppio-wins:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: number of requested ppio inbound windows
+    default: 1
+    maximum: 256
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 1
+
+  interrupts:
+    minItems: 1
+    maxItems: 3
+
+  interrupt-names:
+    minItems: 1
+    maxItems: 3
+
+  dma-coherent: true
+
+  msi-parent: true
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+allOf:
+  - $ref: /schemas/pci/pci-host-bridge.yaml#
+  - if:
+      properties:
+        compatible:
+          enum:
+            - fsl,lx2160a-pcie
+    then:
+      properties:
+        reg:
+          maxItems: 2
+
+        reg-names:
+          maxItems: 2
+
+        interrupt-names:
+          items:
+            - const: aer
+            - const: pme
+            - const: intr
+    else:
+      properties:
+        dma-coherent: false
+        msi-parent: false
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    pcie@b0000000 {
+        compatible = "mbvl,gpex40-pcie";
+        reg = <0xb0000000 0x00010000>,
+              <0xa0000000 0x00001000>,
+              <0xff000000 0x00200000>,
+              <0xb0010000 0x00001000>;
+        reg-names = "csr_axi_slave",
+                    "config_axi_slave",
+                    "gpio_slave",
+                    "apb_csr";
+        #address-cells = <3>;
+        #size-cells = <2>;
+        device_type = "pci";
+        apio-wins = <2>;
+        ppio-wins = <1>;
+        bus-range = <0x00000000 0x000000ff>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-map-mask = <0 0 0 7>;
+        interrupt-map = <0 0 0 0 &pci_express 0>,
+                        <0 0 0 1 &pci_express 1>,
+                        <0 0 0 2 &pci_express 2>,
+                        <0 0 0 3 &pci_express 3>;
+        ranges = <0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
+    };
+
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        pcie@3400000 {
+            compatible = "fsl,lx2160a-pcie";
+            reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+                   0x80 0x00000000 0x0 0x00001000>; /* configuration space */
+            reg-names = "csr_axi_slave", "config_axi_slave";
+            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+                        <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+            interrupt-names = "aer", "pme", "intr";
+            #address-cells = <3>;
+            #size-cells = <2>;
+            device_type = "pci";
+            apio-wins = <8>;
+            ppio-wins = <8>;
+            dma-coherent;
+            bus-range = <0x0 0xff>;
+            msi-parent = <&its>;
+            ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 7>;
+            interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                            <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                            <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                            <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
deleted file mode 100644
index 64156993e052d..0000000000000
--- a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-* Mobiveil AXI PCIe Root Port Bridge DT description
-
-Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
-has up to 8 outbound and inbound windows for the address translation.
-
-Required properties:
-- #address-cells: Address representation for root ports, set to <3>
-- #size-cells: Size representation for root ports, set to <2>
-- #interrupt-cells: specifies the number of cells needed to encode an
-	interrupt source. The value must be 1.
-- compatible: Should contain "mbvl,gpex40-pcie"
-- reg: Should contain PCIe registers location and length
-	Mandatory:
-	"config_axi_slave": PCIe controller registers
-	"csr_axi_slave"	  : Bridge config registers
-	Optional:
-	"gpio_slave"	  : GPIO registers to control slot power
-	"apb_csr"	  : MSI registers
-
-- device_type: must be "pci"
-- apio-wins : number of requested apio outbound windows
-		default 2 outbound windows are configured -
-		1. Config window
-		2. Memory window
-- ppio-wins : number of requested ppio inbound windows
-		default 1 inbound memory window is configured.
-- bus-range: PCI bus numbers covered
-- interrupt-controller: identifies the node as an interrupt controller
-- #interrupt-cells: specifies the number of cells needed to encode an
-	interrupt source. The value must be 1.
-- interrupts: The interrupt line of the PCIe controller
-		last cell of this field is set to 4 to
-		denote it as IRQ_TYPE_LEVEL_HIGH type interrupt.
-- interrupt-map-mask,
-	interrupt-map: standard PCI properties to define the mapping of the
-	PCI interface to interrupt numbers.
-- ranges: ranges for the PCI memory regions (I/O space region is not
-	supported by hardware)
-	Please refer to the standard PCI bus binding document for a more
-	detailed explanation
-
-
-Example:
-++++++++
-	pcie0: pcie@a0000000 {
-		#address-cells = <3>;
-		#size-cells = <2>;
-		compatible = "mbvl,gpex40-pcie";
-		reg =	<0xa0000000 0x00001000>,
-			<0xb0000000 0x00010000>,
-			<0xff000000 0x00200000>,
-			<0xb0010000 0x00001000>;
-		reg-names =	"config_axi_slave",
-				"csr_axi_slave",
-				"gpio_slave",
-				"apb_csr";
-		device_type = "pci";
-		apio-wins = <2>;
-		ppio-wins = <1>;
-		bus-range = <0x00000000 0x000000ff>;
-		interrupt-controller;
-		interrupt-parent = <&gic>;
-		#interrupt-cells = <1>;
-		interrupts = < 0 89 4 >;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 0 &pci_express 0>,
-				<0 0 0 1 &pci_express 1>,
-				<0 0 0 2 &pci_express 2>,
-				<0 0 0 3 &pci_express 3>;
-		ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
-
-	};
diff --git a/MAINTAINERS b/MAINTAINERS
index 1e930c7a58b13..e0fcdd8b6434c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17901,7 +17901,7 @@ M:	Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
 M:	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
 L:	linux-pci@vger.kernel.org
 S:	Supported
-F:	Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
+F:	Documentation/devicetree/bindings/pci/mbvl,gpex40-pcie.yaml
 F:	drivers/pci/controller/mobiveil/pcie-mobiveil*
 
 PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)
@@ -17925,7 +17925,6 @@ M:	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
 L:	linux-pci@vger.kernel.org
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
-F:	Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
 F:	drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
 
 PCI DRIVER FOR PLDA PCIE IP
-- 
2.34.1

Re: [PATCH v2 1/1] dt-bindings: PCI: mobiveil: convert mobiveil-pcie.txt to yaml format

[Bjorn Helgaas]

On Fri, Dec 06, 2024 at 05:25:27PM -0500, Frank Li wrote:
> Convert device tree binding doc mobiveil-pcie.txt to yaml format. Merge
> layerscape-pcie-gen4.txt into this file.
> 
> Additional change:
> - interrupt-names: "aer", "pme", "intr", which align order in examples.
> - reg-names: csr_axi_slave, config_axi_slave, which align existed dts file.

Is there any way to split this into two patches:

  - Convert to yaml and update MAINTAINERS
  - Update interrupt-names, reg-names

It's hard to review the interrupt-names, reg-names when they're mixed
in with the yaml conversion.

Re: [PATCH v2 1/1] dt-bindings: PCI: mobiveil: convert mobiveil-pcie.txt to yaml format

[Krzysztof Kozlowski]

On Mon, Dec 09, 2024 at 05:51:21PM -0600, Bjorn Helgaas wrote:
> On Fri, Dec 06, 2024 at 05:25:27PM -0500, Frank Li wrote:
> > Convert device tree binding doc mobiveil-pcie.txt to yaml format. Merge
> > layerscape-pcie-gen4.txt into this file.
> > 
> > Additional change:
> > - interrupt-names: "aer", "pme", "intr", which align order in examples.
> > - reg-names: csr_axi_slave, config_axi_slave, which align existed dts file.
> 
> Is there any way to split this into two patches:
> 
>   - Convert to yaml and update MAINTAINERS
>   - Update interrupt-names, reg-names
> 
> It's hard to review the interrupt-names, reg-names when they're mixed
> in with the yaml conversion.

The conversion should result in a correct binding, so if original
binding had some issues (and TXT bindings often have: missing or
stale/not-udpated properties), then we expect any fixes in the same
commit.  New things, not supported by existing in-kernel upstream users
or bindings, should be of course in separate patch.

Best regards,
Krzysztof

Re: [PATCH v2 1/1] dt-bindings: PCI: mobiveil: convert mobiveil-pcie.txt to yaml format

[Krzysztof Kozlowski]

On Fri, Dec 06, 2024 at 05:25:27PM -0500, Frank Li wrote:
> Convert device tree binding doc mobiveil-pcie.txt to yaml format. Merge
> layerscape-pcie-gen4.txt into this file.
> 
> Additional change:
> - interrupt-names: "aer", "pme", "intr", which align order in examples.
> - reg-names: csr_axi_slave, config_axi_slave, which align existed dts file.

mobiveil-pcie.txt binding suggested reversed orders of above, so please
mention that you unify the order to match layerscape-pcie-gen4 and
existing Layerscape DTS users.


...


> +++ b/Documentation/devicetree/bindings/pci/mbvl,gpex40-pcie.yaml
> @@ -0,0 +1,167 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/mbvl,gpex40-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mobiveil AXI PCIe Root Port Bridge
> +
> +maintainers:
> +  - Frank Li <Frank Li@nxp.com>
> +
> +description:
> +  Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
> +  has up to 8 outbound and inbound windows for the address translation.
> +
> +  NXP Layerscape PCIe Gen4 controller (Deprecated) base on Mobiveil's GPEX 4.0.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - mbvl,gpex40-pcie
> +      - fsl,lx2160a-pcie

Please reverse them to keep alphabetical order.

> +
> +  reg:
> +    items:
> +      - description: PCIe controller registers
> +      - description: Bridge config registers
> +      - description: GPIO registers to control slot power
> +      - description: MSI registers
> +    minItems: 2
> +
> +  reg-names:
> +    items:
> +      - const: csr_axi_slave
> +      - const: config_axi_slave
> +      - const: gpio_slave
> +      - const: apb_csr
> +    minItems: 2
> +
> +  apio-wins:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: |
> +      numbers of requested apio outbound windows
> +        1. Config window
> +        2. Memory window
> +    default: 2
> +    maximum: 256
> +
> +  ppio-wins:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description: number of requested ppio inbound windows
> +    default: 1
> +    maximum: 256
> +
> +  interrupt-controller: true
> +
> +  "#interrupt-cells":
> +    const: 1
> +
> +  interrupts:
> +    minItems: 1
> +    maxItems: 3
> +
> +  interrupt-names:
> +    minItems: 1
> +    maxItems: 3
> +
> +  dma-coherent: true
> +
> +  msi-parent: true
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-host-bridge.yaml#
> +  - if:
> +      properties:
> +        compatible:
> +          enum:
> +            - fsl,lx2160a-pcie
> +    then:
> +      properties:
> +        reg:
> +          maxItems: 2
> +
> +        reg-names:
> +          maxItems: 2
> +

interrupts:
  minItems: 3

> +        interrupt-names:
> +          items:
> +            - const: aer
> +            - const: pme
> +            - const: intr
> +    else:
> +      properties:
> +        dma-coherent: false
> +        msi-parent: false

reg? interrupts? interrupt-names?



> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    pcie@b0000000 {
> +        compatible = "mbvl,gpex40-pcie";
> +        reg = <0xb0000000 0x00010000>,
> +              <0xa0000000 0x00001000>,
> +              <0xff000000 0x00200000>,
> +              <0xb0010000 0x00001000>;
> +        reg-names = "csr_axi_slave",
> +                    "config_axi_slave",
> +                    "gpio_slave",
> +                    "apb_csr";
> +        #address-cells = <3>;
> +        #size-cells = <2>;
> +        device_type = "pci";
> +        apio-wins = <2>;
> +        ppio-wins = <1>;
> +        bus-range = <0x00000000 0x000000ff>;
> +        interrupt-controller;
> +        #interrupt-cells = <1>;
> +        interrupt-parent = <&gic>;
> +        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-map-mask = <0 0 0 7>;
> +        interrupt-map = <0 0 0 0 &pci_express 0>,
> +                        <0 0 0 1 &pci_express 1>,
> +                        <0 0 0 2 &pci_express 2>,
> +                        <0 0 0 3 &pci_express 3>;
> +        ranges = <0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;

Please keep ranges after reg-names

> +    };
> +
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +        pcie@3400000 {
> +            compatible = "fsl,lx2160a-pcie";
> +            reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
> +                   0x80 0x00000000 0x0 0x00001000>; /* configuration space */
> +            reg-names = "csr_axi_slave", "config_axi_slave";
> +            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> +                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> +                        <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> +            interrupt-names = "aer", "pme", "intr";
> +            #address-cells = <3>;
> +            #size-cells = <2>;
> +            device_type = "pci";
> +            apio-wins = <8>;
> +            ppio-wins = <8>;
> +            dma-coherent;
> +            bus-range = <0x0 0xff>;
> +            msi-parent = <&its>;
> +            ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;

Ditto here

> +            #interrupt-cells = <1>;
> +            interrupt-map-mask = <0 0 0 7>;
> +            interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> +                            <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> +                            <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> +                            <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> +        };

Best regards,
Krzysztof

Re: [PATCH v2 1/1] dt-bindings: PCI: mobiveil: convert mobiveil-pcie.txt to yaml format

[Bjorn Helgaas]

On Tue, Dec 10, 2024 at 09:42:31AM +0100, Krzysztof Kozlowski wrote:
> On Mon, Dec 09, 2024 at 05:51:21PM -0600, Bjorn Helgaas wrote:
> > On Fri, Dec 06, 2024 at 05:25:27PM -0500, Frank Li wrote:
> > > Convert device tree binding doc mobiveil-pcie.txt to yaml format. Merge
> > > layerscape-pcie-gen4.txt into this file.
> > > 
> > > Additional change:
> > > - interrupt-names: "aer", "pme", "intr", which align order in examples.
> > > - reg-names: csr_axi_slave, config_axi_slave, which align existed dts file.
> > 
> > Is there any way to split this into two patches:
> > 
> >   - Convert to yaml and update MAINTAINERS
> >   - Update interrupt-names, reg-names
> > 
> > It's hard to review the interrupt-names, reg-names when they're mixed
> > in with the yaml conversion.
> 
> The conversion should result in a correct binding, so if original
> binding had some issues (and TXT bindings often have: missing or
> stale/not-udpated properties), then we expect any fixes in the same
> commit.  New things, not supported by existing in-kernel upstream users
> or bindings, should be of course in separate patch.

Maybe they could be added to the original TXT binding first in one
patch, and then converted to yaml in a second patch?

Re: [PATCH v2 1/1] dt-bindings: PCI: mobiveil: convert mobiveil-pcie.txt to yaml format

[Frank Li]

On Tue, Dec 10, 2024 at 09:52:47AM +0100, Krzysztof Kozlowski wrote:
> On Fri, Dec 06, 2024 at 05:25:27PM -0500, Frank Li wrote:
> > Convert device tree binding doc mobiveil-pcie.txt to yaml format. Merge
> > layerscape-pcie-gen4.txt into this file.
> >
> > Additional change:
> > - interrupt-names: "aer", "pme", "intr", which align order in examples.
> > - reg-names: csr_axi_slave, config_axi_slave, which align existed dts file.
>
> mobiveil-pcie.txt binding suggested reversed orders of above, so please
> mention that you unify the order to match layerscape-pcie-gen4 and
> existing Layerscape DTS users.
>
>
> ...
>
>
> > +++ b/Documentation/devicetree/bindings/pci/mbvl,gpex40-pcie.yaml
> > @@ -0,0 +1,167 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/mbvl,gpex40-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mobiveil AXI PCIe Root Port Bridge
> > +
> > +maintainers:
> > +  - Frank Li <Frank Li@nxp.com>
> > +
> > +description:
> > +  Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
> > +  has up to 8 outbound and inbound windows for the address translation.
> > +
> > +  NXP Layerscape PCIe Gen4 controller (Deprecated) base on Mobiveil's GPEX 4.0.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - mbvl,gpex40-pcie
> > +      - fsl,lx2160a-pcie
>
> Please reverse them to keep alphabetical order.
>
> > +
> > +  reg:
> > +    items:
> > +      - description: PCIe controller registers
> > +      - description: Bridge config registers
> > +      - description: GPIO registers to control slot power
> > +      - description: MSI registers
> > +    minItems: 2
> > +
> > +  reg-names:
> > +    items:
> > +      - const: csr_axi_slave
> > +      - const: config_axi_slave
> > +      - const: gpio_slave
> > +      - const: apb_csr
> > +    minItems: 2
> > +
> > +  apio-wins:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description: |
> > +      numbers of requested apio outbound windows
> > +        1. Config window
> > +        2. Memory window
> > +    default: 2
> > +    maximum: 256
> > +
> > +  ppio-wins:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description: number of requested ppio inbound windows
> > +    default: 1
> > +    maximum: 256
> > +
> > +  interrupt-controller: true
> > +
> > +  "#interrupt-cells":
> > +    const: 1
> > +
> > +  interrupts:
> > +    minItems: 1
> > +    maxItems: 3
> > +
> > +  interrupt-names:
> > +    minItems: 1
> > +    maxItems: 3
> > +
> > +  dma-coherent: true
> > +
> > +  msi-parent: true
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +
> > +allOf:
> > +  - $ref: /schemas/pci/pci-host-bridge.yaml#
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          enum:
> > +            - fsl,lx2160a-pcie
> > +    then:
> > +      properties:
> > +        reg:
> > +          maxItems: 2
> > +
> > +        reg-names:
> > +          maxItems: 2
> > +
>
> interrupts:
>   minItems: 3
>
> > +        interrupt-names:
> > +          items:
> > +            - const: aer
> > +            - const: pme
> > +            - const: intr
> > +    else:
> > +      properties:
> > +        dma-coherent: false
> > +        msi-parent: false
>
> reg? interrupts? interrupt-names?

mbvl,gpex40-pcie text file descript reg as

Mandatory:
  "config_axi_slave": PCIe controller registers
  "csr_axi_slave"	  : Bridge config registers
Optional:
  "gpio_slave"	  : GPIO registers to control slot power
  "apb_csr"	  : MSI registers

reg have set minItems 2 and maxItems 4 at top. So needn't set it again.

I will add interrupts and interrupt-names.

Frank

>
>
>
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +    pcie@b0000000 {
> > +        compatible = "mbvl,gpex40-pcie";
> > +        reg = <0xb0000000 0x00010000>,
> > +              <0xa0000000 0x00001000>,
> > +              <0xff000000 0x00200000>,
> > +              <0xb0010000 0x00001000>;
> > +        reg-names = "csr_axi_slave",
> > +                    "config_axi_slave",
> > +                    "gpio_slave",
> > +                    "apb_csr";
> > +        #address-cells = <3>;
> > +        #size-cells = <2>;
> > +        device_type = "pci";
> > +        apio-wins = <2>;
> > +        ppio-wins = <1>;
> > +        bus-range = <0x00000000 0x000000ff>;
> > +        interrupt-controller;
> > +        #interrupt-cells = <1>;
> > +        interrupt-parent = <&gic>;
> > +        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > +        interrupt-map-mask = <0 0 0 7>;
> > +        interrupt-map = <0 0 0 0 &pci_express 0>,
> > +                        <0 0 0 1 &pci_express 1>,
> > +                        <0 0 0 2 &pci_express 2>,
> > +                        <0 0 0 3 &pci_express 3>;
> > +        ranges = <0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
>
> Please keep ranges after reg-names
>
> > +    };
> > +
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +    soc {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +        pcie@3400000 {
> > +            compatible = "fsl,lx2160a-pcie";
> > +            reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
> > +                   0x80 0x00000000 0x0 0x00001000>; /* configuration space */
> > +            reg-names = "csr_axi_slave", "config_axi_slave";
> > +            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
> > +                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
> > +                        <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> > +            interrupt-names = "aer", "pme", "intr";
> > +            #address-cells = <3>;
> > +            #size-cells = <2>;
> > +            device_type = "pci";
> > +            apio-wins = <8>;
> > +            ppio-wins = <8>;
> > +            dma-coherent;
> > +            bus-range = <0x0 0xff>;
> > +            msi-parent = <&its>;
> > +            ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
>
> Ditto here
>
> > +            #interrupt-cells = <1>;
> > +            interrupt-map-mask = <0 0 0 7>;
> > +            interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> > +        };
>
> Best regards,
> Krzysztof
>

Re: [PATCH v2 1/1] dt-bindings: PCI: mobiveil: convert mobiveil-pcie.txt to yaml format

[Krzysztof Kozlowski]

On 10/12/2024 18:07, Bjorn Helgaas wrote:
> On Tue, Dec 10, 2024 at 09:42:31AM +0100, Krzysztof Kozlowski wrote:
>> On Mon, Dec 09, 2024 at 05:51:21PM -0600, Bjorn Helgaas wrote:
>>> On Fri, Dec 06, 2024 at 05:25:27PM -0500, Frank Li wrote:
>>>> Convert device tree binding doc mobiveil-pcie.txt to yaml format. Merge
>>>> layerscape-pcie-gen4.txt into this file.
>>>>
>>>> Additional change:
>>>> - interrupt-names: "aer", "pme", "intr", which align order in examples.
>>>> - reg-names: csr_axi_slave, config_axi_slave, which align existed dts file.
>>>
>>> Is there any way to split this into two patches:
>>>
>>>   - Convert to yaml and update MAINTAINERS
>>>   - Update interrupt-names, reg-names
>>>
>>> It's hard to review the interrupt-names, reg-names when they're mixed
>>> in with the yaml conversion.
>>
>> The conversion should result in a correct binding, so if original
>> binding had some issues (and TXT bindings often have: missing or
>> stale/not-udpated properties), then we expect any fixes in the same
>> commit.  New things, not supported by existing in-kernel upstream users
>> or bindings, should be of course in separate patch.
> 
> Maybe they could be added to the original TXT binding first in one
> patch, and then converted to yaml in a second patch?


This would solve one thing and cause another issues: you add lines in
one commit which are immediately removed in the next commit, plus we
don't want any changes in TXT because absolute lack of means for
verification/testing.


Best regards,
Krzysztof