[PATCH 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

[PATCH 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

[Lijuan Gao]

The UFS_RESET pin is expected to be wired to the reset pin of the
primary UFS memory, it's a general purpose output pin. Reorder it and
expose it as a gpio, so that the UFS driver can toggle it.

The QCS615 TLMM pin controller has GPIOs 0-122, so correct the
gpio-rangs to 124.

The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
gpio-rangs to 134.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
Lijuan Gao (6):
      dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
      dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
      pinctrl: qcom: correct the number of ngpios for QCS615
      pinctrl: qcom: correct the number of ngpios for QCS8300
      arm64: dts: qcom: correct gpio-ranges for QCS615
      arm64: dts: qcom: correct gpio-ranges for QCS8300

 Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml  | 2 +-
 Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 2 +-
 arch/arm64/boot/dts/qcom/qcs615.dtsi                             | 2 +-
 arch/arm64/boot/dts/qcom/qcs8300.dtsi                            | 2 +-
 drivers/pinctrl/qcom/pinctrl-qcs615.c                            | 2 +-
 drivers/pinctrl/qcom/pinctrl-qcs8300.c                           | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)
---
base-commit: 91e71d606356e50f238d7a87aacdee4abc427f07
change-id: 20241211-correct_gpio_ranges-ed8a25ad22e7

Best regards,
-- 
Lijuan Gao <quic_lijuang@quicinc.com>

[PATCH 1/6] dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615

[Lijuan Gao]

The QCS615 TLMM pin controller have the UFS_RESET pin, which is expected
to be wired to the reset pin of the primary UFS memory. Include it in
gpio-ranges so that the UFS driver can toggle it.

Fixes: 55c487ea6084 ("dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml
index 1ce4b5df584a..2791e578c1de 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml
@@ -110,7 +110,7 @@ examples:
               <0x03c00000 0x300000>;
         reg-names = "east", "west", "south";
         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
-        gpio-ranges = <&tlmm 0 0 123>;
+        gpio-ranges = <&tlmm 0 0 124>;
         gpio-controller;
         #gpio-cells = <2>;
         interrupt-controller;

-- 
2.46.0

[PATCH 2/6] dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300

[Lijuan Gao]

The QCS8300 TLMM pin controller have the UFS_RESET pin, which is expected
to be wired to the reset pin of the primary UFS memory. Include it in
gpio-ranges so that the UFS driver can toggle it.

Fixes: 5778535972e2 ("dt-bindings: pinctrl: describe qcs8300-tlmm")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml
index bb0d7132886a..489b41dcc179 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml
@@ -106,7 +106,7 @@ examples:
         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
         gpio-controller;
         #gpio-cells = <2>;
-        gpio-ranges = <&tlmm 0 0 133>;
+        gpio-ranges = <&tlmm 0 0 134>;
         interrupt-controller;
         #interrupt-cells = <2>;
 

-- 
2.46.0

[PATCH 3/6] pinctrl: qcom: correct the number of ngpios for QCS615

[Lijuan Gao]

The UFS_RESET pin is expected to be wired to the reset pin of the primary
UFS memory. Reorder the pins and expose it as a GPIO, so that the UFS
driver can toggle it. Therefore, correct the number of ngpios.

Fixes: b698f36a9d40 ("pinctrl: qcom: add the tlmm driver for QCS615 platform")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 drivers/pinctrl/qcom/pinctrl-qcs615.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qcs615.c b/drivers/pinctrl/qcom/pinctrl-qcs615.c
index 23015b055f6a..17ca743c2210 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs615.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs615.c
@@ -1062,7 +1062,7 @@ static const struct msm_pinctrl_soc_data qcs615_tlmm = {
 	.nfunctions = ARRAY_SIZE(qcs615_functions),
 	.groups = qcs615_groups,
 	.ngroups = ARRAY_SIZE(qcs615_groups),
-	.ngpios = 123,
+	.ngpios = 124,
 	.tiles = qcs615_tiles,
 	.ntiles = ARRAY_SIZE(qcs615_tiles),
 	.wakeirq_map = qcs615_pdc_map,

-- 
2.46.0

[PATCH 4/6] pinctrl: qcom: correct the number of ngpios for QCS8300

[Lijuan Gao]

The UFS_RESET pin is expected to be wired to the reset pin of the primary
UFS memory. Reorder the pins and expose it as a GPIO, so that the UFS
driver can toggle it. Therefore, correct the number of ngpios.

Fixes: 0c4cd2cc87c8 ("pinctrl: qcom: add the tlmm driver for QCS8300 platforms")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 drivers/pinctrl/qcom/pinctrl-qcs8300.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qcs8300.c b/drivers/pinctrl/qcom/pinctrl-qcs8300.c
index ba6de944a859..5f5f7c4ac644 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs8300.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs8300.c
@@ -1204,7 +1204,7 @@ static const struct msm_pinctrl_soc_data qcs8300_pinctrl = {
 	.nfunctions = ARRAY_SIZE(qcs8300_functions),
 	.groups = qcs8300_groups,
 	.ngroups = ARRAY_SIZE(qcs8300_groups),
-	.ngpios = 133,
+	.ngpios = 134,
 	.wakeirq_map = qcs8300_pdc_map,
 	.nwakeirq_map = ARRAY_SIZE(qcs8300_pdc_map),
 	.egpio_func = 11,

-- 
2.46.0

[PATCH 5/6] arm64: dts: qcom: correct gpio-ranges for QCS615

[Lijuan Gao]

The QCS615 TLMM pin controller has GPIOs 0-122, it also has UFS_RESET
pin for primary UFS memory reset, so correct the gpio-ranges for the UFS
driver can toggle it.

Fixes: 8e266654a2fe ("arm64: dts: qcom: add QCS615 platform")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index c0e4b376a1c6..4c3d8e39ce0b 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -938,7 +938,7 @@ tlmm: pinctrl@3100000 {
 				    "west",
 				    "south";
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
-			gpio-ranges = <&tlmm 0 0 123>;
+			gpio-ranges = <&tlmm 0 0 124>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;

-- 
2.46.0

[PATCH 6/6] arm64: dts: qcom: correct gpio-ranges for QCS8300

[Lijuan Gao]

The QCS8300 TLMM pin controller has GPIOs 0-132, it also has UFS_RESET
pin for primary UFS memory reset, so correct the gpio-ranges for the UFS
driver can toggle it.

Fixes: 7be190e4bdd2 ("arm64: dts: qcom: add QCS8300 platform")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 73abf2ef9c9f..07d6d3ff4365 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -971,7 +971,7 @@ tlmm: pinctrl@f100000 {
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 			gpio-controller;
 			#gpio-cells = <2>;
-			gpio-ranges = <&tlmm 0 0 133>;
+			gpio-ranges = <&tlmm 0 0 134>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			wakeup-parent = <&pdc>;

-- 
2.46.0

Re: [PATCH 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

[Dmitry Baryshkov]

On Thu, Dec 12, 2024 at 05:23:59PM +0800, Lijuan Gao wrote:
> The UFS_RESET pin is expected to be wired to the reset pin of the
> primary UFS memory, it's a general purpose output pin. Reorder it and
> expose it as a gpio, so that the UFS driver can toggle it.

I don't see pins being reordered. Please correct your commit messages.

> 
> The QCS615 TLMM pin controller has GPIOs 0-122, so correct the
> gpio-rangs to 124.
> 
> The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
> gpio-rangs to 134.
> 
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---
> Lijuan Gao (6):
>       dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
>       dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
>       pinctrl: qcom: correct the number of ngpios for QCS615
>       pinctrl: qcom: correct the number of ngpios for QCS8300
>       arm64: dts: qcom: correct gpio-ranges for QCS615
>       arm64: dts: qcom: correct gpio-ranges for QCS8300
> 
>  Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml  | 2 +-
>  Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 2 +-
>  arch/arm64/boot/dts/qcom/qcs615.dtsi                             | 2 +-
>  arch/arm64/boot/dts/qcom/qcs8300.dtsi                            | 2 +-
>  drivers/pinctrl/qcom/pinctrl-qcs615.c                            | 2 +-
>  drivers/pinctrl/qcom/pinctrl-qcs8300.c                           | 2 +-
>  6 files changed, 6 insertions(+), 6 deletions(-)
> ---
> base-commit: 91e71d606356e50f238d7a87aacdee4abc427f07
> change-id: 20241211-correct_gpio_ranges-ed8a25ad22e7
> 
> Best regards,
> -- 
> Lijuan Gao <quic_lijuang@quicinc.com>
> 

-- 
With best wishes
Dmitry

Re: [PATCH 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

[Lijuan Gao]

在 12/12/2024 5:34 PM, Dmitry Baryshkov 写道:
> On Thu, Dec 12, 2024 at 05:23:59PM +0800, Lijuan Gao wrote:
>> The UFS_RESET pin is expected to be wired to the reset pin of the
>> primary UFS memory, it's a general purpose output pin. Reorder it and
>> expose it as a gpio, so that the UFS driver can toggle it.
> 
> I don't see pins being reordered. Please correct your commit messages.
> 
Understood,  I will update the commit message in next patch, thanks!
>>
>> The QCS615 TLMM pin controller has GPIOs 0-122, so correct the
>> gpio-rangs to 124.
>>
>> The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
>> gpio-rangs to 134.
>>
>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>> ---
>> Lijuan Gao (6):
>>        dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
>>        dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
>>        pinctrl: qcom: correct the number of ngpios for QCS615
>>        pinctrl: qcom: correct the number of ngpios for QCS8300
>>        arm64: dts: qcom: correct gpio-ranges for QCS615
>>        arm64: dts: qcom: correct gpio-ranges for QCS8300
>>
>>   Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml  | 2 +-
>>   Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 2 +-
>>   arch/arm64/boot/dts/qcom/qcs615.dtsi                             | 2 +-
>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi                            | 2 +-
>>   drivers/pinctrl/qcom/pinctrl-qcs615.c                            | 2 +-
>>   drivers/pinctrl/qcom/pinctrl-qcs8300.c                           | 2 +-
>>   6 files changed, 6 insertions(+), 6 deletions(-)
>> ---
>> base-commit: 91e71d606356e50f238d7a87aacdee4abc427f07
>> change-id: 20241211-correct_gpio_ranges-ed8a25ad22e7
>>
>> Best regards,
>> -- 
>> Lijuan Gao <quic_lijuang@quicinc.com>
>>
> 

-- 
Thx and BRs
Lijuan Gao

Re: [PATCH 1/6] dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615

[Rob Herring (Arm)]

On Thu, 12 Dec 2024 17:24:00 +0800, Lijuan Gao wrote:
> The QCS615 TLMM pin controller have the UFS_RESET pin, which is expected
> to be wired to the reset pin of the primary UFS memory. Include it in
> gpio-ranges so that the UFS driver can toggle it.
> 
> Fixes: 55c487ea6084 ("dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer")
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---
>  Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 2/6] dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300

[Rob Herring (Arm)]

On Thu, 12 Dec 2024 17:24:01 +0800, Lijuan Gao wrote:
> The QCS8300 TLMM pin controller have the UFS_RESET pin, which is expected
> to be wired to the reset pin of the primary UFS memory. Include it in
> gpio-ranges so that the UFS driver can toggle it.
> 
> Fixes: 5778535972e2 ("dt-bindings: pinctrl: describe qcs8300-tlmm")
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---
>  Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>