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Wed, 18 Dec 2024 01:08:42 -0800 (PST) Date: Wed, 18 Dec 2024 14:38:34 +0530 From: Manivannan Sadhasivam To: Christian Bruel Cc: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, p.zabel@pengutronix.de, cassel@kernel.org, quic_schintav@quicinc.com, fabrice.gasnier@foss.st.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 4/5] PCI: stm32: Add PCIe endpoint support for STM32MP25 Message-ID: <20241218090834.bz5htywl3sjbzq6w@thinkpad> References: <20241126155119.1574564-1-christian.bruel@foss.st.com> <20241126155119.1574564-5-christian.bruel@foss.st.com> <20241203152230.5mdrt27u5u5ecwcz@thinkpad> <4e257489-4d90-4e47-a4d9-a2444627c356@foss.st.com> <20241216161700.dtldi7fari6kafrr@thinkpad> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Tue, Dec 17, 2024 at 10:48:43AM +0100, Christian Bruel wrote: > > > On 12/16/24 17:17, Manivannan Sadhasivam wrote: > > On Mon, Dec 16, 2024 at 11:02:07AM +0100, Christian Bruel wrote: > > > Hi Manivanna, > > > > > > On 12/3/24 16:22, Manivannan Sadhasivam wrote: > > > > On Tue, Nov 26, 2024 at 04:51:18PM +0100, Christian Bruel wrote: > > > > > > > > [...] > > > > > > > > > +static int stm32_pcie_start_link(struct dw_pcie *pci) > > > > > +{ > > > > > + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); > > > > > + int ret; > > > > > + > > > > > + if (stm32_pcie->link_status == STM32_PCIE_EP_LINK_ENABLED) { > > > > > + dev_dbg(pci->dev, "Link is already enabled\n"); > > > > > + return 0; > > > > > + } > > > > > + > > > > > + ret = stm32_pcie_enable_link(pci); > > > > > + if (ret) { > > > > > + dev_err(pci->dev, "PCIe cannot establish link: %d\n", ret); > > > > > + return ret; > > > > > + } > > > > > > > > How the REFCLK is supplied to the endpoint? From host or generated locally? > > > > > > From Host only, we don't support the separated clock model. > > > > > > > OK. So even without refclk you are still able to access the controller > > registers? So the controller CSRs should be accessible by separate local clock I > > believe. > > > > Anyhow, please add this limitation (refclk dependency from host) in commit > > message. > > > > [...] > > > > > > > + ret = phy_set_mode(stm32_pcie->phy, PHY_MODE_PCIE); > > > > > > > > Hmm, so PHY mode is common for both endpoint and host? > > > > > > Yes it is. We need to init the phy here because it is a clock source for the > > > PCIe core clk > > > > > > > Clock source? Is it coming directly to PCIe or through RCC? There is no direct > > clock representation from PHY to PCIe in DT binding. > > The core_clk is generated directly by the PLL in the COMBOPHY, gated by the > RCC > In that case, phy should be the clock provider to RCC and PCIe should get the gated clock it. - Mani -- மணிவண்ணன் சதாசிவம்