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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad8fbac8sm45302b3a.159.2024.12.18.16.04.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 16:04:02 -0800 (PST) Date: Thu, 19 Dec 2024 09:04:00 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Thippeswamy Havalige Cc: manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, devicetree@vger.kernel.org, conor+dt@kernel.org, krzk+dt@kernel.org, bharat.kumar.gogada@amd.com, michal.simek@amd.com, lpieralisi@kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 0/2] Add support for CPM5 controller 1 Message-ID: <20241219000400.GF1444967@rocinante> References: <20240922061318.2653503-1-thippesw@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240922061318.2653503-1-thippesw@amd.com> Hello, > This patch series introduces support for the second Root Port controller in > the Xilinx Versal Premium CPM5 block. The Versal Premium platform features > two Type-A Root Port controllers operating at Gen5 speed. However, the > error interrupt registers and their corresponding bits are located at > different offsets for Controller 0 and Controller 1. > > To handle these differences, the series includes: > > A new compatible string for the second Root Port controller in the device > tree bindings. > > Driver updates to manage platform-specific interrupt registers and offsets > for both controllers using the new compatible string. Applied to controller/xilinx-cpm, thank you! [01/02] dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5 host1 https://git.kernel.org/pci/pci/c/5c911b4659d5 [02/02] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port Controller 1 https://git.kernel.org/pci/pci/c/ Krzysztof