[PATCH v3 0/3] ADF4371 refin mode and doubler support

[PATCH v3 0/3] ADF4371 refin mode and doubler support

[Antoniu Miclaus]

Add support for selecting between single-ended and differential
reference input. By default the single-ended input is enabled.

Input frequency boundaries are change based on the mode selected
(single-ended/differential).

Add support for the reference doubler. This feature is enabled
automatically to improve noise performance if the input frequency
is within the accepted range.

Antoniu Miclaus (3):
  dt-bindings: iio: adf4371: add refin mode
  iio: frequency: adf4371: add refin mode
  iio: frequency: adf4371: add ref doubler

 .../bindings/iio/frequency/adf4371.yaml       |  7 ++++
 drivers/iio/frequency/adf4371.c               | 38 ++++++++++++++++++-
 2 files changed, 43 insertions(+), 2 deletions(-)

-- 
2.47.1

[PATCH v3 1/3] dt-bindings: iio: adf4371: add refin mode

[Antoniu Miclaus]

Add support for selecting between single-ended and differential
reference input.

By default the single-ended input is enabled.

Input frequency boundaries are change based on the mode selected
(single-ended/differential).

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
changes in v3:
 - add option to select between refin-se and refin-diff
 .../devicetree/bindings/iio/frequency/adf4371.yaml         | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml
index 1cb2adaf66f9..f927d3af9f43 100644
--- a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml
+++ b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml
@@ -40,6 +40,13 @@ properties:
       output stage will shut down until the ADF4371/ADF4372 achieves lock as
       measured by the digital lock detect circuitry.
 
+  adi,refin-mode:
+    description:
+      Choose between single-ended or differential reference input.
+      refin-se - Single-Ended Reference Input
+      refin-diff - Differential Reference Input
+    enum: [refin-se, refin-diff]
+
 required:
   - compatible
   - reg
-- 
2.47.1

[PATCH v3 2/3] iio: frequency: adf4371: add refin mode

[Antoniu Miclaus]

Add support for single-ended/differential reference input mode.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
changes in v3:
 - parse refin-mode options.
 drivers/iio/frequency/adf4371.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/iio/frequency/adf4371.c b/drivers/iio/frequency/adf4371.c
index b27088464826..34fb75c379b0 100644
--- a/drivers/iio/frequency/adf4371.c
+++ b/drivers/iio/frequency/adf4371.c
@@ -41,6 +41,10 @@
 #define ADF4371_MOD2WORD_MSK		GENMASK(5, 0)
 #define ADF4371_MOD2WORD(x)		FIELD_PREP(ADF4371_MOD2WORD_MSK, x)
 
+/* ADF4371_REG22 */
+#define ADF4371_REFIN_MODE_MASK		BIT(6)
+#define ADF4371_REFIN_MODE(x)		FIELD_PREP(ADF4371_REFIN_MODE_MASK, x)
+
 /* ADF4371_REG24 */
 #define ADF4371_RF_DIV_SEL_MSK		GENMASK(6, 4)
 #define ADF4371_RF_DIV_SEL(x)		FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x)
@@ -69,6 +73,7 @@
 
 #define ADF4371_MAX_FREQ_PFD		250000000UL /* Hz */
 #define ADF4371_MAX_FREQ_REFIN		600000000UL /* Hz */
+#define ADF4371_MAX_FREQ_REFIN_SE	500000000UL /* Hz */
 
 /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
 #define ADF4371_MODULUS1		33554432ULL
@@ -476,6 +481,7 @@ static int adf4371_setup(struct adf4371_state *st)
 {
 	unsigned int synth_timeout = 2, timeout = 1, vco_alc_timeout = 1;
 	unsigned int vco_band_div, tmp;
+	bool ref_diff_en = false;
 	int ret;
 
 	/* Perform a software reset */
@@ -497,12 +503,30 @@ static int adf4371_setup(struct adf4371_state *st)
 			return ret;
 	}
 
+	if (!device_property_match_string(&st->spi->dev, "adi,refin-mode",
+					  "refin-diff"))
+		ref_diff_en = true;
+	else if (!device_property_match_string(&st->spi->dev, "adi,refin-mode",
+					       "refin-se"))
+		ref_diff_en = false;
+
 	/* Set address in ascending order, so the bulk_write() will work */
 	ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0),
 				 ADF4371_ADDR_ASC_MSK | ADF4371_ADDR_ASC_R_MSK,
 				 ADF4371_ADDR_ASC(1) | ADF4371_ADDR_ASC_R(1));
 	if (ret < 0)
 		return ret;
+
+	if ((ref_diff_en && st->clkin_freq > ADF4371_MAX_FREQ_REFIN) ||
+	    (!ref_diff_en && st->clkin_freq > ADF4371_MAX_FREQ_REFIN_SE))
+		return -EINVAL;
+
+	ret = regmap_update_bits(st->regmap,  ADF4371_REG(0x22),
+				 ADF4371_REFIN_MODE_MASK,
+				 ADF4371_REFIN_MODE(ref_diff_en));
+	if (ret < 0)
+		return ret;
+
 	/*
 	 * Calculate and maximize PFD frequency
 	 * fPFD = REFIN × ((1 + D)/(R × (1 + T)))
-- 
2.47.1

[PATCH v3 3/3] iio: frequency: adf4371: add ref doubler

[Antoniu Miclaus]

Add support for the reference doubler.

Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
changes in v3:
 - fix uninitialized variable.
 drivers/iio/frequency/adf4371.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/frequency/adf4371.c b/drivers/iio/frequency/adf4371.c
index 34fb75c379b0..f889da110efa 100644
--- a/drivers/iio/frequency/adf4371.c
+++ b/drivers/iio/frequency/adf4371.c
@@ -44,6 +44,8 @@
 /* ADF4371_REG22 */
 #define ADF4371_REFIN_MODE_MASK		BIT(6)
 #define ADF4371_REFIN_MODE(x)		FIELD_PREP(ADF4371_REFIN_MODE_MASK, x)
+#define ADF4371_REF_DOUB_MASK		BIT(5)
+#define ADF4371_REF_DOUB(x)		FIELD_PREP(ADF4371_REF_DOUB_MASK, x)\
 
 /* ADF4371_REG24 */
 #define ADF4371_RF_DIV_SEL_MSK		GENMASK(6, 4)
@@ -75,6 +77,9 @@
 #define ADF4371_MAX_FREQ_REFIN		600000000UL /* Hz */
 #define ADF4371_MAX_FREQ_REFIN_SE	500000000UL /* Hz */
 
+#define ADF4371_MIN_CLKIN_DOUB_FREQ	10000000ULL /* Hz */
+#define ADF4371_MAX_CLKIN_DOUB_FREQ	125000000ULL /* Hz */
+
 /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
 #define ADF4371_MODULUS1		33554432ULL
 /* MOD2 is the programmable, 14-bit auxiliary fractional modulus */
@@ -480,7 +485,7 @@ static const struct iio_info adf4371_info = {
 static int adf4371_setup(struct adf4371_state *st)
 {
 	unsigned int synth_timeout = 2, timeout = 1, vco_alc_timeout = 1;
-	unsigned int vco_band_div, tmp;
+	unsigned int vco_band_div, tmp, ref_doubler_en = 0;
 	bool ref_diff_en = false;
 	int ret;
 
@@ -521,6 +526,10 @@ static int adf4371_setup(struct adf4371_state *st)
 	    (!ref_diff_en && st->clkin_freq > ADF4371_MAX_FREQ_REFIN_SE))
 		return -EINVAL;
 
+	if (st->clkin_freq < ADF4371_MAX_CLKIN_DOUB_FREQ &&
+	    st->clkin_freq > ADF4371_MIN_CLKIN_DOUB_FREQ)
+		ref_doubler_en = 1;
+
 	ret = regmap_update_bits(st->regmap,  ADF4371_REG(0x22),
 				 ADF4371_REFIN_MODE_MASK,
 				 ADF4371_REFIN_MODE(ref_diff_en));
@@ -536,7 +545,8 @@ static int adf4371_setup(struct adf4371_state *st)
 	 */
 	do {
 		st->ref_div_factor++;
-		st->fpfd = st->clkin_freq / st->ref_div_factor;
+		st->fpfd = st->clkin_freq * (1 + ref_doubler_en) /
+			   st->ref_div_factor;
 	} while (st->fpfd > ADF4371_MAX_FREQ_PFD);
 
 	/* Calculate Timeouts */
-- 
2.47.1

Re: [PATCH v3 1/3] dt-bindings: iio: adf4371: add refin mode

[Conor Dooley]

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On Fri, Dec 20, 2024 at 11:56:13AM +0200, Antoniu Miclaus wrote:
> Add support for selecting between single-ended and differential
> reference input.
> 
> By default the single-ended input is enabled.

You can, and should, add a default: to the property then. Nothing in the
binding says what teh default is at present.

> 
> Input frequency boundaries are change based on the mode selected
> (single-ended/differential).
> 
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---
> changes in v3:
>  - add option to select between refin-se and refin-diff
>  .../devicetree/bindings/iio/frequency/adf4371.yaml         | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml
> index 1cb2adaf66f9..f927d3af9f43 100644
> --- a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml
> +++ b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml
> @@ -40,6 +40,13 @@ properties:
>        output stage will shut down until the ADF4371/ADF4372 achieves lock as
>        measured by the digital lock detect circuitry.
>  
> +  adi,refin-mode:
> +    description:
> +      Choose between single-ended or differential reference input.
> +      refin-se - Single-Ended Reference Input
> +      refin-diff - Differential Reference Input
> +    enum: [refin-se, refin-diff]
> +
>  required:
>    - compatible
>    - reg
> -- 
> 2.47.1
> 

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Re: [PATCH v3 1/3] dt-bindings: iio: adf4371: add refin mode

[Jonathan Cameron]

On Fri, 20 Dec 2024 11:56:13 +0200
Antoniu Miclaus <antoniu.miclaus@analog.com> wrote:

> Add support for selecting between single-ended and differential
> reference input.
> 
> By default the single-ended input is enabled.
> 
> Input frequency boundaries are change based on the mode selected
> (single-ended/differential).
> 
> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
> ---
> changes in v3:
>  - add option to select between refin-se and refin-diff
>  .../devicetree/bindings/iio/frequency/adf4371.yaml         | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml
> index 1cb2adaf66f9..f927d3af9f43 100644
> --- a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml
> +++ b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml
> @@ -40,6 +40,13 @@ properties:
>        output stage will shut down until the ADF4371/ADF4372 achieves lock as
>        measured by the digital lock detect circuitry.
>  
> +  adi,refin-mode:
> +    description:
> +      Choose between single-ended or differential reference input.
> +      refin-se - Single-Ended Reference Input
> +      refin-diff - Differential Reference Input
> +    enum: [refin-se, refin-diff]

I think I've failed convey what I was suggesting in previous reviews.

Until now the binding has

  clocks:
    description:
      Definition of the external clock (see clock/clock-bindings.txt)
    maxItems: 1

  clock-names:
    description:
      Must be "clkin"
    maxItems: 1

Now you have a situation not dissimilar to what we do for clock where they may
be connected to either a clock source or a crystal.  There we provide
two clock names and depending on which one is set, configure the device
appropriately.

Here we have clkin. That will be whatever the default we have so far.
Now add a possible name of
clkin-se or clkin-diff depending on which one we are not considering the
default.  I think the default is single ended, so make our two possible clock
names

clkin and clkin-diff  with description explaining that clkin is a single ended
clocks signal.

Jonathan




> +
>  required:
>    - compatible
>    - reg