Re: [PATCH v2 1/6] dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG block

[Rob Herring <robh@kernel.org>]

On Fri, Dec 27, 2024 at 07:02:05PM +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset
> Registers (CPG_ERROR_RSTm). A system reset is triggered in response to
> error interrupt factors, and the corresponding bit is set in the
> CPG_ERROR_RSTm register. These registers can be utilized by various IP
> blocks as needed.
> 
> For example, specific bits in these registers indicate resets caused by
> events such as underflow or overflow of the watchdog timer. This
> functionality allows the watchdog driver to determine whether the current
> boot resulted from a `Power-on Reset` or a `Watchdog Reset`.
> 
> Add the syscon-compatible property to the RZ/V2H(P) and RZ/G3E CPG block,
> allowing drivers to interact with the CPG_ERROR_RSTm registers as required.

This is an ABI change. That's okay because...?

> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> - No change
> ---
>  .../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml   | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> index c3fe76abd549..f42d79e73e70 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> @@ -17,9 +17,11 @@ description:
>  
>  properties:
>    compatible:
> -    enum:
> -      - renesas,r9a09g047-cpg # RZ/G3E
> -      - renesas,r9a09g057-cpg # RZ/V2H
> +    items:
> +      - enum:
> +          - renesas,r9a09g047-cpg # RZ/G3E
> +          - renesas,r9a09g057-cpg # RZ/V2H
> +      - const: syscon
>  
>    reg:
>      maxItems: 1
> @@ -73,7 +75,7 @@ additionalProperties: false
>  examples:
>    - |
>      clock-controller@10420000 {
> -        compatible = "renesas,r9a09g057-cpg";
> +        compatible = "renesas,r9a09g057-cpg", "syscon";
>          reg = <0x10420000 0x10000>;
>          clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
>          clock-names = "audio_extal", "rtxin", "qextal";
> -- 
> 2.43.0
>