From: Devang Tailor <dev.tailor@samsung.com>
To: alim.akhtar@samsung.com, dev.tailor@samsung.com, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
faraz.ata@samsung.com
Subject: [PATCH v2] arm64: dts: add cpu cache information to ExynosAuto-v920
Date: Wed, 8 Jan 2025 11:20:12 +0530 [thread overview]
Message-ID: <20250108055012.1938530-1-dev.tailor@samsung.com> (raw)
In-Reply-To: CGME20250108054224epcas5p399f3d734f8d9f82e5ae75d183d1a5344@epcas5p3.samsung.com
Add CPU caches information to its dt nodes so that the same is
available to userspace via sysfs. This SoC has 64/64 KB I/D cache and
256KB of L2 cache for each core, 2 MB of shared L3 cache for each quad
cpu cluster and 1 MB of shared L3 cache for the dual cpu cluster.
Signed-off-by: Devang Tailor <dev.tailor@samsung.com>
---
Changes in v2:
- Added L3 cache for all the three cpu clusters
- Corrected L2 cache numbering as a part of review comments from Krzysztof
and updated as per cpus clusters.
- Link to v1: https://patchwork.kernel.org/project/linux-arm-kernel/patch/20241231064350.523713-1-dev.tailor@samsung.com/
---
.../arm64/boot/dts/exynos/exynosautov920.dtsi | 127 ++++++++++++++++++
1 file changed, 127 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index eb446cdc4ab6..a3fd503c1b21 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -89,6 +89,13 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x0>;
enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_cl0>;
};
cpu1: cpu@100 {
@@ -96,6 +103,13 @@ cpu1: cpu@100 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x100>;
enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_cl0>;
};
cpu2: cpu@200 {
@@ -103,6 +117,13 @@ cpu2: cpu@200 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x200>;
enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_cl0>;
};
cpu3: cpu@300 {
@@ -110,6 +131,13 @@ cpu3: cpu@300 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x300>;
enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_cl0>;
};
cpu4: cpu@10000 {
@@ -117,6 +145,13 @@ cpu4: cpu@10000 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x10000>;
enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_cl1>;
};
cpu5: cpu@10100 {
@@ -124,6 +159,13 @@ cpu5: cpu@10100 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x10100>;
enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_cl1>;
};
cpu6: cpu@10200 {
@@ -131,6 +173,13 @@ cpu6: cpu@10200 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x10200>;
enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_cl1>;
};
cpu7: cpu@10300 {
@@ -138,6 +187,13 @@ cpu7: cpu@10300 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x10300>;
enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_cl1>;
};
cpu8: cpu@20000 {
@@ -145,6 +201,13 @@ cpu8: cpu@20000 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x20000>;
enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_cl2>;
};
cpu9: cpu@20100 {
@@ -152,6 +215,70 @@ cpu9: cpu@20100 {
compatible = "arm,cortex-a78ae";
reg = <0x0 0x20100>;
enable-method = "psci";
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache_cl2>;
+ };
+
+ l2_cache_cl0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_cache_cl0>;
+ };
+
+ l2_cache_cl1: l2-cache1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_cache_cl1>;
+ };
+
+ l2_cache_cl2: l2-cache2 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_cache_cl2>;
+ };
+
+ l3_cache_cl0: l3-cache0 {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
+ cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ };
+
+ l3_cache_cl1: l3-cache1 {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
+ cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ };
+
+ l3_cache_cl2: l3-cache2 {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
+ cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */
+ cache-line-size = <64>;
+ cache-sets = <1365>;
};
};
--
2.34.1
next parent reply other threads:[~2025-01-08 6:08 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20250108054224epcas5p399f3d734f8d9f82e5ae75d183d1a5344@epcas5p3.samsung.com>
2025-01-08 5:50 ` Devang Tailor [this message]
2025-01-31 11:49 ` [PATCH v2] arm64: dts: add cpu cache information to ExynosAuto-v920 Alim Akhtar
2025-01-31 13:27 ` Sudeep Holla
2025-02-05 15:52 ` Krzysztof Kozlowski
2025-02-05 16:10 ` Alim Akhtar
2025-02-17 8:45 ` Devang Tailor
2025-02-05 16:07 ` Alim Akhtar
2025-02-17 10:36 ` Krzysztof Kozlowski
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