[PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC

[PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series adds SYSCON support to retrieve boot status information
for RZ/V2H(P) SoC.
Summary of Changes,

    Clock:
        Add syscon compatible support to the CPG block in bindings and
        device trees.

    Watchdog:
        Document the renesas,r9a09g057-syscon-wdt-errorrst property.
        Update the watchdog driver to fetch and report boot status via
        Error Reset Registers (CPG_ERROR_RSTm).

    Device Tree:
        Add the syscon property to CPG and WDT nodes in R9A09G057 and
        R9A09G047 SoC DTSI.

These changes enable the watchdog driver to identify boot sources like
Power-on Reset and Watchdog Reset, improving system diagnostics.

v2->v3
- Updated comment section to mentione there arent any ABI breakages with
  this patch series.

Cheers,
Prabhakar

Lad Prabhakar (6):
  dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG block
  arm64: dts: renesas: r9a09g047: Add `syscon` compatible for CPG node
  arm64: dts: renesas: r9a09g057: Add `syscon` compatible for CPG node
  dt-bindings: watchdog: renesas: Document
    `renesas,syscon-cpg-error-rst` property
  watchdog: rzv2h_wdt: Add support to retrieve the bootstatus
    information
  arm64: dts: renesas: r9a09g057: Add `renesas,syscon-cpg-error-rst`
    property to WDT node

 .../bindings/clock/renesas,rzv2h-cpg.yaml     | 10 +++---
 .../bindings/watchdog/renesas,wdt.yaml        | 17 +++++++++
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  2 +-
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |  6 +++-
 drivers/watchdog/rzv2h_wdt.c                  | 35 +++++++++++++++++++
 5 files changed, 64 insertions(+), 6 deletions(-)

-- 
2.43.0

[PATCH v3 1/6] dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG block

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset
Registers (CPG_ERROR_RSTm). A system reset is triggered in response to
error interrupt factors, and the corresponding bit is set in the
CPG_ERROR_RSTm register. These registers can be utilized by various IP
blocks as needed.

For example, specific bits in these registers indicate resets caused by
events such as underflow or overflow of the watchdog timer. This
functionality allows the watchdog driver to determine whether the current
boot resulted from a `Power-on Reset` or a `Watchdog Reset`.

Add the syscon-compatible property to the RZ/V2H(P) and RZ/G3E CPG block,
allowing drivers to interact with the CPG_ERROR_RSTm registers as required.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Note, there is no ABI breakage as, this series adds the first `syscon`
user and also note the driver doesnt fail if the `syscon` property isnt
present in the cpg node to handle backward compatibility.
---
v2->v3
- No change

v1->v2
- No change
---
 .../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml   | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
index c3fe76abd549..f42d79e73e70 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
@@ -17,9 +17,11 @@ description:
 
 properties:
   compatible:
-    enum:
-      - renesas,r9a09g047-cpg # RZ/G3E
-      - renesas,r9a09g057-cpg # RZ/V2H
+    items:
+      - enum:
+          - renesas,r9a09g047-cpg # RZ/G3E
+          - renesas,r9a09g057-cpg # RZ/V2H
+      - const: syscon
 
   reg:
     maxItems: 1
@@ -73,7 +75,7 @@ additionalProperties: false
 examples:
   - |
     clock-controller@10420000 {
-        compatible = "renesas,r9a09g057-cpg";
+        compatible = "renesas,r9a09g057-cpg", "syscon";
         reg = <0x10420000 0x10000>;
         clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
         clock-names = "audio_extal", "rtxin", "qextal";
-- 
2.43.0

[PATCH v3 2/6] arm64: dts: renesas: r9a09g047: Add `syscon` compatible for CPG node

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add `syscon` compatible for CPG node to allow the IP blocks to interact
with the CPG registers as needed.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3
- No change

v1->v2
- No change
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 200e9ea89193..57fbe92e794e 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -145,7 +145,7 @@ pinctrl: pinctrl@10410000 {
 		};
 
 		cpg: clock-controller@10420000 {
-			compatible = "renesas,r9a09g047-cpg";
+			compatible = "renesas,r9a09g047-cpg", "syscon";
 			reg = <0 0x10420000 0 0x10000>;
 			clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
 			clock-names = "audio_extal", "rtxin", "qextal";
-- 
2.43.0

[PATCH v3 3/6] arm64: dts: renesas: r9a09g057: Add `syscon` compatible for CPG node

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add `syscon` compatible for CPG node to allow the IP blocks to interact
with the CPG registers as needed.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3
- No change

v1->v2
- No change
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 3938b9740959..e7428b80bda2 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -243,7 +243,7 @@ pinctrl: pinctrl@10410000 {
 		};
 
 		cpg: clock-controller@10420000 {
-			compatible = "renesas,r9a09g057-cpg";
+			compatible = "renesas,r9a09g057-cpg", "syscon";
 			reg = <0 0x10420000 0 0x10000>;
 			clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
 			clock-names = "audio_extal", "rtxin", "qextal";
-- 
2.43.0

[PATCH v3 4/6] dt-bindings: watchdog: renesas: Document `renesas,syscon-cpg-error-rst` property

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The RZ/V2H(P) CPG block includes Error Reset Registers (CPG_ERROR_RSTm).
A system reset is triggered in response to error interrupt factors, and
the corresponding bit is set in the CPG_ERROR_RSTm register. These
registers can be utilized by various IP blocks as needed.

In the event of a watchdog overflow or underflow, a system reset is issued,
and the CPG_ERROR_RST2[0/1/2/3] bits are set depending on the watchdog in
use: CM33 = 0, CA55 = 1, CR8_0 = 2, CR8_1 = 3. For the watchdog driver to
determine and report the current boot status, it needs to read the
CPG_ERROR_RST2[0/1/2/3]bits and provide this information to the user upon
request.

To facilitate this operation, add `renesas,syscon-cpg-error-rst`
property to the WDT node, which maps to the `syscon` CPG node, enabling
retrieval of the necessary information.

Additionally, the property is marked as required for the RZ/V2H(P) SoC to
ensure future compatibility (e.g., where the same IP block is present on
the RZ/G3E SoC) and explicitly disallowed for other SoCs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Note, this change doesnt break any ABI, as the subsequent driver patch handles
the case elegantly if the `syscon` node is missing to handle backward compatibility.

v2->v3
- No change

v1->v2
- Renamed `renesas,r9a09g057-syscon-wdt-errorrst` to `renesas,syscon-cpg-error-rst`
- Updated commit message
---
 .../bindings/watchdog/renesas,wdt.yaml          | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
index 29ada89fdcdc..ca62ae8b1b0c 100644
--- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
@@ -112,6 +112,19 @@ properties:
 
   timeout-sec: true
 
+  renesas,syscon-cpg-error-rst:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description:
+      The first cell is a phandle to the SYSCON entry required to obtain
+      the current boot status. The second cell specifies the CPG_ERROR_RSTm
+      register offset within the SYSCON, and the third cell indicates the
+      bit within the CPG_ERROR_RSTm register.
+    items:
+      - items:
+          - description: Phandle to the CPG node
+          - description: The CPG_ERROR_RSTm register offset
+          - description: The bit within CPG_ERROR_RSTm register of interest
+
 required:
   - compatible
   - reg
@@ -182,7 +195,11 @@ allOf:
       properties:
         interrupts: false
         interrupt-names: false
+      required:
+        - renesas,syscon-cpg-error-rst
     else:
+      properties:
+        renesas,syscon-cpg-error-rst: false
       required:
         - interrupts
 
-- 
2.43.0

[PATCH v3 5/6] watchdog: rzv2h_wdt: Add support to retrieve the bootstatus information

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

On the RZ/V2H(P) SoC we can determine if the current boot is due to
`Power-on-Reset` or due to the `Watchdog`. The information used to
determine this is present on the CPG block.

The CPG_ERROR_RSTm(m = 2 - 8) registers are set in response to an error
interrupt causing an reset. CPG_ERROR_RST2[ERROR_RST0/1/2] is set if there
was an underflow/overflow on WDT1 causing an error interrupt.

To fetch this information from CPG block `syscon` is used and bootstatus
field in the watchdog device is updated based on the
CPG_ERROR_RST2[ERROR_RST0/1/2] bit. Upon consumig
CPG_ERROR_RST2[ERROR_RST0/1/2] bit we clear it.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Note, this change doesnt break any ABI, if the `syscon` node is missing
the driver probe continues further to handle backward compatibility.

v2->v3
- No change

v1->v2
- Returned ret in error path instead of -EINVAL
- Dropped unnecessar regmap_read
---
 drivers/watchdog/rzv2h_wdt.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c
index 8defd0241213..ab7e35928190 100644
--- a/drivers/watchdog/rzv2h_wdt.c
+++ b/drivers/watchdog/rzv2h_wdt.c
@@ -4,14 +4,17 @@
  *
  * Copyright (C) 2024 Renesas Electronics Corporation.
  */
+#include <linux/bitfield.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/regmap.h>
 #include <linux/reset.h>
 #include <linux/units.h>
 #include <linux/watchdog.h>
@@ -40,6 +43,9 @@
 
 #define WDT_DEFAULT_TIMEOUT	60U
 
+#define CPG_ERROR_RST2(x)	BIT(x)
+#define CPG_ERROR_RST2_WEN(x)	BIT((x) + 16)
+
 static bool nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, bool, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
@@ -206,9 +212,37 @@ static const struct watchdog_ops rzv2h_wdt_ops = {
 static int rzv2h_wdt_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
 	struct rzv2h_wdt_priv *priv;
+	unsigned int bootstatus = 0;
+	struct regmap *syscon;
 	int ret;
 
+	/* Do not error out to maintain old DT compatibility */
+	syscon = syscon_regmap_lookup_by_phandle(np, "renesas,syscon-cpg-error-rst");
+	if (!IS_ERR(syscon)) {
+		struct of_phandle_args args;
+		u32 reg;
+
+		ret = of_parse_phandle_with_fixed_args(np, "renesas,syscon-cpg-error-rst",
+						       2, 0, &args);
+		if (ret)
+			return ret;
+
+		ret = regmap_read(syscon, args.args[0], &reg);
+		if (ret)
+			return ret;
+
+		if (reg & CPG_ERROR_RST2(args.args[1])) {
+			ret = regmap_write(syscon, args.args[0],
+					   CPG_ERROR_RST2(args.args[1]) |
+					   CPG_ERROR_RST2_WEN(args.args[1]));
+			if (ret)
+				return ret;
+		}
+		bootstatus = reg & CPG_ERROR_RST2(args.args[1]) ? WDIOF_CARDRESET : 0;
+	}
+
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
@@ -243,6 +277,7 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
 	priv->wdev.info = &rzv2h_wdt_ident;
 	priv->wdev.ops = &rzv2h_wdt_ops;
 	priv->wdev.parent = dev;
+	priv->wdev.bootstatus = bootstatus;
 	watchdog_set_drvdata(&priv->wdev, priv);
 	watchdog_set_nowayout(&priv->wdev, nowayout);
 	watchdog_stop_on_unregister(&priv->wdev);
-- 
2.43.0

[PATCH v3 6/6] arm64: dts: renesas: r9a09g057: Add `renesas,syscon-cpg-error-rst` property to WDT node

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add `renesas,syscon-cpg-error-rst` property to WDT node, to
determine whether the current boot resulted from a `Power-on Reset`
or a `Watchdog Reset`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3
- No change

v1->v2
- No change
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index e7428b80bda2..01b4b4184e5c 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -445,6 +445,7 @@ wdt0: watchdog@11c00400 {
 			clock-names = "pclk", "oscclk";
 			resets = <&cpg 0x75>;
 			power-domains = <&cpg>;
+			renesas,syscon-cpg-error-rst = <&cpg 0xb40 0>;
 			status = "disabled";
 		};
 
@@ -455,6 +456,7 @@ wdt1: watchdog@14400000 {
 			clock-names = "pclk", "oscclk";
 			resets = <&cpg 0x76>;
 			power-domains = <&cpg>;
+			renesas,syscon-cpg-error-rst = <&cpg 0xb40 1>;
 			status = "disabled";
 		};
 
@@ -465,6 +467,7 @@ wdt2: watchdog@13000000 {
 			clock-names = "pclk", "oscclk";
 			resets = <&cpg 0x77>;
 			power-domains = <&cpg>;
+			renesas,syscon-cpg-error-rst = <&cpg 0xb40 2>;
 			status = "disabled";
 		};
 
@@ -475,6 +478,7 @@ wdt3: watchdog@13000400 {
 			clock-names = "pclk", "oscclk";
 			resets = <&cpg 0x78>;
 			power-domains = <&cpg>;
+			renesas,syscon-cpg-error-rst = <&cpg 0xb40 3>;
 			status = "disabled";
 		};
 
-- 
2.43.0

RE: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC

[Biju Das]

Hi Prabhakar,

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 13 January 2025 11:24
> Subject: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Hi All,
> 
> This patch series adds SYSCON support to retrieve boot status information for RZ/V2H(P) SoC.
> Summary of Changes,
> 
>     Clock:
>         Add syscon compatible support to the CPG block in bindings and
>         device trees.
> 
>     Watchdog:
>         Document the renesas,r9a09g057-syscon-wdt-errorrst property.
>         Update the watchdog driver to fetch and report boot status via
>         Error Reset Registers (CPG_ERROR_RSTm).
> 
>     Device Tree:
>         Add the syscon property to CPG and WDT nodes in R9A09G057 and
>         R9A09G047 SoC DTSI.
> 
> These changes enable the watchdog driver to identify boot sources like Power-on Reset and Watchdog
> Reset, improving system diagnostics.

This means that, we should assume U-boot/bootloader should not clear the WDT reset status bit.

If they clear it, there should be a way to propagate it from u-boot/bootloader to linux,
otherwise, we get wrong bootstatus in linux.
But the clearing of watchdog status by one of the cases: 

1) u-boot identify the boot source and clear the status bit
2) u-boot identify the boot source and does not clear the status bit, but linux clear it.
3) u-boot does not touch WDT status bits, but linux clear it.

Cheers,
Biju

Re: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC

[Lad, Prabhakar]

Hi Biju,

On Mon, Jan 13, 2025 at 11:38 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: 13 January 2025 11:24
> > Subject: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Hi All,
> >
> > This patch series adds SYSCON support to retrieve boot status information for RZ/V2H(P) SoC.
> > Summary of Changes,
> >
> >     Clock:
> >         Add syscon compatible support to the CPG block in bindings and
> >         device trees.
> >
> >     Watchdog:
> >         Document the renesas,r9a09g057-syscon-wdt-errorrst property.
> >         Update the watchdog driver to fetch and report boot status via
> >         Error Reset Registers (CPG_ERROR_RSTm).
> >
> >     Device Tree:
> >         Add the syscon property to CPG and WDT nodes in R9A09G057 and
> >         R9A09G047 SoC DTSI.
> >
> > These changes enable the watchdog driver to identify boot sources like Power-on Reset and Watchdog
> > Reset, improving system diagnostics.
>
> This means that, we should assume U-boot/bootloader should not clear the WDT reset status bit.
>
> If they clear it, there should be a way to propagate it from u-boot/bootloader to linux,
> otherwise, we get wrong bootstatus in linux.
> But the clearing of watchdog status by one of the cases:
>
> 1) u-boot identify the boot source and clear the status bit
>
I agree, if the tf-a/u-boot clears the register, the bootstatus
reported by Linux will be in-correct.

Alternative solution, would be:

Let the TF-A create WDT nodes for us and add a property
`renesas,r9a09g057-wdt-bootstatus` and propagate the WDT nodes to
Linux.

renesas,r9a09g057-wdt-bootstatus = <0/1>;

0 -> Power on reset
1 -> WDT reset

Geert/Rob/Krzysztof - Is the proposed approach acceptable or is there
any alternative where this can be avoided.

Cheers,
Prabhakar

Re: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC

[Rob Herring (Arm)]

On Mon, 13 Jan 2025 11:23:43 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Hi All,
> 
> This patch series adds SYSCON support to retrieve boot status information
> for RZ/V2H(P) SoC.
> Summary of Changes,
> 
>     Clock:
>         Add syscon compatible support to the CPG block in bindings and
>         device trees.
> 
>     Watchdog:
>         Document the renesas,r9a09g057-syscon-wdt-errorrst property.
>         Update the watchdog driver to fetch and report boot status via
>         Error Reset Registers (CPG_ERROR_RSTm).
> 
>     Device Tree:
>         Add the syscon property to CPG and WDT nodes in R9A09G057 and
>         R9A09G047 SoC DTSI.
> 
> These changes enable the watchdog driver to identify boot sources like
> Power-on Reset and Watchdog Reset, improving system diagnostics.
> 
> v2->v3
> - Updated comment section to mentione there arent any ABI breakages with
>   this patch series.
> 
> Cheers,
> Prabhakar
> 
> Lad Prabhakar (6):
>   dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG block
>   arm64: dts: renesas: r9a09g047: Add `syscon` compatible for CPG node
>   arm64: dts: renesas: r9a09g057: Add `syscon` compatible for CPG node
>   dt-bindings: watchdog: renesas: Document
>     `renesas,syscon-cpg-error-rst` property
>   watchdog: rzv2h_wdt: Add support to retrieve the bootstatus
>     information
>   arm64: dts: renesas: r9a09g057: Add `renesas,syscon-cpg-error-rst`
>     property to WDT node
> 
>  .../bindings/clock/renesas,rzv2h-cpg.yaml     | 10 +++---
>  .../bindings/watchdog/renesas,wdt.yaml        | 17 +++++++++
>  arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  2 +-
>  arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |  6 +++-
>  drivers/watchdog/rzv2h_wdt.c                  | 35 +++++++++++++++++++
>  5 files changed, 64 insertions(+), 6 deletions(-)
> 
> --
> 2.43.0
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/renesas/' for 20250113112349.801875-1-prabhakar.mahadev-lad.rj@bp.renesas.com:

arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb: /soc/spi@10060000/flash@0: failed to match any schema with compatible: ['micron,mt25qu512a', 'jedec,spi-nor']

Re: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC

[Guenter Roeck]

On 1/13/25 04:40, Lad, Prabhakar wrote:
> Hi Biju,
> 
> On Mon, Jan 13, 2025 at 11:38 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>>
>> Hi Prabhakar,
>>
>>> -----Original Message-----
>>> From: Prabhakar <prabhakar.csengg@gmail.com>
>>> Sent: 13 January 2025 11:24
>>> Subject: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC
>>>
>>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>
>>> Hi All,
>>>
>>> This patch series adds SYSCON support to retrieve boot status information for RZ/V2H(P) SoC.
>>> Summary of Changes,
>>>
>>>      Clock:
>>>          Add syscon compatible support to the CPG block in bindings and
>>>          device trees.
>>>
>>>      Watchdog:
>>>          Document the renesas,r9a09g057-syscon-wdt-errorrst property.
>>>          Update the watchdog driver to fetch and report boot status via
>>>          Error Reset Registers (CPG_ERROR_RSTm).
>>>
>>>      Device Tree:
>>>          Add the syscon property to CPG and WDT nodes in R9A09G057 and
>>>          R9A09G047 SoC DTSI.
>>>
>>> These changes enable the watchdog driver to identify boot sources like Power-on Reset and Watchdog
>>> Reset, improving system diagnostics.
>>
>> This means that, we should assume U-boot/bootloader should not clear the WDT reset status bit.
>>
>> If they clear it, there should be a way to propagate it from u-boot/bootloader to linux,
>> otherwise, we get wrong bootstatus in linux.
>> But the clearing of watchdog status by one of the cases:
>>
>> 1) u-boot identify the boot source and clear the status bit
>>
> I agree, if the tf-a/u-boot clears the register, the bootstatus
> reported by Linux will be in-correct.
> 

I would rephrase that: Today, the boot status is _always_ incorrect if a reboot
was triggered by a watchdog reset. After this patch, it will be correct unless
the boot loader resets the status bit.

> Alternative solution, would be:
> 
> Let the TF-A create WDT nodes for us and add a property
> `renesas,r9a09g057-wdt-bootstatus` and propagate the WDT nodes to
> Linux.
> 
> renesas,r9a09g057-wdt-bootstatus = <0/1>;
> 

That would require both a property change as well as a change in the bootloader.
I suspect it would also be inappropriate as standard property and would have
to be passed as 'chosen' property (if that is even permitted) or as command line
argument.

Either case, if the boot loader has to be changed anyway, why not just tell it
to leave the boot status alone ?

Guenter

Re: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC

[Lad, Prabhakar]

Hi Guenter,

On Mon, Jan 13, 2025 at 4:08 PM Guenter Roeck <linux@roeck-us.net> wrote:
>
> On 1/13/25 04:40, Lad, Prabhakar wrote:
> > Hi Biju,
> >
> > On Mon, Jan 13, 2025 at 11:38 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >>
> >> Hi Prabhakar,
> >>
> >>> -----Original Message-----
> >>> From: Prabhakar <prabhakar.csengg@gmail.com>
> >>> Sent: 13 January 2025 11:24
> >>> Subject: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC
> >>>
> >>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>>
> >>> Hi All,
> >>>
> >>> This patch series adds SYSCON support to retrieve boot status information for RZ/V2H(P) SoC.
> >>> Summary of Changes,
> >>>
> >>>      Clock:
> >>>          Add syscon compatible support to the CPG block in bindings and
> >>>          device trees.
> >>>
> >>>      Watchdog:
> >>>          Document the renesas,r9a09g057-syscon-wdt-errorrst property.
> >>>          Update the watchdog driver to fetch and report boot status via
> >>>          Error Reset Registers (CPG_ERROR_RSTm).
> >>>
> >>>      Device Tree:
> >>>          Add the syscon property to CPG and WDT nodes in R9A09G057 and
> >>>          R9A09G047 SoC DTSI.
> >>>
> >>> These changes enable the watchdog driver to identify boot sources like Power-on Reset and Watchdog
> >>> Reset, improving system diagnostics.
> >>
> >> This means that, we should assume U-boot/bootloader should not clear the WDT reset status bit.
> >>
> >> If they clear it, there should be a way to propagate it from u-boot/bootloader to linux,
> >> otherwise, we get wrong bootstatus in linux.
> >> But the clearing of watchdog status by one of the cases:
> >>
> >> 1) u-boot identify the boot source and clear the status bit
> >>
> > I agree, if the tf-a/u-boot clears the register, the bootstatus
> > reported by Linux will be in-correct.
> >
>
> I would rephrase that: Today, the boot status is _always_ incorrect if a reboot
> was triggered by a watchdog reset. After this patch, it will be correct unless
> the boot loader resets the status bit.
>
Agreed.

> > Alternative solution, would be:
> >
> > Let the TF-A create WDT nodes for us and add a property
> > `renesas,r9a09g057-wdt-bootstatus` and propagate the WDT nodes to
> > Linux.
> >
> > renesas,r9a09g057-wdt-bootstatus = <0/1>;
> >
>
> That would require both a property change as well as a change in the bootloader.
> I suspect it would also be inappropriate as standard property and would have
> to be passed as 'chosen' property (if that is even permitted) or as command line
> argument.
>
> Either case, if the boot loader has to be changed anyway, why not just tell it
> to leave the boot status alone ?
>
It can be done, I think Biju is concerned about the user clearing it,
maybe using the `mw` command or the Linux CPG driver clearing it
during the probe.

Cheers,
Prabhakar

RE: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC

[Biju Das]

Hi Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 13 January 2025 16:29
> Subject: Re: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC
> 
> Hi Guenter,
> 
> On Mon, Jan 13, 2025 at 4:0 PM Guenter Roeck <linux@roeck-us.net> wrote:
> >
> > On 1/13/25 04:40, Lad, Prabhakar wrote:
> > > Hi Biju,
> > >
> > > On Mon, Jan 13, 2025 at 11:38 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > >>
> > >> Hi Prabhakar,
> > >>
> > >>> -----Original Message-----
> > >>> From: Prabhakar <prabhakar.csengg@gmail.com>
> > >>> Sent: 13 January 2025 11:24
> > >>> Subject: [PATCH v3 0/6] Add support to retrieve the bootstatus
> > >>> from watchdog for RZ/V2H(P) SoC
> > >>>
> > >>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >>>
> > >>> Hi All,
> > >>>
> > >>> This patch series adds SYSCON support to retrieve boot status information for RZ/V2H(P) SoC.
> > >>> Summary of Changes,
> > >>>
> > >>>      Clock:
> > >>>          Add syscon compatible support to the CPG block in bindings and
> > >>>          device trees.
> > >>>
> > >>>      Watchdog:
> > >>>          Document the renesas,r9a09g057-syscon-wdt-errorrst property.
> > >>>          Update the watchdog driver to fetch and report boot status via
> > >>>          Error Reset Registers (CPG_ERROR_RSTm).
> > >>>
> > >>>      Device Tree:
> > >>>          Add the syscon property to CPG and WDT nodes in R9A09G057 and
> > >>>          R9A09G047 SoC DTSI.
> > >>>
> > >>> These changes enable the watchdog driver to identify boot sources
> > >>> like Power-on Reset and Watchdog Reset, improving system diagnostics.
> > >>
> > >> This means that, we should assume U-boot/bootloader should not clear the WDT reset status bit.
> > >>
> > >> If they clear it, there should be a way to propagate it from
> > >> u-boot/bootloader to linux, otherwise, we get wrong bootstatus in linux.
> > >> But the clearing of watchdog status by one of the cases:
> > >>
> > >> 1) u-boot identify the boot source and clear the status bit
> > >>
> > > I agree, if the tf-a/u-boot clears the register, the bootstatus
> > > reported by Linux will be in-correct.
> > >
> >
> > I would rephrase that: Today, the boot status is _always_ incorrect if
> > a reboot was triggered by a watchdog reset. After this patch, it will
> > be correct unless the boot loader resets the status bit.
> >
> Agreed.
> 
> > > Alternative solution, would be:
> > >
> > > Let the TF-A create WDT nodes for us and add a property
> > > `renesas,r9a09g057-wdt-bootstatus` and propagate the WDT nodes to
> > > Linux.
> > >
> > > renesas,r9a09g057-wdt-bootstatus = <0/1>;
> > >
> >
> > That would require both a property change as well as a change in the bootloader.
> > I suspect it would also be inappropriate as standard property and
> > would have to be passed as 'chosen' property (if that is even
> > permitted) or as command line argument.
> >
> > Either case, if the boot loader has to be changed anyway, why not just
> > tell it to leave the boot status alone ?
> >
> It can be done, I think Biju is concerned about the user clearing it, maybe using the `mw` command or
> the Linux CPG driver clearing it during the probe.

If either TF-A or U-boot clears the status we have problem. We need to provide input to
stake holders of u-boot/tf-a to not to clear the wdt boot status, so that linux can report correct
status.

 Or 

They need to provide the boot status as command line args if u-boot/tf-a clears it.

Or

If there is command line arg, parse that and report as boot status, else
read from cpg and report it.

Cheers,
Biju

Re: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC

[Lad, Prabhakar]

Hi Biju,

On Mon, Jan 13, 2025 at 4:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > -----Original Message-----
> > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: 13 January 2025 16:29
> > Subject: Re: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC
> >
> > Hi Guenter,
> >
> > On Mon, Jan 13, 2025 at 4:0 PM Guenter Roeck <linux@roeck-us.net> wrote:
> > >
> > > On 1/13/25 04:40, Lad, Prabhakar wrote:
> > > > Hi Biju,
> > > >
> > > > On Mon, Jan 13, 2025 at 11:38 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > >>
> > > >> Hi Prabhakar,
> > > >>
> > > >>> -----Original Message-----
> > > >>> From: Prabhakar <prabhakar.csengg@gmail.com>
> > > >>> Sent: 13 January 2025 11:24
> > > >>> Subject: [PATCH v3 0/6] Add support to retrieve the bootstatus
> > > >>> from watchdog for RZ/V2H(P) SoC
> > > >>>
> > > >>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >>>
> > > >>> Hi All,
> > > >>>
> > > >>> This patch series adds SYSCON support to retrieve boot status information for RZ/V2H(P) SoC.
> > > >>> Summary of Changes,
> > > >>>
> > > >>>      Clock:
> > > >>>          Add syscon compatible support to the CPG block in bindings and
> > > >>>          device trees.
> > > >>>
> > > >>>      Watchdog:
> > > >>>          Document the renesas,r9a09g057-syscon-wdt-errorrst property.
> > > >>>          Update the watchdog driver to fetch and report boot status via
> > > >>>          Error Reset Registers (CPG_ERROR_RSTm).
> > > >>>
> > > >>>      Device Tree:
> > > >>>          Add the syscon property to CPG and WDT nodes in R9A09G057 and
> > > >>>          R9A09G047 SoC DTSI.
> > > >>>
> > > >>> These changes enable the watchdog driver to identify boot sources
> > > >>> like Power-on Reset and Watchdog Reset, improving system diagnostics.
> > > >>
> > > >> This means that, we should assume U-boot/bootloader should not clear the WDT reset status bit.
> > > >>
> > > >> If they clear it, there should be a way to propagate it from
> > > >> u-boot/bootloader to linux, otherwise, we get wrong bootstatus in linux.
> > > >> But the clearing of watchdog status by one of the cases:
> > > >>
> > > >> 1) u-boot identify the boot source and clear the status bit
> > > >>
> > > > I agree, if the tf-a/u-boot clears the register, the bootstatus
> > > > reported by Linux will be in-correct.
> > > >
> > >
> > > I would rephrase that: Today, the boot status is _always_ incorrect if
> > > a reboot was triggered by a watchdog reset. After this patch, it will
> > > be correct unless the boot loader resets the status bit.
> > >
> > Agreed.
> >
> > > > Alternative solution, would be:
> > > >
> > > > Let the TF-A create WDT nodes for us and add a property
> > > > `renesas,r9a09g057-wdt-bootstatus` and propagate the WDT nodes to
> > > > Linux.
> > > >
> > > > renesas,r9a09g057-wdt-bootstatus = <0/1>;
> > > >
> > >
> > > That would require both a property change as well as a change in the bootloader.
> > > I suspect it would also be inappropriate as standard property and
> > > would have to be passed as 'chosen' property (if that is even
> > > permitted) or as command line argument.
> > >
> > > Either case, if the boot loader has to be changed anyway, why not just
> > > tell it to leave the boot status alone ?
> > >
> > It can be done, I think Biju is concerned about the user clearing it, maybe using the `mw` command or
> > the Linux CPG driver clearing it during the probe.
>
> If either TF-A or U-boot clears the status we have problem. We need to provide input to
> stake holders of u-boot/tf-a to not to clear the wdt boot status, so that linux can report correct
> status.
>
I think this can be done, currently the TF-A nor u-boot clears the
status. Are you OK with this approach?

Cheers,
Prabhakar

RE: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC

[Biju Das]

HI Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 13 January 2025 17:00
> Subject: Re: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC
> 
> Hi Biju,
> 
> On Mon, Jan 13, 2025 at 4:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> > Hi Prabhakar,
> >
> > > -----Original Message-----
> > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: 13 January 2025 16:29
> > > Subject: Re: [PATCH v3 0/6] Add support to retrieve the bootstatus
> > > from watchdog for RZ/V2H(P) SoC
> > >
> > > Hi Guenter,
> > >
> > > On Mon, Jan 13, 2025 at 4:0 PM Guenter Roeck <linux@roeck-us.net> wrote:
> > > >
> > > > On 1/13/25 04:40, Lad, Prabhakar wrote:
> > > > > Hi Biju,
> > > > >
> > > > > On Mon, Jan 13, 2025 at 11:38 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > >>
> > > > >> Hi Prabhakar,
> > > > >>
> > > > >>> -----Original Message-----
> > > > >>> From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > >>> Sent: 13 January 2025 11:24
> > > > >>> Subject: [PATCH v3 0/6] Add support to retrieve the bootstatus
> > > > >>> from watchdog for RZ/V2H(P) SoC
> > > > >>>
> > > > >>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >>>
> > > > >>> Hi All,
> > > > >>>
> > > > >>> This patch series adds SYSCON support to retrieve boot status information for RZ/V2H(P) SoC.
> > > > >>> Summary of Changes,
> > > > >>>
> > > > >>>      Clock:
> > > > >>>          Add syscon compatible support to the CPG block in bindings and
> > > > >>>          device trees.
> > > > >>>
> > > > >>>      Watchdog:
> > > > >>>          Document the renesas,r9a09g057-syscon-wdt-errorrst property.
> > > > >>>          Update the watchdog driver to fetch and report boot status via
> > > > >>>          Error Reset Registers (CPG_ERROR_RSTm).
> > > > >>>
> > > > >>>      Device Tree:
> > > > >>>          Add the syscon property to CPG and WDT nodes in R9A09G057 and
> > > > >>>          R9A09G047 SoC DTSI.
> > > > >>>
> > > > >>> These changes enable the watchdog driver to identify boot
> > > > >>> sources like Power-on Reset and Watchdog Reset, improving system diagnostics.
> > > > >>
> > > > >> This means that, we should assume U-boot/bootloader should not clear the WDT reset status
> bit.
> > > > >>
> > > > >> If they clear it, there should be a way to propagate it from
> > > > >> u-boot/bootloader to linux, otherwise, we get wrong bootstatus in linux.
> > > > >> But the clearing of watchdog status by one of the cases:
> > > > >>
> > > > >> 1) u-boot identify the boot source and clear the status bit
> > > > >>
> > > > > I agree, if the tf-a/u-boot clears the register, the bootstatus
> > > > > reported by Linux will be in-correct.
> > > > >
> > > >
> > > > I would rephrase that: Today, the boot status is _always_
> > > > incorrect if a reboot was triggered by a watchdog reset. After
> > > > this patch, it will be correct unless the boot loader resets the status bit.
> > > >
> > > Agreed.
> > >
> > > > > Alternative solution, would be:
> > > > >
> > > > > Let the TF-A create WDT nodes for us and add a property
> > > > > `renesas,r9a09g057-wdt-bootstatus` and propagate the WDT nodes
> > > > > to Linux.
> > > > >
> > > > > renesas,r9a09g057-wdt-bootstatus = <0/1>;
> > > > >
> > > >
> > > > That would require both a property change as well as a change in the bootloader.
> > > > I suspect it would also be inappropriate as standard property and
> > > > would have to be passed as 'chosen' property (if that is even
> > > > permitted) or as command line argument.
> > > >
> > > > Either case, if the boot loader has to be changed anyway, why not
> > > > just tell it to leave the boot status alone ?
> > > >
> > > It can be done, I think Biju is concerned about the user clearing
> > > it, maybe using the `mw` command or the Linux CPG driver clearing it during the probe.
> >
> > If either TF-A or U-boot clears the status we have problem. We need to
> > provide input to stake holders of u-boot/tf-a to not to clear the wdt
> > boot status, so that linux can report correct status.
> >
> I think this can be done, currently the TF-A nor u-boot clears the status. Are you OK with this
> approach?

Yes. As it provides consistent wdt status in tf-a/u-boot/kernel.

Cheers,
Biju

RE: [PATCH v3 5/6] watchdog: rzv2h_wdt: Add support to retrieve the bootstatus information

[Biju Das]

Hi Prabhakar,

Thanks for the patch.

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 13 January 2025 11:24
> Subject: [PATCH v3 5/6] watchdog: rzv2h_wdt: Add support to retrieve the bootstatus information
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> On the RZ/V2H(P) SoC we can determine if the current boot is due to `Power-on-Reset` or due to the
> `Watchdog`. The information used to determine this is present on the CPG block.
> 
> The CPG_ERROR_RSTm(m = 2 - 8) registers are set in response to an error interrupt causing an reset.
> CPG_ERROR_RST2[ERROR_RST0/1/2] is set if there was an underflow/overflow on WDT1 causing an error
> interrupt.
> 
> To fetch this information from CPG block `syscon` is used and bootstatus field in the watchdog device
> is updated based on the CPG_ERROR_RST2[ERROR_RST0/1/2] bit. Upon consumig
> CPG_ERROR_RST2[ERROR_RST0/1/2] bit we clear it.

As syscon-cpg is available, can we get rid of Linux assuming TF_A/U-boot for configuring Error Reset
Select Registers(0x10420B04)for the watchdog to reset the system?

After this, each watchdog device node will have, selection{offset,bit} status{ offset,bit}
renesas,syscon-cpg-error-rst-sel = <&cpg 0xb04 1>;
renesas,syscon-cpg-error-rst = <&cpg 0xb40 1>;

Or

renesas,syscon-cpg-error-rst = < &cpg 0xb04 1 0xb40 1>;

Cheers,
Biju

Re: [PATCH v3 5/6] watchdog: rzv2h_wdt: Add support to retrieve the bootstatus information

[Lad, Prabhakar]

Hi Biju,

On Tue, Jan 14, 2025 at 9:55 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: 13 January 2025 11:24
> > Subject: [PATCH v3 5/6] watchdog: rzv2h_wdt: Add support to retrieve the bootstatus information
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > On the RZ/V2H(P) SoC we can determine if the current boot is due to `Power-on-Reset` or due to the
> > `Watchdog`. The information used to determine this is present on the CPG block.
> >
> > The CPG_ERROR_RSTm(m = 2 - 8) registers are set in response to an error interrupt causing an reset.
> > CPG_ERROR_RST2[ERROR_RST0/1/2] is set if there was an underflow/overflow on WDT1 causing an error
> > interrupt.
> >
> > To fetch this information from CPG block `syscon` is used and bootstatus field in the watchdog device
> > is updated based on the CPG_ERROR_RST2[ERROR_RST0/1/2] bit. Upon consumig
> > CPG_ERROR_RST2[ERROR_RST0/1/2] bit we clear it.
>
> As syscon-cpg is available, can we get rid of Linux assuming TF_A/U-boot for configuring Error Reset
> Select Registers(0x10420B04)for the watchdog to reset the system?
>
Agreed.

> After this, each watchdog device node will have, selection{offset,bit} status{ offset,bit}
> renesas,syscon-cpg-error-rst-sel = <&cpg 0xb04 1>;
> renesas,syscon-cpg-error-rst = <&cpg 0xb40 1>;
>
> Or
>
> renesas,syscon-cpg-error-rst = < &cpg 0xb04 1 0xb40 1>;
>
As we already have 0xb40 we can do 0xb40 - 0x3c to get `0xb04` in the
WDT driver and the same bit numbers can be re-used for
CPG_ERRORRST_SEL2,  so by this way we can avoid adding another
property in DT. And I think this works for G3E too?

Cheers,
Prabhakar

RE: [PATCH v3 5/6] watchdog: rzv2h_wdt: Add support to retrieve the bootstatus information

[Biju Das]

Hi Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 14 January 2025 10:57
> Subject: Re: [PATCH v3 5/6] watchdog: rzv2h_wdt: Add support to retrieve the bootstatus information
> 
> Hi Biju,
> 
> On Tue, Jan 14, 2025 at 9:55 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> > Hi Prabhakar,
> >
> > Thanks for the patch.
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: 13 January 2025 11:24
> > > Subject: [PATCH v3 5/6] watchdog: rzv2h_wdt: Add support to retrieve
> > > the bootstatus information
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > On the RZ/V2H(P) SoC we can determine if the current boot is due to
> > > `Power-on-Reset` or due to the `Watchdog`. The information used to determine this is present on
> the CPG block.
> > >
> > > The CPG_ERROR_RSTm(m = 2 - 8) registers are set in response to an error interrupt causing an
> reset.
> > > CPG_ERROR_RST2[ERROR_RST0/1/2] is set if there was an
> > > underflow/overflow on WDT1 causing an error interrupt.
> > >
> > > To fetch this information from CPG block `syscon` is used and
> > > bootstatus field in the watchdog device is updated based on the
> > > CPG_ERROR_RST2[ERROR_RST0/1/2] bit. Upon consumig CPG_ERROR_RST2[ERROR_RST0/1/2] bit we clear it.
> >
> > As syscon-cpg is available, can we get rid of Linux assuming
> > TF_A/U-boot for configuring Error Reset Select Registers(0x10420B04)for the watchdog to reset the
> system?
> >
> Agreed.
> 
> > After this, each watchdog device node will have, selection{offset,bit}
> > status{ offset,bit} renesas,syscon-cpg-error-rst-sel = <&cpg 0xb04 1>;
> > renesas,syscon-cpg-error-rst = <&cpg 0xb40 1>;
> >
> > Or
> >
> > renesas,syscon-cpg-error-rst = < &cpg 0xb04 1 0xb40 1>;
> >
> As we already have 0xb40 we can do 0xb40 - 0x3c to get `0xb04` in the WDT driver and the same bit
> numbers can be re-used for CPG_ERRORRST_SEL2,  so by this way we can avoid adding another property in
> DT. And I think this works for G3E too?

Yes, as there is 1:1 map between CPG_ERRORRST_SELm and CPG_ERROR_RSTm registers.

Cheers,
Biju

Re: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC

[Rob Herring]

On Mon, Jan 13, 2025 at 11:38:08AM +0000, Biju Das wrote:
> Hi Prabhakar,
> 
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: 13 January 2025 11:24
> > Subject: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC
> > 
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > 
> > Hi All,
> > 
> > This patch series adds SYSCON support to retrieve boot status information for RZ/V2H(P) SoC.
> > Summary of Changes,
> > 
> >     Clock:
> >         Add syscon compatible support to the CPG block in bindings and
> >         device trees.
> > 
> >     Watchdog:
> >         Document the renesas,r9a09g057-syscon-wdt-errorrst property.
> >         Update the watchdog driver to fetch and report boot status via
> >         Error Reset Registers (CPG_ERROR_RSTm).
> > 
> >     Device Tree:
> >         Add the syscon property to CPG and WDT nodes in R9A09G057 and
> >         R9A09G047 SoC DTSI.
> > 
> > These changes enable the watchdog driver to identify boot sources like Power-on Reset and Watchdog
> > Reset, improving system diagnostics.
> 
> This means that, we should assume U-boot/bootloader should not clear the WDT reset status bit.
> 
> If they clear it, there should be a way to propagate it from u-boot/bootloader to linux,
> otherwise, we get wrong bootstatus in linux.
> But the clearing of watchdog status by one of the cases: 
> 
> 1) u-boot identify the boot source and clear the status bit
> 2) u-boot identify the boot source and does not clear the status bit, but linux clear it.
> 3) u-boot does not touch WDT status bits, but linux clear it.

Sounds like the same problem as this[1]. If that works for you, please 
comment there. Always better if there is more than 1 user for something 
"common".

Rob

[1]https://lore.kernel.org/devicetree-spec/48defa98-9718-4997-86cb-b171187708a6@cherry.de/T/#u

Re: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC

[Guenter Roeck]

On 1/14/25 12:03, Rob Herring wrote:
> On Mon, Jan 13, 2025 at 11:38:08AM +0000, Biju Das wrote:
>> Hi Prabhakar,
>>
>>> -----Original Message-----
>>> From: Prabhakar <prabhakar.csengg@gmail.com>
>>> Sent: 13 January 2025 11:24
>>> Subject: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC
>>>
>>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>
>>> Hi All,
>>>
>>> This patch series adds SYSCON support to retrieve boot status information for RZ/V2H(P) SoC.
>>> Summary of Changes,
>>>
>>>      Clock:
>>>          Add syscon compatible support to the CPG block in bindings and
>>>          device trees.
>>>
>>>      Watchdog:
>>>          Document the renesas,r9a09g057-syscon-wdt-errorrst property.
>>>          Update the watchdog driver to fetch and report boot status via
>>>          Error Reset Registers (CPG_ERROR_RSTm).
>>>
>>>      Device Tree:
>>>          Add the syscon property to CPG and WDT nodes in R9A09G057 and
>>>          R9A09G047 SoC DTSI.
>>>
>>> These changes enable the watchdog driver to identify boot sources like Power-on Reset and Watchdog
>>> Reset, improving system diagnostics.
>>
>> This means that, we should assume U-boot/bootloader should not clear the WDT reset status bit.
>>
>> If they clear it, there should be a way to propagate it from u-boot/bootloader to linux,
>> otherwise, we get wrong bootstatus in linux.
>> But the clearing of watchdog status by one of the cases:
>>
>> 1) u-boot identify the boot source and clear the status bit
>> 2) u-boot identify the boot source and does not clear the status bit, but linux clear it.
>> 3) u-boot does not touch WDT status bits, but linux clear it.
> 
> Sounds like the same problem as this[1]. If that works for you, please
> comment there. Always better if there is more than 1 user for something
> "common".
> 
> Rob
> 
> [1]https://lore.kernel.org/devicetree-spec/48defa98-9718-4997-86cb-b171187708a6@cherry.de/T/#u

If this ends up being provided through /chosen, it should probably be supported
in the watchdog core.

Guenter

Re: [PATCH v3 4/6] dt-bindings: watchdog: renesas: Document `renesas,syscon-cpg-error-rst` property

[Rob Herring]

On Mon, Jan 13, 2025 at 11:23:47AM +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> The RZ/V2H(P) CPG block includes Error Reset Registers (CPG_ERROR_RSTm).
> A system reset is triggered in response to error interrupt factors, and
> the corresponding bit is set in the CPG_ERROR_RSTm register. These
> registers can be utilized by various IP blocks as needed.
> 
> In the event of a watchdog overflow or underflow, a system reset is issued,
> and the CPG_ERROR_RST2[0/1/2/3] bits are set depending on the watchdog in
> use: CM33 = 0, CA55 = 1, CR8_0 = 2, CR8_1 = 3. For the watchdog driver to
> determine and report the current boot status, it needs to read the
> CPG_ERROR_RST2[0/1/2/3]bits and provide this information to the user upon
> request.
> 
> To facilitate this operation, add `renesas,syscon-cpg-error-rst`
> property to the WDT node, which maps to the `syscon` CPG node, enabling
> retrieval of the necessary information.
> 
> Additionally, the property is marked as required for the RZ/V2H(P) SoC to
> ensure future compatibility (e.g., where the same IP block is present on
> the RZ/G3E SoC) and explicitly disallowed for other SoCs.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Note, this change doesnt break any ABI, as the subsequent driver patch handles
> the case elegantly if the `syscon` node is missing to handle backward compatibility.
> 
> v2->v3
> - No change
> 
> v1->v2
> - Renamed `renesas,r9a09g057-syscon-wdt-errorrst` to `renesas,syscon-cpg-error-rst`
> - Updated commit message
> ---
>  .../bindings/watchdog/renesas,wdt.yaml          | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
> index 29ada89fdcdc..ca62ae8b1b0c 100644
> --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
> @@ -112,6 +112,19 @@ properties:
>  
>    timeout-sec: true
>  
> +  renesas,syscon-cpg-error-rst:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    description:
> +      The first cell is a phandle to the SYSCON entry required to obtain
> +      the current boot status. The second cell specifies the CPG_ERROR_RSTm
> +      register offset within the SYSCON, and the third cell indicates the
> +      bit within the CPG_ERROR_RSTm register.
> +    items:
> +      - items:
> +          - description: Phandle to the CPG node
> +          - description: The CPG_ERROR_RSTm register offset
> +          - description: The bit within CPG_ERROR_RSTm register of interest

Why does the watchdog node care about the reset reason? Why doesn't the 
CPG handle that? Seems like this is the Linux watchdog subsystem handles 
reset reasons, so let's stick a property in the watchdog node. Sounds 
like OS design dictating bindings.

Rob

Re: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC

[Lad, Prabhakar]

Hi Guenter and Rob,

On Tue, Jan 14, 2025 at 8:17 PM Guenter Roeck <linux@roeck-us.net> wrote:
>
> On 1/14/25 12:03, Rob Herring wrote:
> > On Mon, Jan 13, 2025 at 11:38:08AM +0000, Biju Das wrote:
> >> Hi Prabhakar,
> >>
> >>> -----Original Message-----
> >>> From: Prabhakar <prabhakar.csengg@gmail.com>
> >>> Sent: 13 January 2025 11:24
> >>> Subject: [PATCH v3 0/6] Add support to retrieve the bootstatus from watchdog for RZ/V2H(P) SoC
> >>>
> >>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >>>
> >>> Hi All,
> >>>
> >>> This patch series adds SYSCON support to retrieve boot status information for RZ/V2H(P) SoC.
> >>> Summary of Changes,
> >>>
> >>>      Clock:
> >>>          Add syscon compatible support to the CPG block in bindings and
> >>>          device trees.
> >>>
> >>>      Watchdog:
> >>>          Document the renesas,r9a09g057-syscon-wdt-errorrst property.
> >>>          Update the watchdog driver to fetch and report boot status via
> >>>          Error Reset Registers (CPG_ERROR_RSTm).
> >>>
> >>>      Device Tree:
> >>>          Add the syscon property to CPG and WDT nodes in R9A09G057 and
> >>>          R9A09G047 SoC DTSI.
> >>>
> >>> These changes enable the watchdog driver to identify boot sources like Power-on Reset and Watchdog
> >>> Reset, improving system diagnostics.
> >>
> >> This means that, we should assume U-boot/bootloader should not clear the WDT reset status bit.
> >>
> >> If they clear it, there should be a way to propagate it from u-boot/bootloader to linux,
> >> otherwise, we get wrong bootstatus in linux.
> >> But the clearing of watchdog status by one of the cases:
> >>
> >> 1) u-boot identify the boot source and clear the status bit
> >> 2) u-boot identify the boot source and does not clear the status bit, but linux clear it.
> >> 3) u-boot does not touch WDT status bits, but linux clear it.
> >
> > Sounds like the same problem as this[1]. If that works for you, please
> > comment there. Always better if there is more than 1 user for something
> > "common".
> >
> > Rob
> >
> > [1]https://lore.kernel.org/devicetree-spec/48defa98-9718-4997-86cb-b171187708a6@cherry.de/T/#u
>
> If this ends up being provided through /chosen, it should probably be supported
> in the watchdog core.
>
There wasn't any conclusion on the thread [0]. Can you please
recommend how you want me to proceed on this series.

[0] https://lore.kernel.org/devicetree-spec/48defa98-9718-4997-86cb-b171187708a6@cherry.de/T/#m2f1c7f5c8166522982cecf9351903ab06ca4f9ee

Cheers,
Prabhakar