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Date: Fri, 31 Jan 2025 17:17:35 +0000
From: Conor Dooley <conor@kernel.org>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>,
	Wolfram Sang <wsa+renesas@sang-engineering.com>,
	linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Biju Das <biju.das.au@gmail.com>
Subject: Re: [PATCH v2 1/8] dt-bindings: mmc: renesas,sdhi: Document RZ/G3E
 support
Message-ID: <20250131-dangle-obtain-30ffa8a44083@spud>
References: <20250131112429.119882-1-biju.das.jz@bp.renesas.com>
 <20250131112429.119882-2-biju.das.jz@bp.renesas.com>
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On Fri, Jan 31, 2025 at 11:24:16AM +0000, Biju Das wrote:
> The SD/MMC block on the RZ/G3E ("R9A09G047") SoC is similar to that
> of the RZ/V2H, but the SD0 channel has only dedicated pins, so we must
> use SD_STATUS register to control voltage and power enable (internal
> regulator), for non-fixed voltage (SD) MMC interface. However, it is
> optional for fixed voltage MMC interface (eMMC).
>=20
> For SD1 and SD2 channels, we can either use gpio regulator or internal
> regulator (using SD_STATUS register) for voltage switching.
>=20
> Document RZ/G3E SDHI IP support with optional internal regulator for
> both RZ/G3E and RZ/V2H SoC.
>=20
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

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Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZ50FrwAKCRB4tDGHoIJi
0mTTAP9hMeaxexsvfROzaDoowF7ghWEzn8zaXnkyG2lhXeJgGQEAwYRi02ArAkkT
L5DAmPQ0lCwQs6yMpQ3EzuOUqoCoqQA=
=x6j+
-----END PGP SIGNATURE-----

--2aWd9LJ+bsJ8g84Q--