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Sun, 02 Feb 2025 04:25:34 -0800 (PST) Date: Sun, 2 Feb 2025 17:55:27 +0530 From: Manivannan Sadhasivam To: Christian Bruel Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, jingoohan1@gmail.com, p.zabel@pengutronix.de, johan+linaro@kernel.org, quic_schintav@quicinc.com, cassel@kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, fabrice.gasnier@foss.st.com Subject: Re: [PATCH v4 01/10] dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings Message-ID: <20250202122527.ggy5ccz7o4umyhif@thinkpad> References: <20250128120745.334377-1-christian.bruel@foss.st.com> <20250128120745.334377-2-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250128120745.334377-2-christian.bruel@foss.st.com> On Tue, Jan 28, 2025 at 01:07:36PM +0100, Christian Bruel wrote: [...] > + pcie@48400000 { > + compatible = "st,stm32mp25-pcie-rc"; > + device_type = "pci"; > + reg = <0x48400000 0x400000>, > + <0x10000000 0x10000>; > + reg-names = "dbi", "config"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>, > + <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>, > + <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>; > + dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>; > + clocks = <&rcc CK_BUS_PCIE>; > + resets = <&rcc PCIE_R>; > + msi-parent = <&v2m0>; > + wakeup-source; Does this property really need to be present? If the WAKE# gpio is supported, isn't it implied that the RC is a wakeup source? - Mani -- மணிவண்ணன் சதாசிவம்