* [PATCH 1/4] dt-bindings: reset: sophgo: Add CV1800B support
2025-02-09 12:29 [PATCH 0/4] riscv: sophgo: cv18xx: Add reset generator support Inochi Amaoto
@ 2025-02-09 12:29 ` Inochi Amaoto
2025-02-10 1:00 ` Chen Wang
2025-02-12 19:49 ` Rob Herring (Arm)
2025-02-09 12:29 ` [PATCH 2/4] reset: simple: add support for Sophgo CV1800B Inochi Amaoto
` (2 subsequent siblings)
3 siblings, 2 replies; 18+ messages in thread
From: Inochi Amaoto @ 2025-02-09 12:29 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Thomas Bonnefille, Jisheng Zhang
Cc: Inochi Amaoto, devicetree, linux-kernel, linux-riscv, Yixun Lan,
Longbin Li
Add bindings for the reset generator on the SOPHGO CV1800B
RISC-V SoC.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
.../devicetree/bindings/reset/sophgo,sg2042-reset.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
index 76e1931f0908..73f8009698f3 100644
--- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
@@ -11,7 +11,9 @@ maintainers:
properties:
compatible:
- const: sophgo,sg2042-reset
+ enum:
+ - sophgo,cv1800b-reset
+ - sophgo,sg2042-reset
reg:
maxItems: 1
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 1/4] dt-bindings: reset: sophgo: Add CV1800B support
2025-02-09 12:29 ` [PATCH 1/4] dt-bindings: reset: sophgo: Add CV1800B support Inochi Amaoto
@ 2025-02-10 1:00 ` Chen Wang
2025-02-10 4:44 ` Inochi Amaoto
2025-02-12 19:49 ` Rob Herring (Arm)
1 sibling, 1 reply; 18+ messages in thread
From: Chen Wang @ 2025-02-10 1:00 UTC (permalink / raw)
To: Inochi Amaoto, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Thomas Bonnefille, Jisheng Zhang
Cc: devicetree, linux-kernel, linux-riscv, Yixun Lan, Longbin Li
On 2025/2/9 20:29, Inochi Amaoto wrote:
> Add bindings for the reset generator on the SOPHGO CV1800B
> RISC-V SoC.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> .../devicetree/bindings/reset/sophgo,sg2042-reset.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> index 76e1931f0908..73f8009698f3 100644
> --- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> @@ -11,7 +11,9 @@ maintainers:
>
> properties:
> compatible:
> - const: sophgo,sg2042-reset
> + enum:
> + - sophgo,cv1800b-reset
I have a question, if this patchset is for all cv18xx products? If so,
can we use "cv18xx" instead of "cv1800b"?
> + - sophgo,sg2042-reset
>
> reg:
> maxItems: 1
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/4] dt-bindings: reset: sophgo: Add CV1800B support
2025-02-10 1:00 ` Chen Wang
@ 2025-02-10 4:44 ` Inochi Amaoto
0 siblings, 0 replies; 18+ messages in thread
From: Inochi Amaoto @ 2025-02-10 4:44 UTC (permalink / raw)
To: Chen Wang, Inochi Amaoto, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Thomas Bonnefille, Jisheng Zhang
Cc: devicetree, linux-kernel, linux-riscv, Yixun Lan, Longbin Li
On Mon, Feb 10, 2025 at 09:00:24AM +0800, Chen Wang wrote:
>
> On 2025/2/9 20:29, Inochi Amaoto wrote:
> > Add bindings for the reset generator on the SOPHGO CV1800B
> > RISC-V SoC.
> >
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > ---
> > .../devicetree/bindings/reset/sophgo,sg2042-reset.yaml | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> > index 76e1931f0908..73f8009698f3 100644
> > --- a/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> > +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml
> > @@ -11,7 +11,9 @@ maintainers:
> > properties:
> > compatible:
> > - const: sophgo,sg2042-reset
> > + enum:
> > + - sophgo,cv1800b-reset
>
> I have a question, if this patchset is for all cv18xx products? If so, can
> we use "cv18xx" instead of "cv1800b"?
>
Negative, we can only use a real board compatiable for the device.
This is why I use cv1800b as a base.
Regards,
Inochi
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/4] dt-bindings: reset: sophgo: Add CV1800B support
2025-02-09 12:29 ` [PATCH 1/4] dt-bindings: reset: sophgo: Add CV1800B support Inochi Amaoto
2025-02-10 1:00 ` Chen Wang
@ 2025-02-12 19:49 ` Rob Herring (Arm)
1 sibling, 0 replies; 18+ messages in thread
From: Rob Herring (Arm) @ 2025-02-12 19:49 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Philipp Zabel, linux-riscv, Thomas Bonnefille, devicetree,
Albert Ou, Inochi Amaoto, Jisheng Zhang, linux-kernel,
Palmer Dabbelt, Paul Walmsley, Longbin Li, Chen Wang, Yixun Lan,
Conor Dooley, Krzysztof Kozlowski
On Sun, 09 Feb 2025 20:29:32 +0800, Inochi Amaoto wrote:
> Add bindings for the reset generator on the SOPHGO CV1800B
> RISC-V SoC.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> .../devicetree/bindings/reset/sophgo,sg2042-reset.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/4] reset: simple: add support for Sophgo CV1800B
2025-02-09 12:29 [PATCH 0/4] riscv: sophgo: cv18xx: Add reset generator support Inochi Amaoto
2025-02-09 12:29 ` [PATCH 1/4] dt-bindings: reset: sophgo: Add CV1800B support Inochi Amaoto
@ 2025-02-09 12:29 ` Inochi Amaoto
2025-02-09 13:46 ` Yixun Lan
2025-02-09 12:29 ` [PATCH 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC Inochi Amaoto
2025-02-09 12:29 ` [PATCH 4/4] riscv: dts: sophgo: add reset configuration " Inochi Amaoto
3 siblings, 1 reply; 18+ messages in thread
From: Inochi Amaoto @ 2025-02-09 12:29 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Thomas Bonnefille, Jisheng Zhang
Cc: Inochi Amaoto, devicetree, linux-kernel, linux-riscv, Yixun Lan,
Longbin Li
Reuse reset-simple driver for the Sophgo CV1800B reset generator.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/reset/reset-simple.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
index 276067839830..79e94ecfe4f5 100644
--- a/drivers/reset/reset-simple.c
+++ b/drivers/reset/reset-simple.c
@@ -151,6 +151,8 @@ static const struct of_device_id reset_simple_dt_ids[] = {
{ .compatible = "snps,dw-high-reset" },
{ .compatible = "snps,dw-low-reset",
.data = &reset_simple_active_low },
+ { .compatible = "sophgo,cv1800b-reset",
+ .data = &reset_simple_active_low },
{ .compatible = "sophgo,sg2042-reset",
.data = &reset_simple_active_low },
{ /* sentinel */ },
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 2/4] reset: simple: add support for Sophgo CV1800B
2025-02-09 12:29 ` [PATCH 2/4] reset: simple: add support for Sophgo CV1800B Inochi Amaoto
@ 2025-02-09 13:46 ` Yixun Lan
2025-02-10 4:50 ` Inochi Amaoto
0 siblings, 1 reply; 18+ messages in thread
From: Yixun Lan @ 2025-02-09 13:46 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Thomas Bonnefille, Jisheng Zhang, devicetree,
linux-kernel, linux-riscv, Longbin Li
Hi
On 20:29 Sun 09 Feb , Inochi Amaoto wrote:
> Reuse reset-simple driver for the Sophgo CV1800B reset generator.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> drivers/reset/reset-simple.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
> index 276067839830..79e94ecfe4f5 100644
> --- a/drivers/reset/reset-simple.c
> +++ b/drivers/reset/reset-simple.c
> @@ -151,6 +151,8 @@ static const struct of_device_id reset_simple_dt_ids[] = {
> { .compatible = "snps,dw-high-reset" },
> { .compatible = "snps,dw-low-reset",
> .data = &reset_simple_active_low },
> + { .compatible = "sophgo,cv1800b-reset",
> + .data = &reset_simple_active_low },
I think this isn't really a problem, but..
quite a lot SoCs use the "simple active low" IP,
can we introduce a generic compatible? so can set as fallback..
intead of growing this compatible data each time for new SoC
> { .compatible = "sophgo,sg2042-reset",
> .data = &reset_simple_active_low },
> { /* sentinel */ },
> --
> 2.48.1
>
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 2/4] reset: simple: add support for Sophgo CV1800B
2025-02-09 13:46 ` Yixun Lan
@ 2025-02-10 4:50 ` Inochi Amaoto
0 siblings, 0 replies; 18+ messages in thread
From: Inochi Amaoto @ 2025-02-10 4:50 UTC (permalink / raw)
To: Yixun Lan, Inochi Amaoto
Cc: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Thomas Bonnefille, Jisheng Zhang, devicetree,
linux-kernel, linux-riscv, Longbin Li
On Sun, Feb 09, 2025 at 01:46:52PM +0000, Yixun Lan wrote:
> Hi
>
> On 20:29 Sun 09 Feb , Inochi Amaoto wrote:
> > Reuse reset-simple driver for the Sophgo CV1800B reset generator.
> >
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > ---
> > drivers/reset/reset-simple.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
> > index 276067839830..79e94ecfe4f5 100644
> > --- a/drivers/reset/reset-simple.c
> > +++ b/drivers/reset/reset-simple.c
> > @@ -151,6 +151,8 @@ static const struct of_device_id reset_simple_dt_ids[] = {
> > { .compatible = "snps,dw-high-reset" },
> > { .compatible = "snps,dw-low-reset",
> > .data = &reset_simple_active_low },
> > + { .compatible = "sophgo,cv1800b-reset",
> > + .data = &reset_simple_active_low },
> I think this isn't really a problem, but..
>
> quite a lot SoCs use the "simple active low" IP,
> can we introduce a generic compatible? so can set as fallback..
> intead of growing this compatible data each time for new SoC
>
I have already considered this idea and design something like
"reset-simple-high" and "reset-simple-low" to cover these
generic scenarios. But adding something like this is too hard
for me to migrate existing devices. So finally I drop this and
added the device id, as I am not sure whether is better.
Regards,
Inochi
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
2025-02-09 12:29 [PATCH 0/4] riscv: sophgo: cv18xx: Add reset generator support Inochi Amaoto
2025-02-09 12:29 ` [PATCH 1/4] dt-bindings: reset: sophgo: Add CV1800B support Inochi Amaoto
2025-02-09 12:29 ` [PATCH 2/4] reset: simple: add support for Sophgo CV1800B Inochi Amaoto
@ 2025-02-09 12:29 ` Inochi Amaoto
2025-02-10 0:55 ` Chen Wang
2025-05-23 5:20 ` Junhui Liu
2025-02-09 12:29 ` [PATCH 4/4] riscv: dts: sophgo: add reset configuration " Inochi Amaoto
3 siblings, 2 replies; 18+ messages in thread
From: Inochi Amaoto @ 2025-02-09 12:29 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Thomas Bonnefille, Jisheng Zhang
Cc: Inochi Amaoto, devicetree, linux-kernel, linux-riscv, Yixun Lan,
Longbin Li
Add reset generator node for all CV18XX series SoC.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++++++
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 7 ++
2 files changed, 105 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-reset.h b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
new file mode 100644
index 000000000000..3d9aa9ec7e90
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (C) 2025 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#ifndef _SOPHGO_CV18XX_RESET
+#define _SOPHGO_CV18XX_RESET
+
+#define RST_DDR 2
+#define RST_H264C 3
+#define RST_JPEG 4
+#define RST_H265C 5
+#define RST_VIPSYS 6
+#define RST_TDMA 7
+#define RST_TPU 8
+#define RST_TPUSYS 9
+#define RST_USB 11
+#define RST_ETH0 12
+#define RST_ETH1 13
+#define RST_NAND 14
+#define RST_EMMC 15
+#define RST_SD0 16
+#define RST_SDMA 18
+#define RST_I2S0 19
+#define RST_I2S1 20
+#define RST_I2S2 21
+#define RST_I2S3 22
+#define RST_UART0 23
+#define RST_UART1 24
+#define RST_UART2 25
+#define RST_UART3 26
+#define RST_I2C0 27
+#define RST_I2C1 28
+#define RST_I2C2 29
+#define RST_I2C3 30
+#define RST_I2C4 31
+#define RST_PWM0 32
+#define RST_PWM1 33
+#define RST_PWM2 34
+#define RST_PWM3 35
+#define RST_SPI0 40
+#define RST_SPI1 41
+#define RST_SPI2 42
+#define RST_SPI3 43
+#define RST_GPIO0 44
+#define RST_GPIO1 45
+#define RST_GPIO2 46
+#define RST_EFUSE 47
+#define RST_WDT 48
+#define RST_AHB_ROM 49
+#define RST_SPIC 50
+#define RST_TEMPSEN 51
+#define RST_SARADC 52
+#define RST_COMBO_PHY0 58
+#define RST_SPI_NAND 61
+#define RST_SE 62
+#define RST_UART4 74
+#define RST_GPIO3 75
+#define RST_SYSTEM 76
+#define RST_TIMER 77
+#define RST_TIMER0 78
+#define RST_TIMER1 79
+#define RST_TIMER2 80
+#define RST_TIMER3 81
+#define RST_TIMER4 82
+#define RST_TIMER5 83
+#define RST_TIMER6 84
+#define RST_TIMER7 85
+#define RST_WGN0 86
+#define RST_WGN1 87
+#define RST_WGN2 88
+#define RST_KEYSCAN 89
+#define RST_AUDDAC 91
+#define RST_AUDDAC_APB 92
+#define RST_AUDADC 93
+#define RST_VCSYS 95
+#define RST_ETHPHY 96
+#define RST_ETHPHY_APB 97
+#define RST_AUDSRC 98
+#define RST_VIP_CAM0 99
+#define RST_WDT1 100
+#define RST_WDT2 101
+#define RST_AUTOCLEAR_CPUCORE0 128
+#define RST_AUTOCLEAR_CPUCORE1 129
+#define RST_AUTOCLEAR_CPUCORE2 130
+#define RST_AUTOCLEAR_CPUCORE3 131
+#define RST_AUTOCLEAR_CPUSYS0 132
+#define RST_AUTOCLEAR_CPUSYS1 133
+#define RST_AUTOCLEAR_CPUSYS2 134
+#define RST_CPUCORE0 160
+#define RST_CPUCORE1 161
+#define RST_CPUCORE2 162
+#define RST_CPUCORE3 163
+#define RST_CPUSYS0 164
+#define RST_CPUSYS1 165
+#define RST_CPUSYS2 166
+
+#endif /* _SOPHGO_CV18XX_RESET */
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index c18822ec849f..9aa28ade73a4 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/sophgo,cv1800.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv18xx-reset.h"
/ {
#address-cells = <1>;
@@ -61,6 +62,12 @@ clk: clock-controller@3002000 {
#clock-cells = <1>;
};
+ rst: reset-controller@3003000 {
+ compatible = "sophgo,cv1800b-reset";
+ reg = <0x3003000 0x1000>;
+ #reset-cells = <1>;
+ };
+
gpio0: gpio@3020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3020000 0x1000>;
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
2025-02-09 12:29 ` [PATCH 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC Inochi Amaoto
@ 2025-02-10 0:55 ` Chen Wang
2025-02-10 1:20 ` Yixun Lan
2025-05-23 5:20 ` Junhui Liu
1 sibling, 1 reply; 18+ messages in thread
From: Chen Wang @ 2025-02-10 0:55 UTC (permalink / raw)
To: Inochi Amaoto, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Thomas Bonnefille, Jisheng Zhang
Cc: devicetree, linux-kernel, linux-riscv, Yixun Lan, Longbin Li
On 2025/2/9 20:29, Inochi Amaoto wrote:
> Add reset generator node for all CV18XX series SoC.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++++++
Why it's not include/dt-bindings/reset/sophgo,cv18xx-reset.h?
Regards,
Chen
> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 7 ++
> 2 files changed, 105 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-reset.h b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
> new file mode 100644
> index 000000000000..3d9aa9ec7e90
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
> @@ -0,0 +1,98 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (C) 2025 Inochi Amaoto <inochiama@outlook.com>
> + */
> +
> +#ifndef _SOPHGO_CV18XX_RESET
> +#define _SOPHGO_CV18XX_RESET
> +
> +#define RST_DDR 2
> +#define RST_H264C 3
> +#define RST_JPEG 4
> +#define RST_H265C 5
> +#define RST_VIPSYS 6
> +#define RST_TDMA 7
> +#define RST_TPU 8
> +#define RST_TPUSYS 9
> +#define RST_USB 11
> +#define RST_ETH0 12
> +#define RST_ETH1 13
> +#define RST_NAND 14
> +#define RST_EMMC 15
> +#define RST_SD0 16
> +#define RST_SDMA 18
> +#define RST_I2S0 19
> +#define RST_I2S1 20
> +#define RST_I2S2 21
> +#define RST_I2S3 22
> +#define RST_UART0 23
> +#define RST_UART1 24
> +#define RST_UART2 25
> +#define RST_UART3 26
> +#define RST_I2C0 27
> +#define RST_I2C1 28
> +#define RST_I2C2 29
> +#define RST_I2C3 30
> +#define RST_I2C4 31
> +#define RST_PWM0 32
> +#define RST_PWM1 33
> +#define RST_PWM2 34
> +#define RST_PWM3 35
> +#define RST_SPI0 40
> +#define RST_SPI1 41
> +#define RST_SPI2 42
> +#define RST_SPI3 43
> +#define RST_GPIO0 44
> +#define RST_GPIO1 45
> +#define RST_GPIO2 46
> +#define RST_EFUSE 47
> +#define RST_WDT 48
> +#define RST_AHB_ROM 49
> +#define RST_SPIC 50
> +#define RST_TEMPSEN 51
> +#define RST_SARADC 52
> +#define RST_COMBO_PHY0 58
> +#define RST_SPI_NAND 61
> +#define RST_SE 62
> +#define RST_UART4 74
> +#define RST_GPIO3 75
> +#define RST_SYSTEM 76
> +#define RST_TIMER 77
> +#define RST_TIMER0 78
> +#define RST_TIMER1 79
> +#define RST_TIMER2 80
> +#define RST_TIMER3 81
> +#define RST_TIMER4 82
> +#define RST_TIMER5 83
> +#define RST_TIMER6 84
> +#define RST_TIMER7 85
> +#define RST_WGN0 86
> +#define RST_WGN1 87
> +#define RST_WGN2 88
> +#define RST_KEYSCAN 89
> +#define RST_AUDDAC 91
> +#define RST_AUDDAC_APB 92
> +#define RST_AUDADC 93
> +#define RST_VCSYS 95
> +#define RST_ETHPHY 96
> +#define RST_ETHPHY_APB 97
> +#define RST_AUDSRC 98
> +#define RST_VIP_CAM0 99
> +#define RST_WDT1 100
> +#define RST_WDT2 101
> +#define RST_AUTOCLEAR_CPUCORE0 128
> +#define RST_AUTOCLEAR_CPUCORE1 129
> +#define RST_AUTOCLEAR_CPUCORE2 130
> +#define RST_AUTOCLEAR_CPUCORE3 131
> +#define RST_AUTOCLEAR_CPUSYS0 132
> +#define RST_AUTOCLEAR_CPUSYS1 133
> +#define RST_AUTOCLEAR_CPUSYS2 134
> +#define RST_CPUCORE0 160
> +#define RST_CPUCORE1 161
> +#define RST_CPUCORE2 162
> +#define RST_CPUCORE3 163
> +#define RST_CPUSYS0 164
> +#define RST_CPUSYS1 165
> +#define RST_CPUSYS2 166
> +
> +#endif /* _SOPHGO_CV18XX_RESET */
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index c18822ec849f..9aa28ade73a4 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/clock/sophgo,cv1800.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> +#include "cv18xx-reset.h"
>
> / {
> #address-cells = <1>;
> @@ -61,6 +62,12 @@ clk: clock-controller@3002000 {
> #clock-cells = <1>;
> };
>
> + rst: reset-controller@3003000 {
> + compatible = "sophgo,cv1800b-reset";
> + reg = <0x3003000 0x1000>;
> + #reset-cells = <1>;
> + };
> +
> gpio0: gpio@3020000 {
> compatible = "snps,dw-apb-gpio";
> reg = <0x3020000 0x1000>;
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
2025-02-10 0:55 ` Chen Wang
@ 2025-02-10 1:20 ` Yixun Lan
2025-02-10 2:56 ` Chen Wang
0 siblings, 1 reply; 18+ messages in thread
From: Yixun Lan @ 2025-02-10 1:20 UTC (permalink / raw)
To: Chen Wang
Cc: Inochi Amaoto, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Thomas Bonnefille, Jisheng Zhang, devicetree,
linux-kernel, linux-riscv, Longbin Li
Hi Chen:
On 08:55 Mon 10 Feb , Chen Wang wrote:
>
> On 2025/2/9 20:29, Inochi Amaoto wrote:
> > Add reset generator node for all CV18XX series SoC.
> >
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > ---
> > arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++++++
>
> Why it's not include/dt-bindings/reset/sophgo,cv18xx-reset.h?
>
then first need to answer if it's really a binding, there are some disucssions
I personally favor Inochi's way here
https://lore.kernel.org/linux-devicetree/c7e243e3-3f61-4d63-8727-3837838bdfcc@linaro.org
https://lore.kernel.org/linux-devicetree/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
> Regards,
>
> Chen
>
> > arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 7 ++
> > 2 files changed, 105 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h
> >
> > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-reset.h b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
> > new file mode 100644
> > index 000000000000..3d9aa9ec7e90
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
> > @@ -0,0 +1,98 @@
> > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> > +/*
> > + * Copyright (C) 2025 Inochi Amaoto <inochiama@outlook.com>
> > + */
> > +
> > +#ifndef _SOPHGO_CV18XX_RESET
> > +#define _SOPHGO_CV18XX_RESET
> > +
> > +#define RST_DDR 2
> > +#define RST_H264C 3
> > +#define RST_JPEG 4
> > +#define RST_H265C 5
> > +#define RST_VIPSYS 6
> > +#define RST_TDMA 7
> > +#define RST_TPU 8
> > +#define RST_TPUSYS 9
> > +#define RST_USB 11
> > +#define RST_ETH0 12
> > +#define RST_ETH1 13
> > +#define RST_NAND 14
> > +#define RST_EMMC 15
> > +#define RST_SD0 16
> > +#define RST_SDMA 18
> > +#define RST_I2S0 19
> > +#define RST_I2S1 20
> > +#define RST_I2S2 21
> > +#define RST_I2S3 22
> > +#define RST_UART0 23
> > +#define RST_UART1 24
> > +#define RST_UART2 25
> > +#define RST_UART3 26
> > +#define RST_I2C0 27
> > +#define RST_I2C1 28
> > +#define RST_I2C2 29
> > +#define RST_I2C3 30
> > +#define RST_I2C4 31
> > +#define RST_PWM0 32
> > +#define RST_PWM1 33
> > +#define RST_PWM2 34
> > +#define RST_PWM3 35
> > +#define RST_SPI0 40
> > +#define RST_SPI1 41
> > +#define RST_SPI2 42
> > +#define RST_SPI3 43
> > +#define RST_GPIO0 44
> > +#define RST_GPIO1 45
> > +#define RST_GPIO2 46
> > +#define RST_EFUSE 47
> > +#define RST_WDT 48
> > +#define RST_AHB_ROM 49
> > +#define RST_SPIC 50
> > +#define RST_TEMPSEN 51
> > +#define RST_SARADC 52
> > +#define RST_COMBO_PHY0 58
> > +#define RST_SPI_NAND 61
> > +#define RST_SE 62
> > +#define RST_UART4 74
> > +#define RST_GPIO3 75
> > +#define RST_SYSTEM 76
> > +#define RST_TIMER 77
> > +#define RST_TIMER0 78
> > +#define RST_TIMER1 79
> > +#define RST_TIMER2 80
> > +#define RST_TIMER3 81
> > +#define RST_TIMER4 82
> > +#define RST_TIMER5 83
> > +#define RST_TIMER6 84
> > +#define RST_TIMER7 85
> > +#define RST_WGN0 86
> > +#define RST_WGN1 87
> > +#define RST_WGN2 88
> > +#define RST_KEYSCAN 89
> > +#define RST_AUDDAC 91
> > +#define RST_AUDDAC_APB 92
> > +#define RST_AUDADC 93
> > +#define RST_VCSYS 95
> > +#define RST_ETHPHY 96
> > +#define RST_ETHPHY_APB 97
> > +#define RST_AUDSRC 98
> > +#define RST_VIP_CAM0 99
> > +#define RST_WDT1 100
> > +#define RST_WDT2 101
> > +#define RST_AUTOCLEAR_CPUCORE0 128
> > +#define RST_AUTOCLEAR_CPUCORE1 129
> > +#define RST_AUTOCLEAR_CPUCORE2 130
> > +#define RST_AUTOCLEAR_CPUCORE3 131
> > +#define RST_AUTOCLEAR_CPUSYS0 132
> > +#define RST_AUTOCLEAR_CPUSYS1 133
> > +#define RST_AUTOCLEAR_CPUSYS2 134
> > +#define RST_CPUCORE0 160
> > +#define RST_CPUCORE1 161
> > +#define RST_CPUCORE2 162
> > +#define RST_CPUCORE3 163
> > +#define RST_CPUSYS0 164
> > +#define RST_CPUSYS1 165
> > +#define RST_CPUSYS2 166
> > +
> > +#endif /* _SOPHGO_CV18XX_RESET */
> > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> > index c18822ec849f..9aa28ade73a4 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> > @@ -7,6 +7,7 @@
> > #include <dt-bindings/clock/sophgo,cv1800.h>
> > #include <dt-bindings/gpio/gpio.h>
> > #include <dt-bindings/interrupt-controller/irq.h>
> > +#include "cv18xx-reset.h"
> >
> > / {
> > #address-cells = <1>;
> > @@ -61,6 +62,12 @@ clk: clock-controller@3002000 {
> > #clock-cells = <1>;
> > };
> >
> > + rst: reset-controller@3003000 {
> > + compatible = "sophgo,cv1800b-reset";
> > + reg = <0x3003000 0x1000>;
> > + #reset-cells = <1>;
> > + };
> > +
> > gpio0: gpio@3020000 {
> > compatible = "snps,dw-apb-gpio";
> > reg = <0x3020000 0x1000>;
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
2025-02-10 1:20 ` Yixun Lan
@ 2025-02-10 2:56 ` Chen Wang
2025-02-10 4:55 ` Inochi Amaoto
0 siblings, 1 reply; 18+ messages in thread
From: Chen Wang @ 2025-02-10 2:56 UTC (permalink / raw)
To: Yixun Lan
Cc: Inochi Amaoto, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Thomas Bonnefille, Jisheng Zhang, devicetree,
linux-kernel, linux-riscv, Longbin Li
On 2025/2/10 9:20, Yixun Lan wrote:
> Hi Chen:
>
> On 08:55 Mon 10 Feb , Chen Wang wrote:
>> On 2025/2/9 20:29, Inochi Amaoto wrote:
>>> Add reset generator node for all CV18XX series SoC.
>>>
>>> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
>>> ---
>>> arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++++++
>> Why it's not include/dt-bindings/reset/sophgo,cv18xx-reset.h?
>>
> then first need to answer if it's really a binding, there are some disucssions
> I personally favor Inochi's way here
>
> https://lore.kernel.org/linux-devicetree/c7e243e3-3f61-4d63-8727-3837838bdfcc@linaro.org
> https://lore.kernel.org/linux-devicetree/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
Well, it's fine if you don't want to define it as binding just because
the ids are not continuous. In fact, for simple-reset, I think there is
no big problem to define it as bindings.
Actually, in the first link upon, I see Krzysztof also said
"simple-reset is an exception."
I recall we ever discussed this when Jisheng submitted the first version
of reset driver for cv18xx. FYI. See
https://lore.kernel.org/linux-riscv/42ad3f60-2755-4d3b-a766-8e4404f76a7c@linaro.org/.
>> Regards,
>>
>> Chen
>>
>>> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 7 ++
>>> 2 files changed, 105 insertions(+)
>>> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h
>>>
>>> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-reset.h b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
>>> new file mode 100644
>>> index 000000000000..3d9aa9ec7e90
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
>>> @@ -0,0 +1,98 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
>>> +/*
>>> + * Copyright (C) 2025 Inochi Amaoto <inochiama@outlook.com>
>>> + */
>>> +
>>> +#ifndef _SOPHGO_CV18XX_RESET
>>> +#define _SOPHGO_CV18XX_RESET
>>> +
>>> +#define RST_DDR 2
>>> +#define RST_H264C 3
>>> +#define RST_JPEG 4
>>> +#define RST_H265C 5
>>> +#define RST_VIPSYS 6
>>> +#define RST_TDMA 7
>>> +#define RST_TPU 8
>>> +#define RST_TPUSYS 9
>>> +#define RST_USB 11
>>> +#define RST_ETH0 12
>>> +#define RST_ETH1 13
>>> +#define RST_NAND 14
>>> +#define RST_EMMC 15
>>> +#define RST_SD0 16
>>> +#define RST_SDMA 18
>>> +#define RST_I2S0 19
>>> +#define RST_I2S1 20
>>> +#define RST_I2S2 21
>>> +#define RST_I2S3 22
>>> +#define RST_UART0 23
>>> +#define RST_UART1 24
>>> +#define RST_UART2 25
>>> +#define RST_UART3 26
>>> +#define RST_I2C0 27
>>> +#define RST_I2C1 28
>>> +#define RST_I2C2 29
>>> +#define RST_I2C3 30
>>> +#define RST_I2C4 31
>>> +#define RST_PWM0 32
>>> +#define RST_PWM1 33
>>> +#define RST_PWM2 34
>>> +#define RST_PWM3 35
>>> +#define RST_SPI0 40
>>> +#define RST_SPI1 41
>>> +#define RST_SPI2 42
>>> +#define RST_SPI3 43
>>> +#define RST_GPIO0 44
>>> +#define RST_GPIO1 45
>>> +#define RST_GPIO2 46
>>> +#define RST_EFUSE 47
>>> +#define RST_WDT 48
>>> +#define RST_AHB_ROM 49
>>> +#define RST_SPIC 50
>>> +#define RST_TEMPSEN 51
>>> +#define RST_SARADC 52
>>> +#define RST_COMBO_PHY0 58
>>> +#define RST_SPI_NAND 61
>>> +#define RST_SE 62
>>> +#define RST_UART4 74
>>> +#define RST_GPIO3 75
>>> +#define RST_SYSTEM 76
>>> +#define RST_TIMER 77
>>> +#define RST_TIMER0 78
>>> +#define RST_TIMER1 79
>>> +#define RST_TIMER2 80
>>> +#define RST_TIMER3 81
>>> +#define RST_TIMER4 82
>>> +#define RST_TIMER5 83
>>> +#define RST_TIMER6 84
>>> +#define RST_TIMER7 85
>>> +#define RST_WGN0 86
>>> +#define RST_WGN1 87
>>> +#define RST_WGN2 88
>>> +#define RST_KEYSCAN 89
>>> +#define RST_AUDDAC 91
>>> +#define RST_AUDDAC_APB 92
>>> +#define RST_AUDADC 93
>>> +#define RST_VCSYS 95
>>> +#define RST_ETHPHY 96
>>> +#define RST_ETHPHY_APB 97
>>> +#define RST_AUDSRC 98
>>> +#define RST_VIP_CAM0 99
>>> +#define RST_WDT1 100
>>> +#define RST_WDT2 101
>>> +#define RST_AUTOCLEAR_CPUCORE0 128
>>> +#define RST_AUTOCLEAR_CPUCORE1 129
>>> +#define RST_AUTOCLEAR_CPUCORE2 130
>>> +#define RST_AUTOCLEAR_CPUCORE3 131
>>> +#define RST_AUTOCLEAR_CPUSYS0 132
>>> +#define RST_AUTOCLEAR_CPUSYS1 133
>>> +#define RST_AUTOCLEAR_CPUSYS2 134
>>> +#define RST_CPUCORE0 160
>>> +#define RST_CPUCORE1 161
>>> +#define RST_CPUCORE2 162
>>> +#define RST_CPUCORE3 163
>>> +#define RST_CPUSYS0 164
>>> +#define RST_CPUSYS1 165
>>> +#define RST_CPUSYS2 166
>>> +
>>> +#endif /* _SOPHGO_CV18XX_RESET */
>>> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>>> index c18822ec849f..9aa28ade73a4 100644
>>> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>>> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>>> @@ -7,6 +7,7 @@
>>> #include <dt-bindings/clock/sophgo,cv1800.h>
>>> #include <dt-bindings/gpio/gpio.h>
>>> #include <dt-bindings/interrupt-controller/irq.h>
>>> +#include "cv18xx-reset.h"
>>>
>>> / {
>>> #address-cells = <1>;
>>> @@ -61,6 +62,12 @@ clk: clock-controller@3002000 {
>>> #clock-cells = <1>;
>>> };
>>>
>>> + rst: reset-controller@3003000 {
>>> + compatible = "sophgo,cv1800b-reset";
>>> + reg = <0x3003000 0x1000>;
>>> + #reset-cells = <1>;
>>> + };
>>> +
>>> gpio0: gpio@3020000 {
>>> compatible = "snps,dw-apb-gpio";
>>> reg = <0x3020000 0x1000>;
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
2025-02-10 2:56 ` Chen Wang
@ 2025-02-10 4:55 ` Inochi Amaoto
0 siblings, 0 replies; 18+ messages in thread
From: Inochi Amaoto @ 2025-02-10 4:55 UTC (permalink / raw)
To: Chen Wang, Yixun Lan
Cc: Inochi Amaoto, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Thomas Bonnefille, Jisheng Zhang, devicetree,
linux-kernel, linux-riscv, Longbin Li
On Mon, Feb 10, 2025 at 10:56:30AM +0800, Chen Wang wrote:
>
> On 2025/2/10 9:20, Yixun Lan wrote:
> > Hi Chen:
> >
> > On 08:55 Mon 10 Feb , Chen Wang wrote:
> > > On 2025/2/9 20:29, Inochi Amaoto wrote:
> > > > Add reset generator node for all CV18XX series SoC.
> > > >
> > > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > > > ---
> > > > arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++++++
> > > Why it's not include/dt-bindings/reset/sophgo,cv18xx-reset.h?
> > >
> > then first need to answer if it's really a binding, there are some disucssions
> > I personally favor Inochi's way here
> >
> > https://lore.kernel.org/linux-devicetree/c7e243e3-3f61-4d63-8727-3837838bdfcc@linaro.org
> > https://lore.kernel.org/linux-devicetree/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
>
> Well, it's fine if you don't want to define it as binding just because the
> ids are not continuous. In fact, for simple-reset, I think there is no big
> problem to define it as bindings.
>
I add this as a dts header because it is a device abi, not a binding one.
> Actually, in the first link upon, I see Krzysztof also said "simple-reset is
> an exception."
>
> I recall we ever discussed this when Jisheng submitted the first version of
> reset driver for cv18xx. FYI. See https://lore.kernel.org/linux-riscv/42ad3f60-2755-4d3b-a766-8e4404f76a7c@linaro.org/.
>
Yeah, I have seen this. But due to the previous reason, I will hold this and
see whether there are any new discussions.
Regards,
Inochi
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
2025-02-09 12:29 ` [PATCH 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC Inochi Amaoto
2025-02-10 0:55 ` Chen Wang
@ 2025-05-23 5:20 ` Junhui Liu
2025-05-23 5:47 ` Inochi Amaoto
1 sibling, 1 reply; 18+ messages in thread
From: Junhui Liu @ 2025-05-23 5:20 UTC (permalink / raw)
To: Inochi Amaoto, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen Wang, Inochi Amaoto, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Thomas Bonnefille, Jisheng Zhang
Cc: devicetree, linux-kernel, linux-riscv, Yixun Lan, Longbin Li
Hi Inochi,
Thanks for your patch. While testing remoteproc with it, I noticed some
issues that need correction:
On 2025/2/9 20:29, Inochi Amaoto wrote:
> Add reset generator node for all CV18XX series SoC.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++++++
> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 7 ++
> 2 files changed, 105 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-reset.h b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
> new file mode 100644
> index 000000000000..3d9aa9ec7e90
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
> @@ -0,0 +1,98 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (C) 2025 Inochi Amaoto <inochiama@outlook.com>
> + */
> +
> +#ifndef _SOPHGO_CV18XX_RESET
> +#define _SOPHGO_CV18XX_RESET
> +
> +#define RST_DDR 2
> +#define RST_H264C 3
> +#define RST_JPEG 4
> +#define RST_H265C 5
> +#define RST_VIPSYS 6
> +#define RST_TDMA 7
> +#define RST_TPU 8
> +#define RST_TPUSYS 9
> +#define RST_USB 11
> +#define RST_ETH0 12
> +#define RST_ETH1 13
> +#define RST_NAND 14
> +#define RST_EMMC 15
> +#define RST_SD0 16
> +#define RST_SDMA 18
> +#define RST_I2S0 19
> +#define RST_I2S1 20
> +#define RST_I2S2 21
> +#define RST_I2S3 22
> +#define RST_UART0 23
> +#define RST_UART1 24
> +#define RST_UART2 25
> +#define RST_UART3 26
> +#define RST_I2C0 27
> +#define RST_I2C1 28
> +#define RST_I2C2 29
> +#define RST_I2C3 30
> +#define RST_I2C4 31
> +#define RST_PWM0 32
> +#define RST_PWM1 33
> +#define RST_PWM2 34
> +#define RST_PWM3 35
> +#define RST_SPI0 40
> +#define RST_SPI1 41
> +#define RST_SPI2 42
> +#define RST_SPI3 43
> +#define RST_GPIO0 44
> +#define RST_GPIO1 45
> +#define RST_GPIO2 46
> +#define RST_EFUSE 47
> +#define RST_WDT 48
> +#define RST_AHB_ROM 49
> +#define RST_SPIC 50
> +#define RST_TEMPSEN 51
> +#define RST_SARADC 52
> +#define RST_COMBO_PHY0 58
> +#define RST_SPI_NAND 61
> +#define RST_SE 62
> +#define RST_UART4 74
> +#define RST_GPIO3 75
> +#define RST_SYSTEM 76
> +#define RST_TIMER 77
> +#define RST_TIMER0 78
> +#define RST_TIMER1 79
> +#define RST_TIMER2 80
> +#define RST_TIMER3 81
> +#define RST_TIMER4 82
> +#define RST_TIMER5 83
> +#define RST_TIMER6 84
> +#define RST_TIMER7 85
> +#define RST_WGN0 86
> +#define RST_WGN1 87
> +#define RST_WGN2 88
> +#define RST_KEYSCAN 89
> +#define RST_AUDDAC 91
> +#define RST_AUDDAC_APB 92
> +#define RST_AUDADC 93
> +#define RST_VCSYS 95
> +#define RST_ETHPHY 96
> +#define RST_ETHPHY_APB 97
> +#define RST_AUDSRC 98
> +#define RST_VIP_CAM0 99
> +#define RST_WDT1 100
> +#define RST_WDT2 101
> +#define RST_AUTOCLEAR_CPUCORE0 128
I think here should start from 256.
> +#define RST_AUTOCLEAR_CPUCORE1 129
> +#define RST_AUTOCLEAR_CPUCORE2 130
> +#define RST_AUTOCLEAR_CPUCORE3 131
> +#define RST_AUTOCLEAR_CPUSYS0 132
> +#define RST_AUTOCLEAR_CPUSYS1 133
> +#define RST_AUTOCLEAR_CPUSYS2 134
> +#define RST_CPUCORE0 160
And here should start from 288.
> +#define RST_CPUCORE1 161
> +#define RST_CPUCORE2 162
> +#define RST_CPUCORE3 163
> +#define RST_CPUSYS0 164
> +#define RST_CPUSYS1 165
> +#define RST_CPUSYS2 166
> +
> +#endif /* _SOPHGO_CV18XX_RESET */
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index c18822ec849f..9aa28ade73a4 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/clock/sophgo,cv1800.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> +#include "cv18xx-reset.h"
>
> / {
> #address-cells = <1>;
> @@ -61,6 +62,12 @@ clk: clock-controller@3002000 {
> #clock-cells = <1>;
> };
>
> + rst: reset-controller@3003000 {
> + compatible = "sophgo,cv1800b-reset";
> + reg = <0x3003000 0x1000>;
> + #reset-cells = <1>;
> + };
> +
> gpio0: gpio@3020000 {
> compatible = "snps,dw-apb-gpio";
> reg = <0x3020000 0x1000>;
--
Best regards,
Junhui Liu
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
2025-05-23 5:20 ` Junhui Liu
@ 2025-05-23 5:47 ` Inochi Amaoto
0 siblings, 0 replies; 18+ messages in thread
From: Inochi Amaoto @ 2025-05-23 5:47 UTC (permalink / raw)
To: Junhui Liu, Inochi Amaoto, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chen Wang, Inochi Amaoto,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Thomas Bonnefille,
Jisheng Zhang
Cc: devicetree, linux-kernel, linux-riscv, Yixun Lan, Longbin Li
On Fri, May 23, 2025 at 01:20:00PM +0800, Junhui Liu wrote:
> Hi Inochi,
>
> Thanks for your patch. While testing remoteproc with it, I noticed some
> issues that need correction:
>
> On 2025/2/9 20:29, Inochi Amaoto wrote:
> > Add reset generator node for all CV18XX series SoC.
> >
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > ---
> > arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++++++
> > arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 7 ++
> > 2 files changed, 105 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h
> >
> > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-reset.h b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
> > new file mode 100644
> > index 000000000000..3d9aa9ec7e90
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
> > @@ -0,0 +1,98 @@
> > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> > +/*
> > + * Copyright (C) 2025 Inochi Amaoto <inochiama@outlook.com>
> > + */
> > +
> > +#ifndef _SOPHGO_CV18XX_RESET
> > +#define _SOPHGO_CV18XX_RESET
> > +
> > +#define RST_DDR 2
> > +#define RST_H264C 3
> > +#define RST_JPEG 4
> > +#define RST_H265C 5
> > +#define RST_VIPSYS 6
> > +#define RST_TDMA 7
> > +#define RST_TPU 8
> > +#define RST_TPUSYS 9
> > +#define RST_USB 11
> > +#define RST_ETH0 12
> > +#define RST_ETH1 13
> > +#define RST_NAND 14
> > +#define RST_EMMC 15
> > +#define RST_SD0 16
> > +#define RST_SDMA 18
> > +#define RST_I2S0 19
> > +#define RST_I2S1 20
> > +#define RST_I2S2 21
> > +#define RST_I2S3 22
> > +#define RST_UART0 23
> > +#define RST_UART1 24
> > +#define RST_UART2 25
> > +#define RST_UART3 26
> > +#define RST_I2C0 27
> > +#define RST_I2C1 28
> > +#define RST_I2C2 29
> > +#define RST_I2C3 30
> > +#define RST_I2C4 31
> > +#define RST_PWM0 32
> > +#define RST_PWM1 33
> > +#define RST_PWM2 34
> > +#define RST_PWM3 35
> > +#define RST_SPI0 40
> > +#define RST_SPI1 41
> > +#define RST_SPI2 42
> > +#define RST_SPI3 43
> > +#define RST_GPIO0 44
> > +#define RST_GPIO1 45
> > +#define RST_GPIO2 46
> > +#define RST_EFUSE 47
> > +#define RST_WDT 48
> > +#define RST_AHB_ROM 49
> > +#define RST_SPIC 50
> > +#define RST_TEMPSEN 51
> > +#define RST_SARADC 52
> > +#define RST_COMBO_PHY0 58
> > +#define RST_SPI_NAND 61
> > +#define RST_SE 62
> > +#define RST_UART4 74
> > +#define RST_GPIO3 75
> > +#define RST_SYSTEM 76
> > +#define RST_TIMER 77
> > +#define RST_TIMER0 78
> > +#define RST_TIMER1 79
> > +#define RST_TIMER2 80
> > +#define RST_TIMER3 81
> > +#define RST_TIMER4 82
> > +#define RST_TIMER5 83
> > +#define RST_TIMER6 84
> > +#define RST_TIMER7 85
> > +#define RST_WGN0 86
> > +#define RST_WGN1 87
> > +#define RST_WGN2 88
> > +#define RST_KEYSCAN 89
> > +#define RST_AUDDAC 91
> > +#define RST_AUDDAC_APB 92
> > +#define RST_AUDADC 93
> > +#define RST_VCSYS 95
> > +#define RST_ETHPHY 96
> > +#define RST_ETHPHY_APB 97
> > +#define RST_AUDSRC 98
> > +#define RST_VIP_CAM0 99
> > +#define RST_WDT1 100
> > +#define RST_WDT2 101
> > +#define RST_AUTOCLEAR_CPUCORE0 128
>
>
> I think here should start from 256.
>
> > +#define RST_AUTOCLEAR_CPUCORE1 129
> > +#define RST_AUTOCLEAR_CPUCORE2 130
> > +#define RST_AUTOCLEAR_CPUCORE3 131
> > +#define RST_AUTOCLEAR_CPUSYS0 132
> > +#define RST_AUTOCLEAR_CPUSYS1 133
> > +#define RST_AUTOCLEAR_CPUSYS2 134
> > +#define RST_CPUCORE0 160
>
> And here should start from 288.
>
> > +#define RST_CPUCORE1 161
> > +#define RST_CPUCORE2 162
> > +#define RST_CPUCORE3 163
> > +#define RST_CPUSYS0 164
> > +#define RST_CPUSYS1 165
> > +#define RST_CPUSYS2 166
> > +
You are right, I will update this patch in the next rc1.
Thanks for testing.
Regards,
Inochi
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/4] riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
2025-02-09 12:29 [PATCH 0/4] riscv: sophgo: cv18xx: Add reset generator support Inochi Amaoto
` (2 preceding siblings ...)
2025-02-09 12:29 ` [PATCH 3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC Inochi Amaoto
@ 2025-02-09 12:29 ` Inochi Amaoto
2025-02-10 1:07 ` Chen Wang
3 siblings, 1 reply; 18+ messages in thread
From: Inochi Amaoto @ 2025-02-09 12:29 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen Wang, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Thomas Bonnefille, Jisheng Zhang
Cc: Inochi Amaoto, devicetree, linux-kernel, linux-riscv, Yixun Lan,
Longbin Li
Add already known reset configuration for existed device.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 9aa28ade73a4..4fadcb8e4359 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -170,6 +170,7 @@ i2c0: i2c@4000000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
clock-names = "ref", "pclk";
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C0>;
status = "disabled";
};
@@ -181,6 +182,7 @@ i2c1: i2c@4010000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
clock-names = "ref", "pclk";
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C1>;
status = "disabled";
};
@@ -192,6 +194,7 @@ i2c2: i2c@4020000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
clock-names = "ref", "pclk";
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C2>;
status = "disabled";
};
@@ -203,6 +206,7 @@ i2c3: i2c@4030000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
clock-names = "ref", "pclk";
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C3>;
status = "disabled";
};
@@ -214,6 +218,7 @@ i2c4: i2c@4040000 {
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
clock-names = "ref", "pclk";
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_I2C4>;
status = "disabled";
};
@@ -225,6 +230,7 @@ uart0: serial@4140000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART0>;
status = "disabled";
};
@@ -236,6 +242,7 @@ uart1: serial@4150000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART1>;
status = "disabled";
};
@@ -247,6 +254,7 @@ uart2: serial@4160000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART2>;
status = "disabled";
};
@@ -258,6 +266,7 @@ uart3: serial@4170000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART3>;
status = "disabled";
};
@@ -269,6 +278,7 @@ spi0: spi@4180000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
clock-names = "ssi_clk", "pclk";
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI0>;
status = "disabled";
};
@@ -280,6 +290,7 @@ spi1: spi@4190000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
clock-names = "ssi_clk", "pclk";
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI1>;
status = "disabled";
};
@@ -291,6 +302,7 @@ spi2: spi@41a0000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
clock-names = "ssi_clk", "pclk";
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI2>;
status = "disabled";
};
@@ -302,6 +314,7 @@ spi3: spi@41b0000 {
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
clock-names = "ssi_clk", "pclk";
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rst RST_SPI3>;
status = "disabled";
};
@@ -313,6 +326,7 @@ uart4: serial@41c0000 {
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rst RST_UART4>;
status = "disabled";
};
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 4/4] riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
2025-02-09 12:29 ` [PATCH 4/4] riscv: dts: sophgo: add reset configuration " Inochi Amaoto
@ 2025-02-10 1:07 ` Chen Wang
2025-02-10 4:52 ` Inochi Amaoto
0 siblings, 1 reply; 18+ messages in thread
From: Chen Wang @ 2025-02-10 1:07 UTC (permalink / raw)
To: Inochi Amaoto, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Thomas Bonnefille, Jisheng Zhang
Cc: devicetree, linux-kernel, linux-riscv, Yixun Lan, Longbin Li
I found that the titles of the patches in this patchset are some using
cv18xx, some using cv1800b, and some using cv1800. Please unify them.
All in“cv18xx”?
On 2025/2/9 20:29, Inochi Amaoto wrote:
> Add already known reset configuration for existed device.
Please change this description to "Add known reset configurations for
existing devices."
Regards,
Chen
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index 9aa28ade73a4..4fadcb8e4359 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -170,6 +170,7 @@ i2c0: i2c@4000000 {
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
> clock-names = "ref", "pclk";
> interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&rst RST_I2C0>;
> status = "disabled";
> };
>
> @@ -181,6 +182,7 @@ i2c1: i2c@4010000 {
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
> clock-names = "ref", "pclk";
> interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&rst RST_I2C1>;
> status = "disabled";
> };
>
> @@ -192,6 +194,7 @@ i2c2: i2c@4020000 {
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
> clock-names = "ref", "pclk";
> interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&rst RST_I2C2>;
> status = "disabled";
> };
>
> @@ -203,6 +206,7 @@ i2c3: i2c@4030000 {
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
> clock-names = "ref", "pclk";
> interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&rst RST_I2C3>;
> status = "disabled";
> };
>
> @@ -214,6 +218,7 @@ i2c4: i2c@4040000 {
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
> clock-names = "ref", "pclk";
> interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&rst RST_I2C4>;
> status = "disabled";
> };
>
> @@ -225,6 +230,7 @@ uart0: serial@4140000 {
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> reg-io-width = <4>;
> + resets = <&rst RST_UART0>;
> status = "disabled";
> };
>
> @@ -236,6 +242,7 @@ uart1: serial@4150000 {
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> reg-io-width = <4>;
> + resets = <&rst RST_UART1>;
> status = "disabled";
> };
>
> @@ -247,6 +254,7 @@ uart2: serial@4160000 {
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> reg-io-width = <4>;
> + resets = <&rst RST_UART2>;
> status = "disabled";
> };
>
> @@ -258,6 +266,7 @@ uart3: serial@4170000 {
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> reg-io-width = <4>;
> + resets = <&rst RST_UART3>;
> status = "disabled";
> };
>
> @@ -269,6 +278,7 @@ spi0: spi@4180000 {
> clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
> clock-names = "ssi_clk", "pclk";
> interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&rst RST_SPI0>;
> status = "disabled";
> };
>
> @@ -280,6 +290,7 @@ spi1: spi@4190000 {
> clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
> clock-names = "ssi_clk", "pclk";
> interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&rst RST_SPI1>;
> status = "disabled";
> };
>
> @@ -291,6 +302,7 @@ spi2: spi@41a0000 {
> clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
> clock-names = "ssi_clk", "pclk";
> interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&rst RST_SPI2>;
> status = "disabled";
> };
>
> @@ -302,6 +314,7 @@ spi3: spi@41b0000 {
> clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
> clock-names = "ssi_clk", "pclk";
> interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&rst RST_SPI3>;
> status = "disabled";
> };
>
> @@ -313,6 +326,7 @@ uart4: serial@41c0000 {
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> reg-io-width = <4>;
> + resets = <&rst RST_UART4>;
> status = "disabled";
> };
>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 4/4] riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
2025-02-10 1:07 ` Chen Wang
@ 2025-02-10 4:52 ` Inochi Amaoto
0 siblings, 0 replies; 18+ messages in thread
From: Inochi Amaoto @ 2025-02-10 4:52 UTC (permalink / raw)
To: Chen Wang, Inochi Amaoto, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Thomas Bonnefille, Jisheng Zhang
Cc: devicetree, linux-kernel, linux-riscv, Yixun Lan, Longbin Li
On Mon, Feb 10, 2025 at 09:07:42AM +0800, Chen Wang wrote:
> I found that the titles of the patches in this patchset are some using
> cv18xx, some using cv1800b, and some using cv1800. Please unify them. All
> in“cv18xx”?
>
> On 2025/2/9 20:29, Inochi Amaoto wrote:
> > Add already known reset configuration for existed device.
>
> Please change this description to "Add known reset configurations for
> existing devices."
>
> Regards,
>
> Chen
>
Thanks, I will fix it.
Regards,
Inochi
^ permalink raw reply [flat|nested] 18+ messages in thread