[PATCH v3 00/12] media: imx8: add camera support

[PATCH v3 00/12] media: imx8: add camera support

[Frank Li]

Add SCU reset driver for i.MX8QM/i.MX8QXP.
Update binding doc.
Update driver for imx8qxp and imx8qm.
Add dts files for it.

To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Dong Aisheng <aisheng.dong@nxp.com>
To: Philipp Zabel <p.zabel@pengutronix.de>
To: Shawn Guo <shawnguo@kernel.org>
To: Sascha Hauer <s.hauer@pengutronix.de>
To: Pengutronix Kernel Team <kernel@pengutronix.de>
To: Fabio Estevam <festevam@gmail.com>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Mauro Carvalho Chehab <mchehab@kernel.org>
To: Rui Miguel Silva <rmfrfs@gmail.com>
To: Martin Kepplinger <martink@posteo.de>
To: Purism Kernel Team <kernel@puri.sm>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: imx@lists.linux.dev
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-media@vger.kernel.org
Cc: Robert Chiras <robert.chiras@nxp.com>
Cc: "Guoniu.zhou" <guoniu.zhou@nxp.com>

Signed-off-by: Frank Li <Frank.Li@nxp.com>

Changes in v3:
- Remove phy driver parts.
- csr is dedicate for mipi csi2, so add it as second register space. csr is
mixed with PHY and link control with csi2.
- Link to v2: https://lore.kernel.org/r/20250205-8qxp_camera-v2-0-731a3edf2744@nxp.com

Changes in v2:
- move scu reset binding doc to top scu doc.
- isi use seperate binding doc for imx8qxp and imx8qm.
- phy and csi2, compatible string 8qm fallback to qxp
- remove internal review tags
- Link to v1: https://lore.kernel.org/r/20250131-8qxp_camera-v1-0-319402ab606a@nxp.com

---
Frank Li (9):
      dt-bindings: firmware: imx: add property reset-controller
      reset: imx: Add SCU reset driver for i.MX8QXP and i.MX8QM
      media: dt-bindings: Add binding doc for i.MX8QXP and i.MX8QM ISI
      media: nxp: imx8-isi: Allow num_sources to be greater than num_sink
      media: imx8mq-mipi-csi2: Add support for i.MX8QXP
      arm64: dts: imx8: add capture controller for i.MX8's img subsystem
      arm64: dts: imx8qm: add 24MHz clock-xtal24m
      arm64: dts: imx8q: add linux,cma node for imx8qm-mek and imx8qxp-mek
      arm64: dts: imx8q: add camera ov5640 support for imx8qm-mek and imx8qxp-mek

Guoniu.zhou (1):
      media: imx8mq-mipi-csi2: Add imx8mq_plat_data for different compatible strings

Robert Chiras (2):
      media: imx8-isi: Add support for i.MX8QM and i.MX8QXP
      media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8QM(QXP) compatible strings

 .../devicetree/bindings/firmware/fsl,scu.yaml      |  12 +
 .../devicetree/bindings/media/fsl,imx8qm-isi.yaml  | 117 +++++++
 .../devicetree/bindings/media/fsl,imx8qxp-isi.yaml | 103 ++++++
 .../bindings/media/nxp,imx8mq-mipi-csi2.yaml       |  38 ++-
 MAINTAINERS                                        |   1 +
 arch/arm64/boot/dts/freescale/Makefile             |  12 +
 arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi     | 376 +++++++++++++++++++++
 .../boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso |  90 +++++
 .../boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso |  90 +++++
 arch/arm64/boot/dts/freescale/imx8qm-mek.dts       |  60 ++++
 arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi   |  45 +++
 arch/arm64/boot/dts/freescale/imx8qm.dtsi          |  12 +
 .../boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso |  89 +++++
 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts      |  44 +++
 arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi  |  60 ++++
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi         |   5 +
 .../media/platform/nxp/imx8-isi/imx8-isi-core.c    |  47 +++
 .../media/platform/nxp/imx8-isi/imx8-isi-core.h    |   2 +
 .../platform/nxp/imx8-isi/imx8-isi-crossbar.c      |   8 +-
 drivers/media/platform/nxp/imx8mq-mipi-csi2.c      | 179 +++++++++-
 drivers/reset/Kconfig                              |   7 +
 drivers/reset/Makefile                             |   1 +
 drivers/reset/reset-imx-scu.c                      | 101 ++++++
 23 files changed, 1477 insertions(+), 22 deletions(-)
---
base-commit: ce37eebeae8fa9e6c53f7f1ccd182ad5f27d66cd
change-id: 20250114-8qxp_camera-c1af5749d304

Best regards,
---
Frank Li <Frank.Li@nxp.com>

[PATCH v3 01/12] dt-bindings: firmware: imx: add property reset-controller

[Frank Li]

System Controller Firmware(SCU) reset some peripherals, such as CSI. So add
reset-controller for it.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change from v2 to v3
-none

change from v1 to v2
- new patch, move reset-controller in top fsl,scu.yaml
---
 Documentation/devicetree/bindings/firmware/fsl,scu.yaml | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
index 557e524786c22..f9ba18f063692 100644
--- a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
+++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
@@ -45,6 +45,18 @@ properties:
       Keys provided by the SCU
     $ref: /schemas/input/fsl,scu-key.yaml
 
+  reset-controller:
+    type: object
+    properties:
+      compatible:
+        const: fsl,imx-scu-reset
+      '#reset-cells':
+        const: 1
+    required:
+      - compatible
+      - '#reset-cells'
+    additionalProperties: false
+
   mboxes:
     description:
       A list of phandles of TX MU channels followed by a list of phandles of

-- 
2.34.1

[PATCH v3 02/12] reset: imx: Add SCU reset driver for i.MX8QXP and i.MX8QM

[Frank Li]

Add System Controller Firmware(SCU) reset driver for i.MX8QM and i.MX8QXP.
SCU Manage resets for peripherals such as MIPI CSI. Currently, support two
reset sources: IMX_SC_R_CSI_0 and IMX_SC_R_CSI_1.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change from v1 to v3
- none
---
 drivers/reset/Kconfig         |   7 +++
 drivers/reset/Makefile        |   1 +
 drivers/reset/reset-imx-scu.c | 101 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 109 insertions(+)

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 5b3abb6db2489..99f6f9784e686 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -96,6 +96,13 @@ config RESET_HSDK
 	help
 	  This enables the reset controller driver for HSDK board.
 
+config RESET_IMX_SCU
+	tristate "i.MX8Q Reset Driver"
+	depends on IMX_SCU && HAVE_ARM_SMCCC
+	depends on (ARM64 && ARCH_MXC) || COMPILE_TEST
+	help
+          This enables the reset controller driver for i.MX8QM/i.MX8QXP
+
 config RESET_IMX7
 	tristate "i.MX7/8 Reset Driver"
 	depends on HAS_IOMEM
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 677c4d1e26320..31f9904d13f9c 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
 obj-$(CONFIG_RESET_EYEQ) += reset-eyeq.o
 obj-$(CONFIG_RESET_GPIO) += reset-gpio.o
 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
+obj-$(CONFIG_RESET_IMX_SCU) += reset-imx-scu.o
 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
 obj-$(CONFIG_RESET_IMX8MP_AUDIOMIX) += reset-imx8mp-audiomix.o
 obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
diff --git a/drivers/reset/reset-imx-scu.c b/drivers/reset/reset-imx-scu.c
new file mode 100644
index 0000000000000..d3074eaad4c99
--- /dev/null
+++ b/drivers/reset/reset-imx-scu.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ * Frank Li <Frank.Li@nxp.com>
+ */
+#include <linux/firmware/imx/svc/misc.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+struct imx_scu_reset {
+	struct reset_controller_dev rc;
+	struct imx_sc_ipc *ipc_handle;
+};
+
+static struct imx_scu_reset *to_imx_scu(struct reset_controller_dev *rc)
+{
+	return container_of(rc, struct imx_scu_reset, rc);
+}
+
+struct imx_scu_id_map {
+	u32 resource_id;
+	u32 command_id;
+};
+
+static const struct imx_scu_id_map imx_scu_id_map[] = {
+	{ IMX_SC_R_CSI_0, IMX_SC_C_MIPI_RESET },
+	{ IMX_SC_R_CSI_1, IMX_SC_C_MIPI_RESET },
+};
+
+static int imx_scu_reset_assert(struct reset_controller_dev *rc, unsigned long id)
+{
+	struct imx_scu_reset *priv = to_imx_scu(rc);
+
+	return imx_sc_misc_set_control(priv->ipc_handle, imx_scu_id_map[id].resource_id,
+				       imx_scu_id_map[id].command_id, true);
+}
+
+static const struct reset_control_ops imx_scu_reset_ops = {
+	.assert = imx_scu_reset_assert,
+};
+
+static int imx_scu_xlate(struct reset_controller_dev *rc, const struct of_phandle_args *reset_spec)
+{
+	int i;
+
+	for (i = 0; i < rc->nr_resets; i++)
+		if (reset_spec->args[0] == imx_scu_id_map[i].resource_id)
+			return i;
+
+	return -EINVAL;
+}
+
+static int imx_scu_reset_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct imx_scu_reset *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, &priv->rc);
+
+	ret = imx_scu_get_handle(&priv->ipc_handle);
+	if (ret)
+		return dev_err_probe(dev, ret, "sc_misc_MIPI get ipc handle failed!\n");
+
+	priv->rc.ops = &imx_scu_reset_ops;
+	priv->rc.owner = THIS_MODULE;
+	priv->rc.of_node = dev->of_node;
+	priv->rc.of_reset_n_cells = 1;
+	priv->rc.of_xlate = imx_scu_xlate;
+	priv->rc.nr_resets = ARRAY_SIZE(imx_scu_id_map);
+
+	return devm_reset_controller_register(dev, &priv->rc);
+}
+
+static const struct of_device_id imx_scu_reset_ids[] = {
+	{ .compatible = "fsl,imx-scu-reset", },
+	{}
+};
+MODULE_DEVICE_TABLE(platform, imx_scu_reset_ids);
+
+static struct platform_driver imx_scu_reset_driver = {
+	.probe          = imx_scu_reset_probe,
+	.driver = {
+		.name = "scu-reset",
+		.of_match_table = imx_scu_reset_ids,
+	},
+};
+module_platform_driver(imx_scu_reset_driver);
+
+MODULE_AUTHOR("Frank Li <Frank.Li@nxp.com>");
+MODULE_DESCRIPTION("i.MX scu reset driver");
+MODULE_LICENSE("GPL");

-- 
2.34.1

[PATCH v3 03/12] media: dt-bindings: Add binding doc for i.MX8QXP and i.MX8QM ISI

[Frank Li]

Add binding documentation for i.MX8QXP and i.MX8QM ISI. The clock-names,
power-domains, and ports differ significantly from the existing
nxp,imx8-isi.yaml. Create a new file to avoid complex if-else branches.

Add new file to MAINTAINERS.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change from v2 to v3
- none
change from v1 to v2
- create new file for 8qm and 8qxp accroding rob's suggestion.
---
 .../devicetree/bindings/media/fsl,imx8qm-isi.yaml  | 117 +++++++++++++++++++++
 .../devicetree/bindings/media/fsl,imx8qxp-isi.yaml | 103 ++++++++++++++++++
 MAINTAINERS                                        |   1 +
 3 files changed, 221 insertions(+)

diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml
new file mode 100644
index 0000000000000..61c551673e2a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/fsl,imx8qm-isi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX8QM Image Sensing Interface
+
+maintainers:
+  - Frank Li <Frank.Li@nxp.com>
+
+description:
+  The Image Sensing Interface (ISI) combines image processing pipelines with
+  DMA engines to process and capture frames originating from a variety of
+  sources. The inputs to the ISI go through Pixel Link interfaces, and their
+  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
+  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8qm-isi
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 8
+
+  clock-names:
+    items:
+      - const: per0
+      - const: per1
+      - const: per2
+      - const: per3
+      - const: per4
+      - const: per5
+      - const: per6
+      - const: per7
+
+  interrupts:
+    maxItems: 8
+
+  power-domains:
+    maxItems: 8
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    properties:
+      port@2:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: MIPI CSI-2 RX 0
+      port@3:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: MIPI CSI-2 RX 1
+      port@4:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: HDMI RX
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/clock/imx8-clock.h>
+    #include <dt-bindings/clock/imx8-lpcg.h>
+    #include <dt-bindings/firmware/imx/rsrc.h>
+
+    image-controller@58100000 {
+        compatible = "fsl,imx8qm-isi";
+        reg = <0x58100000 0x90000>;
+        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
+                 <&pdma1_lpcg IMX_LPCG_CLK_0>,
+                 <&pdma2_lpcg IMX_LPCG_CLK_0>,
+                 <&pdma3_lpcg IMX_LPCG_CLK_0>,
+                 <&pdma4_lpcg IMX_LPCG_CLK_0>,
+                 <&pdma5_lpcg IMX_LPCG_CLK_0>,
+                 <&pdma6_lpcg IMX_LPCG_CLK_0>,
+                 <&pdma7_lpcg IMX_LPCG_CLK_0>;
+        clock-names = "per0", "per1", "per2", "per3",
+                      "per4", "per5", "per6", "per7";
+        power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>,
+                        <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>,
+                        <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>,
+                        <&pd IMX_SC_R_ISI_CH6>, <&pd IMX_SC_R_ISI_CH7>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@2 {
+                reg = <2>;
+                endpoint {
+                    remote-endpoint = <&mipi_csi0_out>;
+                };
+            };
+        };
+    };
+...
diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml
new file mode 100644
index 0000000000000..818fea0e4679f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/fsl,imx8qxp-isi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX8QXP Image Sensing Interface
+
+maintainers:
+  - Frank Li <Frank.Li@nxp.com>
+
+description:
+  The Image Sensing Interface (ISI) combines image processing pipelines with
+  DMA engines to process and capture frames originating from a variety of
+  sources. The inputs to the ISI go through Pixel Link interfaces, and their
+  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
+  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8qxp-isi
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 5
+
+  clock-names:
+    items:
+      - const: per0
+      - const: per4
+      - const: per5
+      - const: per6
+      - const: per7
+
+  interrupts:
+    maxItems: 5
+
+  power-domains:
+    maxItems: 5
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    properties:
+      port@2:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: MIPI CSI-2 RX 0
+      port@6:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: CSI-2 Parallel RX
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/clock/imx8-clock.h>
+    #include <dt-bindings/clock/imx8-lpcg.h>
+    #include <dt-bindings/firmware/imx/rsrc.h>
+
+    image-controller@58100000 {
+        compatible = "fsl,imx8qxp-isi";
+        reg = <0x58100000 0x90000>;
+        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
+                 <&pdma4_lpcg IMX_LPCG_CLK_0>,
+                 <&pdma5_lpcg IMX_LPCG_CLK_0>,
+                 <&pdma6_lpcg IMX_LPCG_CLK_0>,
+                 <&pdma7_lpcg IMX_LPCG_CLK_0>;
+        clock-names = "per0", "per4", "per5", "per6", "per7";
+        power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH4>,
+                        <&pd IMX_SC_R_ISI_CH5>, <&pd IMX_SC_R_ISI_CH6>,
+                        <&pd IMX_SC_R_ISI_CH7>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@2 {
+                reg = <2>;
+                endpoint {
+                    remote-endpoint = <&mipi_csi0_out>;
+                };
+            };
+        };
+    };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 40d1b7ec30fde..f243257ef7653 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17000,6 +17000,7 @@ NXP i.MX 8M ISI DRIVER
 M:	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
 L:	linux-media@vger.kernel.org
 S:	Maintained
+F:	Documentation/devicetree/bindings/media/fsl,imx8*-isi.yaml
 F:	Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml
 F:	drivers/media/platform/nxp/imx8-isi/
 

-- 
2.34.1

[PATCH v3 04/12] media: nxp: imx8-isi: Allow num_sources to be greater than num_sink

[Frank Li]

Allow num_sources (drvdata: num_channels) to be greater than num_sink
(drvdata: num_ports + 1).

ISI support stream multiplexing, such as differentiates multiple cameras
from a single 2-lane MIPI input, or duplicates input stream into multiple
outputs. So num_channels may be greater than num_ports at some platform.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change from v1 to v3
- none
---
 drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c b/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c
index 93a55c97cd173..ba5b2d3617a23 100644
--- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c
+++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c
@@ -188,11 +188,11 @@ static int mxc_isi_crossbar_init_state(struct v4l2_subdev *sd,
 	 * Create a 1:1 mapping between pixel link inputs and outputs to
 	 * pipelines by default.
 	 */
-	routes = kcalloc(xbar->num_sources, sizeof(*routes), GFP_KERNEL);
+	routes = kcalloc(xbar->num_sinks - 1, sizeof(*routes), GFP_KERNEL);
 	if (!routes)
 		return -ENOMEM;
 
-	for (i = 0; i < xbar->num_sources; ++i) {
+	for (i = 0; i < xbar->num_sinks - 1; ++i) {
 		struct v4l2_subdev_route *route = &routes[i];
 
 		route->sink_pad = i;
@@ -200,7 +200,7 @@ static int mxc_isi_crossbar_init_state(struct v4l2_subdev *sd,
 		route->flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE;
 	}
 
-	routing.num_routes = xbar->num_sources;
+	routing.num_routes = xbar->num_sinks - 1;
 	routing.routes = routes;
 
 	ret = __mxc_isi_crossbar_set_routing(sd, state, &routing);
@@ -453,7 +453,7 @@ int mxc_isi_crossbar_init(struct mxc_isi_dev *isi)
 	 * the memory input.
 	 */
 	xbar->num_sinks = isi->pdata->num_ports + 1;
-	xbar->num_sources = isi->pdata->num_ports;
+	xbar->num_sources = isi->pdata->num_channels;
 	num_pads = xbar->num_sinks + xbar->num_sources;
 
 	xbar->pads = kcalloc(num_pads, sizeof(*xbar->pads), GFP_KERNEL);

-- 
2.34.1

[PATCH v3 05/12] media: imx8-isi: Add support for i.MX8QM and i.MX8QXP

[Frank Li]

From: Robert Chiras <robert.chiras@nxp.com>

Add compatibles and platform data for i.MX8QM and i.MX8QXP platforms.
There are 8 ISI channels on i.MX8QM while there are only 5 channels on
i.MX8QXP.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change from v2 to v3
- none

change from v1 to v2
- remove intenal review tags
---
 .../media/platform/nxp/imx8-isi/imx8-isi-core.c    | 47 ++++++++++++++++++++++
 .../media/platform/nxp/imx8-isi/imx8-isi-core.h    |  2 +
 2 files changed, 49 insertions(+)

diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c
index 1e79b1211b603..a3237d76f7aa5 100644
--- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c
+++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c
@@ -274,6 +274,25 @@ static const struct mxc_isi_set_thd mxc_imx8_isi_thd_v1 = {
 	.panic_set_thd_v = { .mask = 0xf0000, .offset = 16, .threshold = 0x7 },
 };
 
+static const struct clk_bulk_data mxc_imx8qm_clks[] = {
+	{ .id = "per0" },
+	{ .id = "per1" },
+	{ .id = "per2" },
+	{ .id = "per3" },
+	{ .id = "per4" },
+	{ .id = "per5" },
+	{ .id = "per6" },
+	{ .id = "per7" },
+};
+
+static const struct clk_bulk_data mxc_imx8qxp_clks[] = {
+	{ .id = "per0" },
+	{ .id = "per4" },
+	{ .id = "per5" },
+	{ .id = "per6" },
+	{ .id = "per7" },
+};
+
 static const struct clk_bulk_data mxc_imx8mn_clks[] = {
 	{ .id = "axi" },
 	{ .id = "apb" },
@@ -334,6 +353,32 @@ static const struct mxc_isi_plat_data mxc_imx93_data = {
 	.has_36bit_dma		= false,
 };
 
+static const struct mxc_isi_plat_data mxc_imx8qm_data = {
+	.model			= MXC_ISI_IMX8QM,
+	.num_ports		= 5,
+	.num_channels		= 8,
+	.reg_offset		= 0x10000,
+	.ier_reg		= &mxc_imx8_isi_ier_v1,
+	.set_thd		= &mxc_imx8_isi_thd_v1,
+	.clks			= mxc_imx8qm_clks,
+	.num_clks		= ARRAY_SIZE(mxc_imx8qm_clks),
+	.buf_active_reverse	= true,
+	.has_36bit_dma		= false,
+};
+
+static const struct mxc_isi_plat_data mxc_imx8qxp_data = {
+	.model			= MXC_ISI_IMX8QXP,
+	.num_ports		= 5,
+	.num_channels		= 5,
+	.reg_offset		= 0x10000,
+	.ier_reg		= &mxc_imx8_isi_ier_v1,
+	.set_thd		= &mxc_imx8_isi_thd_v1,
+	.clks			= mxc_imx8qxp_clks,
+	.num_clks		= ARRAY_SIZE(mxc_imx8qxp_clks),
+	.buf_active_reverse	= true,
+	.has_36bit_dma		= false,
+};
+
 /* -----------------------------------------------------------------------------
  * Power management
  */
@@ -541,6 +586,8 @@ static void mxc_isi_remove(struct platform_device *pdev)
 static const struct of_device_id mxc_isi_of_match[] = {
 	{ .compatible = "fsl,imx8mn-isi", .data = &mxc_imx8mn_data },
 	{ .compatible = "fsl,imx8mp-isi", .data = &mxc_imx8mp_data },
+	{ .compatible = "fsl,imx8qm-isi", .data = &mxc_imx8qm_data },
+	{ .compatible = "fsl,imx8qxp-isi", .data = &mxc_imx8qxp_data },
 	{ .compatible = "fsl,imx8ulp-isi", .data = &mxc_imx8ulp_data },
 	{ .compatible = "fsl,imx93-isi", .data = &mxc_imx93_data },
 	{ /* sentinel */ },
diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h
index 9c7fe9e5f941f..496cad3f9423d 100644
--- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h
+++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h
@@ -158,6 +158,8 @@ struct mxc_gasket_ops {
 enum model {
 	MXC_ISI_IMX8MN,
 	MXC_ISI_IMX8MP,
+	MXC_ISI_IMX8QM,
+	MXC_ISI_IMX8QXP,
 	MXC_ISI_IMX8ULP,
 	MXC_ISI_IMX93,
 };

-- 
2.34.1

[PATCH v3 06/12] media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8QM(QXP) compatible strings

[Frank Li]

From: Robert Chiras <robert.chiras@nxp.com>

Add compatible strings for i.MX8QM/i.MX8QXP platform. Remove
fsl,mipi-phy-gpr from required properties and add new reg space, since
i.MX8QM and i.MX8QXP use dedicate control and status register(csr) space.

Keep the same restriction for other compatible strings.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change from v2 to v3
- use dedicate csr register space
change from v1 to v2
- remove internal review tags
- remove reg maxitems:1
- remove 8ulp part
- add 8qxp compatible string and make 8qm failback to 8qxp
- limit reset and power domain number to 1 for 8qxp and 8qm
- remove power-domains change because 8qm/8qxp only need 1 power domain
---
 .../bindings/media/nxp,imx8mq-mipi-csi2.yaml       | 38 +++++++++++++++++++---
 1 file changed, 34 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
index 2a14e3b0e0040..522449e50079e 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
@@ -16,11 +16,19 @@ description: |-
 
 properties:
   compatible:
-    enum:
-      - fsl,imx8mq-mipi-csi2
+    oneOf:
+      - enum:
+          - fsl,imx8mq-mipi-csi2
+          - fsl,imx8qxp-mipi-csi2
+      - items:
+          - const: fsl,imx8qm-mipi-csi2
+          - const: fsl,imx8qxp-mipi-csi2
 
   reg:
-    maxItems: 1
+    items:
+      - description: mipi csi2 rx host controller register.
+      - description: mipi csi2 control and status register (csr).
+    minItems: 1
 
   clocks:
     items:
@@ -46,6 +54,7 @@ properties:
       - description: CORE_RESET reset register bit definition
       - description: PHY_REF_RESET reset register bit definition
       - description: ESC_RESET reset register bit definition
+    minItems: 1
 
   fsl,mipi-phy-gpr:
     description: |
@@ -113,9 +122,30 @@ required:
   - clock-names
   - power-domains
   - resets
-  - fsl,mipi-phy-gpr
   - ports
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - fsl,imx8qxp-mipi-csi2
+    then:
+      properties:
+        reg:
+          minItems: 2
+        resets:
+          maxItems: 1
+    else:
+      properties:
+        reg:
+          maxItems: 1
+        resets:
+          minItems: 3
+      required:
+        - fsl,mipi-phy-gpr
+
 additionalProperties: false
 
 examples:

-- 
2.34.1

[PATCH v3 07/12] media: imx8mq-mipi-csi2: Add imx8mq_plat_data for different compatible strings

[Frank Li]

From: "Guoniu.zhou" <guoniu.zhou@nxp.com>

Introduce `imx8mq_plat_data` along with enable/disable callback operations
to facilitate support for new chips. No functional changes.

Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Change from v2 to v3
- none
change from v1 to v2
- remove internal review tags
---
 drivers/media/platform/nxp/imx8mq-mipi-csi2.c | 60 ++++++++++++++++++++-------
 1 file changed, 46 insertions(+), 14 deletions(-)

diff --git a/drivers/media/platform/nxp/imx8mq-mipi-csi2.c b/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
index 1f2657cf6e824..b5eae56d92f49 100644
--- a/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
+++ b/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
@@ -62,6 +62,8 @@
 #define CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL	0x188
 #define CSI2RX_CFG_DISABLE_PAYLOAD_1		0x130
 
+struct csi_state;
+
 enum {
 	ST_POWERED	= 1,
 	ST_STREAMING	= 2,
@@ -83,11 +85,11 @@ static const char * const imx8mq_mipi_csi_clk_id[CSI2_NUM_CLKS] = {
 
 #define CSI2_NUM_CLKS	ARRAY_SIZE(imx8mq_mipi_csi_clk_id)
 
-#define	GPR_CSI2_1_RX_ENABLE		BIT(13)
-#define	GPR_CSI2_1_VID_INTFC_ENB	BIT(12)
-#define	GPR_CSI2_1_HSEL			BIT(10)
-#define	GPR_CSI2_1_CONT_CLK_MODE	BIT(8)
-#define	GPR_CSI2_1_S_PRG_RXHS_SETTLE(x)	(((x) & 0x3f) << 2)
+struct imx8mq_plat_data {
+	const char *name;
+	int (*enable)(struct csi_state *state, u32 hs_settle);
+	void (*disable)(struct csi_state *state);
+};
 
 /*
  * The send level configures the number of entries that must accumulate in
@@ -106,6 +108,7 @@ static const char * const imx8mq_mipi_csi_clk_id[CSI2_NUM_CLKS] = {
 
 struct csi_state {
 	struct device *dev;
+	const struct imx8mq_plat_data *pdata;
 	void __iomem *regs;
 	struct clk_bulk_data clks[CSI2_NUM_CLKS];
 	struct reset_control *rst;
@@ -137,6 +140,35 @@ struct csi2_pix_format {
 	u8 width;
 };
 
+/* -----------------------------------------------------------------------------
+ * i.MX8MQ GPR
+ */
+
+#define	GPR_CSI2_1_RX_ENABLE		BIT(13)
+#define	GPR_CSI2_1_VID_INTFC_ENB	BIT(12)
+#define	GPR_CSI2_1_HSEL			BIT(10)
+#define	GPR_CSI2_1_CONT_CLK_MODE	BIT(8)
+#define	GPR_CSI2_1_S_PRG_RXHS_SETTLE(x)	(((x) & 0x3f) << 2)
+
+static int imx8mq_gpr_enable(struct csi_state *state, u32 hs_settle)
+{
+	regmap_update_bits(state->phy_gpr,
+			   state->phy_gpr_reg,
+			   0x3fff,
+			   GPR_CSI2_1_RX_ENABLE |
+			   GPR_CSI2_1_VID_INTFC_ENB |
+			   GPR_CSI2_1_HSEL |
+			   GPR_CSI2_1_CONT_CLK_MODE |
+			   GPR_CSI2_1_S_PRG_RXHS_SETTLE(hs_settle));
+
+	return 0;
+}
+
+static const struct imx8mq_plat_data imx8mq_data = {
+	.name = "i.MX8MQ",
+	.enable = imx8mq_gpr_enable,
+};
+
 static const struct csi2_pix_format imx8mq_mipi_csi_formats[] = {
 	/* RAW (Bayer and greyscale) formats. */
 	{
@@ -364,14 +396,9 @@ static int imx8mq_mipi_csi_start_stream(struct csi_state *state,
 	if (ret)
 		return ret;
 
-	regmap_update_bits(state->phy_gpr,
-			   state->phy_gpr_reg,
-			   0x3fff,
-			   GPR_CSI2_1_RX_ENABLE |
-			   GPR_CSI2_1_VID_INTFC_ENB |
-			   GPR_CSI2_1_HSEL |
-			   GPR_CSI2_1_CONT_CLK_MODE |
-			   GPR_CSI2_1_S_PRG_RXHS_SETTLE(hs_settle));
+	ret = state->pdata->enable(state, hs_settle);
+	if (ret)
+		return ret;
 
 	return 0;
 }
@@ -379,6 +406,9 @@ static int imx8mq_mipi_csi_start_stream(struct csi_state *state,
 static void imx8mq_mipi_csi_stop_stream(struct csi_state *state)
 {
 	imx8mq_mipi_csi_write(state, CSI2RX_CFG_DISABLE_DATA_LANES, 0xf);
+
+	if (state->pdata->disable)
+		state->pdata->disable(state);
 }
 
 /* -----------------------------------------------------------------------------
@@ -869,6 +899,8 @@ static int imx8mq_mipi_csi_probe(struct platform_device *pdev)
 
 	state->dev = dev;
 
+	state->pdata = of_device_get_match_data(dev);
+
 	ret = imx8mq_mipi_csi_parse_dt(state);
 	if (ret < 0) {
 		dev_err(dev, "Failed to parse device tree: %d\n", ret);
@@ -946,7 +978,7 @@ static void imx8mq_mipi_csi_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id imx8mq_mipi_csi_of_match[] = {
-	{ .compatible = "fsl,imx8mq-mipi-csi2", },
+	{ .compatible = "fsl,imx8mq-mipi-csi2", .data = &imx8mq_data },
 	{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, imx8mq_mipi_csi_of_match);

-- 
2.34.1

[PATCH v3 08/12] media: imx8mq-mipi-csi2: Add support for i.MX8QXP

[Frank Li]

Add support for i.MX8QXP, which has a dedicated control and status register
(csr) space. Enable obtaining the second register space and initializing
PHY and link settings accordingly.

Add reset delay for i.MX8QXP. It needs a delay after toggle reset.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change from v2 to v3
- use dedicate csr reg to control phy and link settings.

Change from v1 to v2
- change 8QM go 8QXP, 8QM will failback to 8QXP to keep consisense with
phy drivers
---
 drivers/media/platform/nxp/imx8mq-mipi-csi2.c | 119 ++++++++++++++++++++++++++
 1 file changed, 119 insertions(+)

diff --git a/drivers/media/platform/nxp/imx8mq-mipi-csi2.c b/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
index b5eae56d92f49..788dabe5a0870 100644
--- a/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
+++ b/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
@@ -89,6 +89,8 @@ struct imx8mq_plat_data {
 	const char *name;
 	int (*enable)(struct csi_state *state, u32 hs_settle);
 	void (*disable)(struct csi_state *state);
+	bool use_reg_csr: 1;
+	int reset_delay;
 };
 
 /*
@@ -169,6 +171,101 @@ static const struct imx8mq_plat_data imx8mq_data = {
 	.enable = imx8mq_gpr_enable,
 };
 
+/* -----------------------------------------------------------------------------
+ * i.MX8QXP
+ */
+
+#define CSI2SS_PL_CLK_INTERVAL_US		10000
+#define CSI2SS_PL_CLK_TIMEOUT_US		100000
+
+#define CSI2SS_PLM_CTRL				0x0
+#define CSI2SS_PLM_CTRL_PL_CLK_RUN		BIT(31)
+#define CSI2SS_PLM_CTRL_VSYNC_OVERRIDE		BIT(9)
+#define CSI2SS_PLM_CTRL_HSYNC_OVERRIDE		BIT(10)
+#define CSI2SS_PLM_CTRL_VALID_OVERRIDE		BIT(11)
+#define CSI2SS_PLM_CTRL_POLARITY_MASK		BIT(12)
+#define CSI2SS_PLM_CTRL_ENABLE_PL		BIT(0)
+
+#define CSI2SS_PHY_CTRL				0x4
+#define CSI2SS_PHY_CTRL_PD			BIT(22)
+#define CSI2SS_PHY_CTRL_RTERM_SEL		BIT(21)
+#define CSI2SS_PLM_CTRL_POLARITY		BIT(12)
+#define CSI2SS_PHY_CTRL_RX_HS_SETTLE_MASK	GENMASK(9, 4)
+#define CSI2SS_PHY_CTRL_CONT_CLK_MODE		BIT(3)
+#define CSI2SS_PHY_CTRL_DDRCLK_EN		BIT(2)
+#define CSI2SS_PHY_CTRL_AUTO_PD_EN		BIT(1)
+#define CSI2SS_PHY_CTRL_RX_ENABLE		BIT(0)
+
+#define CSI2SS_DATA_TYPE			0x38
+#define CSI2SS_DATA_TYPE_MASK			GENMASK(23, 0)
+
+#define CSI2SS_CTRL_CLK_RESET			0x44
+#define CSI2SS_CTRL_CLK_RESET_EN		BIT(0)
+
+static int imx8qxp_gpr_enable(struct csi_state *state, u32 hs_settle)
+{
+	int ret;
+	u32 val;
+
+	/* clear format */
+	regmap_clear_bits(state->phy_gpr, CSI2SS_DATA_TYPE, CSI2SS_DATA_TYPE_MASK);
+
+	/* clear polarity */
+	regmap_clear_bits(state->phy_gpr, CSI2SS_PLM_CTRL,
+			  CSI2SS_PLM_CTRL_VSYNC_OVERRIDE |
+			  CSI2SS_PLM_CTRL_HSYNC_OVERRIDE |
+			  CSI2SS_PLM_CTRL_VALID_OVERRIDE |
+			  CSI2SS_PLM_CTRL_POLARITY_MASK);
+
+	regmap_update_bits(state->phy_gpr, CSI2SS_PHY_CTRL, CSI2SS_PHY_CTRL_RX_HS_SETTLE_MASK,
+			   FIELD_PREP(CSI2SS_PHY_CTRL_RX_HS_SETTLE_MASK, hs_settle));
+
+	regmap_set_bits(state->phy_gpr, CSI2SS_PHY_CTRL,
+			CSI2SS_PHY_CTRL_RX_ENABLE | CSI2SS_PHY_CTRL_DDRCLK_EN |
+			CSI2SS_PHY_CTRL_CONT_CLK_MODE | CSI2SS_PHY_CTRL_PD |
+			CSI2SS_PHY_CTRL_RTERM_SEL | CSI2SS_PHY_CTRL_AUTO_PD_EN);
+
+	ret = regmap_read_poll_timeout(state->phy_gpr, CSI2SS_PLM_CTRL,
+				       val, !(val & CSI2SS_PLM_CTRL_PL_CLK_RUN),
+				       CSI2SS_PL_CLK_INTERVAL_US,
+				       CSI2SS_PL_CLK_TIMEOUT_US);
+
+	if (ret) {
+		dev_err(state->dev, "Timeout waiting for Pixel-Link clock");
+		return ret;
+	}
+
+	/* Enable Pixel link Master*/
+	regmap_set_bits(state->phy_gpr, CSI2SS_PLM_CTRL,
+			CSI2SS_PLM_CTRL_ENABLE_PL | CSI2SS_PLM_CTRL_VALID_OVERRIDE);
+
+	/* PHY Enable */
+	regmap_clear_bits(state->phy_gpr, CSI2SS_PHY_CTRL,
+			  CSI2SS_PHY_CTRL_PD | CSI2SS_PLM_CTRL_POLARITY);
+
+	/* Release Reset */
+	regmap_set_bits(state->phy_gpr, CSI2SS_CTRL_CLK_RESET, CSI2SS_CTRL_CLK_RESET_EN);
+
+	return ret;
+}
+
+static void imx8qxp_gpr_disable(struct csi_state *state)
+{
+	/* Disable Pixel Link */
+	regmap_write(state->phy_gpr, CSI2SS_PLM_CTRL, 0x0);
+
+	/* Disable  PHY */
+	regmap_write(state->phy_gpr, CSI2SS_PHY_CTRL, 0x0);
+};
+
+static const struct imx8mq_plat_data imx8qxp_data = {
+	.name = "i.MX8QXP",
+	.enable = imx8qxp_gpr_enable,
+	.disable = imx8qxp_gpr_disable,
+	.use_reg_csr = 1,
+	.reset_delay = 10000,
+};
+
 static const struct csi2_pix_format imx8mq_mipi_csi_formats[] = {
 	/* RAW (Bayer and greyscale) formats. */
 	{
@@ -273,6 +370,8 @@ static int imx8mq_mipi_csi_sw_reset(struct csi_state *state)
 		return ret;
 	}
 
+	fsleep(state->pdata->reset_delay);
+
 	return 0;
 }
 
@@ -860,6 +959,25 @@ static int imx8mq_mipi_csi_parse_dt(struct csi_state *state)
 		return PTR_ERR(state->rst);
 	}
 
+	if (state->pdata->use_reg_csr) {
+		const struct regmap_config regmap_config = {
+			.reg_bits = 32,
+			.val_bits = 32,
+			.reg_stride = 4,
+		};
+		void __iomem *base;
+
+		base = devm_platform_ioremap_resource(to_platform_device(dev), 1);
+		if (IS_ERR(base))
+			return dev_err_probe(dev, IS_ERR(base), "missed csr register\n");
+
+		state->phy_gpr = devm_regmap_init_mmio(dev, base, &regmap_config);
+		if (IS_ERR(state->phy_gpr))
+			return dev_err_probe(dev, PTR_ERR(state->phy_gpr),
+					     "Fail to init mmio regmap\n");
+		return 0;
+	}
+
 	ret = of_property_read_u32_array(np, "fsl,mipi-phy-gpr", out_val,
 					 ARRAY_SIZE(out_val));
 	if (ret) {
@@ -979,6 +1097,7 @@ static void imx8mq_mipi_csi_remove(struct platform_device *pdev)
 
 static const struct of_device_id imx8mq_mipi_csi_of_match[] = {
 	{ .compatible = "fsl,imx8mq-mipi-csi2", .data = &imx8mq_data },
+	{ .compatible = "fsl,imx8qxp-mipi-csi2", .data = &imx8qxp_data },
 	{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, imx8mq_mipi_csi_of_match);

-- 
2.34.1

[PATCH v3 09/12] arm64: dts: imx8: add capture controller for i.MX8's img subsystem

[Frank Li]

Add CSI related nodes (i2c, irqsteer, csi, lpcg) for i.MX8 img subsystem.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Change from v2 to v3
- remove phy and put csr register space under mipi csi2

change from v1 to v2
- move scu reset under scu node
- add 8qm comaptible string for mipi csi2 and mipi csi phys.
---
 arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi    | 376 ++++++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi  |  45 +++
 arch/arm64/boot/dts/freescale/imx8qm.dtsi         |   5 +
 arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi |  60 ++++
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi        |   5 +
 5 files changed, 491 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
index d39242c1b9f79..eb41a6fcaf5b8 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
@@ -3,6 +3,14 @@
  * Copyright 2019-2021 NXP
  * Zhou Guoniu <guoniu.zhou@nxp.com>
  */
+
+img_axi_clk: clock-img-axi {
+	compatible = "fixed-clock";
+	#clock-cells = <0>;
+	clock-frequency = <400000000>;
+	clock-output-names = "img_axi_clk";
+};
+
 img_ipg_clk: clock-img-ipg {
 	compatible = "fixed-clock";
 	#clock-cells = <0>;
@@ -10,12 +18,270 @@ img_ipg_clk: clock-img-ipg {
 	clock-output-names = "img_ipg_clk";
 };
 
+img_pxl_clk: clock-img-pxl {
+	compatible = "fixed-clock";
+	#clock-cells = <0>;
+	clock-frequency = <600000000>;
+	clock-output-names = "img_pxl_clk";
+};
+
 img_subsys: bus@58000000 {
 	compatible = "simple-bus";
 	#address-cells = <1>;
 	#size-cells = <1>;
 	ranges = <0x58000000 0x0 0x58000000 0x1000000>;
 
+	isi: isi@58100000 {
+		reg = <0x58100000 0x90000>;
+		interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
+			 <&pdma1_lpcg IMX_LPCG_CLK_0>,
+			 <&pdma2_lpcg IMX_LPCG_CLK_0>,
+			 <&pdma3_lpcg IMX_LPCG_CLK_0>,
+			 <&pdma4_lpcg IMX_LPCG_CLK_0>,
+			 <&pdma5_lpcg IMX_LPCG_CLK_0>,
+			 <&pdma6_lpcg IMX_LPCG_CLK_0>,
+			 <&pdma7_lpcg IMX_LPCG_CLK_0>;
+		clock-names = "per0",
+			      "per1",
+			      "per2",
+			      "per3",
+			      "per4",
+			      "per5",
+			      "per6",
+			      "per7";
+		interrupt-parent = <&gic>;
+		power-domains = <&pd IMX_SC_R_ISI_CH0>,
+				<&pd IMX_SC_R_ISI_CH1>,
+				<&pd IMX_SC_R_ISI_CH2>,
+				<&pd IMX_SC_R_ISI_CH3>,
+				<&pd IMX_SC_R_ISI_CH4>,
+				<&pd IMX_SC_R_ISI_CH5>,
+				<&pd IMX_SC_R_ISI_CH6>,
+				<&pd IMX_SC_R_ISI_CH7>;
+		status = "disabled";
+	};
+
+	irqsteer_csi0: irqsteer@58220000 {
+		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
+		reg = <0x58220000 0x1000>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&img_ipg_clk>;
+		clock-names = "ipg";
+		interrupt-parent = <&gic>;
+		power-domains = <&pd IMX_SC_R_CSI_0>;
+		fsl,channel = <0>;
+		fsl,num-irqs = <32>;
+		status = "disabled";
+	};
+
+	gpio0_mipi_csi0: gpio@58222000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x58222000 0x1000>;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupts = <0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		interrupt-parent = <&irqsteer_csi0>;
+		power-domains = <&pd IMX_SC_R_CSI_0>;
+	};
+
+	csi0_core_lpcg: clock-controller@58223018 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58223018 0x4>;
+		clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_4>;
+		clock-output-names = "csi0_lpcg_core_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH0>;
+	};
+
+	csi0_esc_lpcg: clock-controller@5822301c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5822301c 0x4>;
+		clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_4>;
+		clock-output-names = "csi0_lpcg_esc_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH0>;
+	};
+
+	i2c_mipi_csi0: i2c@58226000 {
+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x58226000 0x1000>;
+		interrupts = <8>;
+		clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>,
+			 <&img_ipg_clk>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		interrupt-parent = <&irqsteer_csi0>;
+		power-domains = <&pd IMX_SC_R_CSI_0_I2C_0>;
+		status = "disabled";
+	};
+
+	mipi_csi_0: csi@58227000 {
+		compatible = "fsl,imx8qxp-mipi-csi2";
+		reg = <0x58227000 0x1000>,
+		      <0x58221000 0x1000>;
+		clocks = <&csi0_core_lpcg IMX_LPCG_CLK_4>,
+			 <&csi0_esc_lpcg IMX_LPCG_CLK_4>,
+			 <&csi0_pxl_lpcg IMX_LPCG_CLK_0>;
+		clock-names = "core", "esc", "ui";
+		assigned-clocks = <&csi0_core_lpcg IMX_LPCG_CLK_4>,
+				  <&csi0_esc_lpcg IMX_LPCG_CLK_4>;
+		assigned-clock-rates = <360000000>, <72000000>;
+		power-domains = <&pd IMX_SC_R_ISI_CH0>;
+		resets = <&scu_reset IMX_SC_R_CSI_0>;
+		status = "disabled";
+	};
+
+	irqsteer_csi1: irqsteer@58240000 {
+		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
+		reg = <0x58240000 0x1000>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&img_ipg_clk>;
+		clock-names = "ipg";
+		interrupt-parent = <&gic>;
+		power-domains = <&pd IMX_SC_R_CSI_1>;
+		fsl,channel = <0>;
+		fsl,num-irqs = <32>;
+		status = "disabled";
+	};
+
+	gpio0_mipi_csi1: gpio@58242000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x58242000 0x1000>;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupts = <0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		interrupt-parent = <&irqsteer_csi1>;
+		power-domains = <&pd IMX_SC_R_CSI_1>;
+	};
+
+	csi1_core_lpcg: clock-controller@58243018 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58243018 0x4>;
+		clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_4>;
+		clock-output-names = "csi1_lpcg_core_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH0>;
+	};
+
+	csi1_esc_lpcg: clock-controller@5824301c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5824301c 0x4>;
+		clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_4>;
+		clock-output-names = "csi1_lpcg_esc_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH0>;
+	};
+
+	i2c_mipi_csi1: i2c@58246000 {
+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x58246000 0x1000>;
+		interrupts = <8>;
+		clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>,
+			 <&img_ipg_clk>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		interrupt-parent = <&irqsteer_csi1>;
+		power-domains = <&pd IMX_SC_R_CSI_1_I2C_0>;
+		status = "disabled";
+	};
+
+	mipi_csi_1: csi@58247000 {
+		compatible = "fsl,imx8qxp-mipi-csi2";
+		reg = <0x58247000 0x1000>,
+		      <0x58241000 0x1000>;
+		clocks = <&csi1_core_lpcg IMX_LPCG_CLK_4>,
+			 <&csi1_esc_lpcg IMX_LPCG_CLK_4>,
+			 <&csi1_pxl_lpcg IMX_LPCG_CLK_0>;
+		clock-names = "core", "esc", "ui";
+		assigned-clocks = <&csi1_core_lpcg IMX_LPCG_CLK_4>,
+				  <&csi1_esc_lpcg IMX_LPCG_CLK_4>;
+		assigned-clock-rates = <360000000>, <72000000>;
+		power-domains = <&pd IMX_SC_R_ISI_CH0>;
+		resets = <&scu_reset IMX_SC_R_CSI_1>;
+		status = "disabled";
+	};
+
+	irqsteer_parallel: irqsteer@58260000 {
+		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
+		reg = <0x58260000 0x1000>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk_dummy>;
+		clock-names = "ipg";
+		interrupt-parent = <&gic>;
+		power-domains = <&pd IMX_SC_R_PI_0>;
+		fsl,channel = <0>;
+		fsl,num-irqs = <32>;
+		status = "disabled";
+	};
+
+	pi0_ipg_lpcg: clock-controller@58263004 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58263004 0x4>;
+		clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_4>;
+		clock-output-names = "pi0_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH0>;
+	};
+
+	pi0_pxl_lpcg: clock-controller@58263018 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58263018 0x4>;
+		clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "pi0_lpcg_pxl_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH0>;
+	};
+
+	pi0_misc_lpcg: clock-controller@5826301c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5826301c 0x4>;
+		clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "pi0_lpcg_misc_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH0>;
+	};
+
+	i2c0_parallel: i2c@58266000 {
+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x58266000 0x1000>;
+		interrupts = <8>;
+		clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>,
+			 <&img_ipg_clk>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		interrupt-parent = <&irqsteer_parallel>;
+		power-domains = <&pd IMX_SC_R_PI_0_I2C_0>;
+		status = "disabled";
+	};
+
 	jpegdec: jpegdec@58400000 {
 		reg = <0x58400000 0x00050000>;
 		interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
@@ -40,6 +306,116 @@ jpegenc: jpegenc@58450000 {
 				<&pd IMX_SC_R_MJPEG_ENC_S0>;
 	};
 
+	pdma0_lpcg: clock-controller@58500000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58500000 0x10000>;
+		clocks = <&img_pxl_clk>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "pdma0_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH0>;
+	};
+
+	pdma1_lpcg: clock-controller@58510000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58510000 0x10000>;
+		clocks = <&img_pxl_clk>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "pdma1_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH1>;
+	};
+
+	pdma2_lpcg: clock-controller@58520000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58520000 0x10000>;
+		clocks = <&img_pxl_clk>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "pdma2_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH2>;
+	};
+
+	pdma3_lpcg: clock-controller@58530000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58530000 0x10000>;
+		clocks = <&img_pxl_clk>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "pdma3_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH3>;
+	};
+
+	pdma4_lpcg: clock-controller@58540000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58540000 0x10000>;
+		clocks = <&img_pxl_clk>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "pdma4_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH4>;
+	};
+
+	pdma5_lpcg: clock-controller@58550000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58550000 0x10000>;
+		clocks = <&img_pxl_clk>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "pdma5_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH5>;
+	};
+
+	pdma6_lpcg: clock-controller@58560000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58560000 0x10000>;
+		clocks = <&img_pxl_clk>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "pdma6_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH6>;
+	};
+
+	pdma7_lpcg: clock-controller@58570000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58570000 0x10000>;
+		clocks = <&img_pxl_clk>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "pdma7_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_ISI_CH7>;
+	};
+
+	csi0_pxl_lpcg: clock-controller@58580000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58580000 0x10000>;
+		clocks = <&img_pxl_clk>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "csi0_lpcg_pxl_clk";
+		power-domains = <&pd IMX_SC_R_CSI_0>;
+	};
+
+	csi1_pxl_lpcg: clock-controller@58590000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x58590000 0x10000>;
+		clocks = <&img_pxl_clk>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "csi1_lpcg_pxl_clk";
+		power-domains = <&pd IMX_SC_R_CSI_1>;
+	};
+
+	hdmi_rx_pxl_link_lpcg: clock-controller@585a0000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x585a0000 0x10000>;
+		clocks = <&img_pxl_clk>;
+		#clock-cells = <1>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "hdmi_rx_lpcg_pxl_link_clk";
+		power-domains = <&pd IMX_SC_R_HDMI_RX>;
+	};
+
 	img_jpeg_dec_lpcg: clock-controller@585d0000 {
 		compatible = "fsl,imx8qxp-lpcg";
 		reg = <0x585d0000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
index 2bbdacb1313f9..efca0baec4b47 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
@@ -3,6 +3,31 @@
  * Copyright 2021 NXP
  */
 
+&isi {
+	compatible = "fsl,imx8qm-isi";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+		};
+
+		port@1 {
+			reg = <1>;
+		};
+
+		port@2 {
+			reg = <2>;
+		};
+
+		port@3 {
+			reg = <3>;
+		};
+	};
+};
+
 &jpegdec {
 	compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgdec";
 };
@@ -10,3 +35,23 @@ &jpegdec {
 &jpegenc {
 	compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
 };
+
+&mipi_csi_0 {
+	compatible = "fsl,imx8qm-mipi-csi2", "fsl,imx8qxp-mipi-csi2";
+};
+
+&mipi_csi_1 {
+	compatible = "fsl,imx8qm-mipi-csi2", "fsl,imx8qxp-mipi-csi2";
+};
+
+&pi0_ipg_lpcg {
+	status = "disabled";
+};
+
+&pi0_misc_lpcg {
+	status = "disabled";
+};
+
+&pi0_pxl_lpcg {
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 6fa31bc9ece8f..c6a17a0d739c5 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -333,6 +333,11 @@ iomuxc: pinctrl {
 			compatible = "fsl,imx8qm-iomuxc";
 		};
 
+		scu_reset: reset-controller {
+			compatible = "fsl,imx-scu-reset";
+			#reset-cells = <1>;
+		};
+
 		rtc: rtc {
 			compatible = "fsl,imx8qxp-sc-rtc";
 		};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
index 3a087317591d8..4c15e4569a51a 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
@@ -4,6 +4,62 @@
  *	Dong Aisheng <aisheng.dong@nxp.com>
  */
 
+&csi1_pxl_lpcg {
+	status = "disabled";
+};
+
+&csi1_core_lpcg {
+	status = "disabled";
+};
+
+&csi1_esc_lpcg {
+	status = "disabled";
+};
+
+&gpio0_mipi_csi1 {
+	status = "disabled";
+};
+
+&i2c_mipi_csi1 {
+	status = "disabled";
+};
+
+&irqsteer_csi1 {
+	status = "disabled";
+};
+
+&isi {
+	compatible = "fsl,imx8qxp-isi";
+	interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>, <&pdma4_lpcg IMX_LPCG_CLK_0>,
+		 <&pdma5_lpcg IMX_LPCG_CLK_0>, <&pdma6_lpcg IMX_LPCG_CLK_0>,
+		 <&pdma7_lpcg IMX_LPCG_CLK_0>;
+	clock-names = "per0", "per4", "per5", "per6", "per7";
+	power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>,
+			<&pd IMX_SC_R_ISI_CH6>, <&pd IMX_SC_R_ISI_CH7>;
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+		};
+
+		port@1 {
+			reg = <1>;
+		};
+
+		port@2 {
+			reg = <2>;
+		};
+	};
+};
+
 &jpegdec {
 	compatible = "nxp,imx8qxp-jpgdec";
 };
@@ -11,3 +67,7 @@ &jpegdec {
 &jpegenc {
 	compatible = "nxp,imx8qxp-jpgenc";
 };
+
+&mipi_csi_1 {
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 05138326f0a57..c078d92f76c0e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -241,6 +241,11 @@ scu_key: keys {
 			status = "disabled";
 		};
 
+		scu_reset: reset-controller {
+			compatible = "fsl,imx-scu-reset";
+			#reset-cells = <1>;
+		};
+
 		rtc: rtc {
 			compatible = "fsl,imx8qxp-sc-rtc";
 		};

-- 
2.34.1

[PATCH v3 10/12] arm64: dts: imx8qm: add 24MHz clock-xtal24m

[Frank Li]

Add fixed clock node clock-xtal24m to prepare to add camera support.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change from v1 to v3
- none
---
 arch/arm64/boot/dts/freescale/imx8qm.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index c6a17a0d739c5..40cd45cd9f88f 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -590,6 +590,13 @@ mipi_pll_div2_clk: clock-controller-mipi-div2-pll {
 		clock-output-names = "mipi_pll_div2_clk";
 	};
 
+	xtal24m: clock-xtal24m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "xtal_24MHz";
+	};
+
 	vpu_subsys_dsp: bus@55000000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;

-- 
2.34.1

[PATCH v3 11/12] arm64: dts: imx8q: add linux,cma node for imx8qm-mek and imx8qxp-mek

[Frank Li]

Add linux,cma node because some devices, such as camera, need big continue
physical memory.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change from v1 to v3
- none
---
 arch/arm64/boot/dts/freescale/imx8qm-mek.dts  | 9 +++++++++
 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 8 ++++++++
 2 files changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 50fd3370f7dce..61ef00f4259e1 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -113,6 +113,15 @@ dsp_vdev0buffer: memory@94300000 {
 			reg = <0 0x94300000 0 0x100000>;
 			no-map;
 		};
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0 0xc0000000 0 0x3c000000>;
+			size = <0 0x3c000000>;
+			linux,cma-default;
+			reusable;
+		};
 	};
 
 	lvds_backlight0: backlight-lvds0 {
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index be79c793213a5..89c6516c5ba90 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -56,6 +56,14 @@ dsp_vdev0buffer: memory@94300000 {
 			reg = <0 0x94300000 0 0x100000>;
 			no-map;
 		};
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0 0xc0000000 0 0x3c000000>;
+			size = <0 0x3c000000>;
+			linux,cma-default;
+			reusable;
+		};
 	};
 
 	reg_usdhc2_vmmc: usdhc2-vmmc {

-- 
2.34.1

[PATCH v3 12/12] arm64: dts: imx8q: add camera ov5640 support for imx8qm-mek and imx8qxp-mek

[Frank Li]

Add ov5640 overlay file for imx8qm-mek and imx8qxp-mek board. Camera can
connect different CSI port. So use dts overlay file to handle these
difference connect options.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change from v2 to v3
- remove phy nodes

change from v1 to v2
- none
---
 arch/arm64/boot/dts/freescale/Makefile             | 12 +++
 .../boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso | 90 ++++++++++++++++++++++
 .../boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso | 90 ++++++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8qm-mek.dts       | 51 ++++++++++++
 .../boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso | 89 +++++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts      | 36 +++++++++
 6 files changed, 368 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 839432153cc7a..d1cbc08eb3f4d 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -261,12 +261,24 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-eval-v1.2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
+
+imx8qm-mek-ov5640-csi0-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo
+dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi0.dtb
+imx8qm-mek-ov5640-csi1-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi1.dtbo
+dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi1.dtb
+imx8qm-mek-ov5640-dual-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo imx8qm-mek-ov5640-csi1.dtbo
+dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-dual.dtb
+
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
+
+imx8qxp-mek-ov5640-csi-dtbs := imx8qxp-mek.dtb imx8qxp-mek-ov5640-csi.dtbo
+dtb-${CONFIG_ARCH_MXC} += imx8qxp-mek-ov5640-csi.dtb
+
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso
new file mode 100644
index 0000000000000..cfd599db997b9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 NXP
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/video-interfaces.h>
+
+&i2c_mipi_csi0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-0 = <&pinctrl_i2c_mipi_csi0>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	ov5640_mipi_0: camera@3c {
+		compatible = "ovti,ov5640";
+		reg = <0x3c>;
+		clocks = <&xtal24m>;
+		clock-names = "xclk";
+		pinctrl-0 = <&pinctrl_mipi_csi0>;
+		pinctrl-names = "default";
+		powerdown-gpios = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_LOW>;
+		AVDD-supply = <&reg_2v8>;
+		DVDD-supply = <&reg_1v5>;
+		DOVDD-supply = <&reg_1v8>;
+		status = "okay";
+
+		port {
+			ov5640_mipi_0_ep: endpoint {
+				bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+				data-lanes = <1 2>;
+				remote-endpoint = <&mipi_csi0_in>;
+			};
+		};
+	};
+};
+
+&irqsteer_csi0 {
+	status = "okay";
+};
+
+&isi {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@2 {
+			reg = <2>;
+
+			isi_in_2: endpoint {
+				remote-endpoint = <&mipi_csi0_out>;
+			};
+		};
+	};
+};
+
+&mipi_csi_0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			mipi_csi0_in: endpoint {
+				data-lanes = <1 2>;
+				remote-endpoint = <&ov5640_mipi_0_ep>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+
+			mipi_csi0_out: endpoint {
+				remote-endpoint = <&isi_in_2>;
+			};
+		};
+	};
+};
+
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso
new file mode 100644
index 0000000000000..199a79e98d88b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 NXP
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/video-interfaces.h>
+
+&i2c_mipi_csi1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-0 = <&pinctrl_i2c_mipi_csi1>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	ov5640_mipi_1: camera@3c {
+		compatible = "ovti,ov5640";
+		reg = <0x3c>;
+		clocks = <&xtal24m>;
+		clock-names = "xclk";
+		pinctrl-0 = <&pinctrl_mipi_csi1>;
+		pinctrl-names = "default";
+		powerdown-gpios = <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_LOW>;
+		AVDD-supply = <&reg_2v8>;
+		DVDD-supply = <&reg_1v5>;
+		DOVDD-supply = <&reg_1v8>;
+		status = "okay";
+
+		port {
+			ov5640_mipi_1_ep: endpoint {
+				bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+				data-lanes = <1 2>;
+				remote-endpoint = <&mipi_csi1_in>;
+			};
+		};
+	};
+};
+
+&irqsteer_csi1 {
+	status = "okay";
+};
+
+&isi {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@3 {
+			reg = <3>;
+
+			isi_in_3: endpoint {
+				remote-endpoint = <&mipi_csi1_out>;
+			};
+		};
+	};
+};
+
+&mipi_csi_1 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			mipi_csi1_in: endpoint {
+				data-lanes = <1 2>;
+				remote-endpoint = <&ov5640_mipi_1_ep>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+
+			mipi_csi1_out: endpoint {
+				remote-endpoint = <&isi_in_3>;
+			};
+		};
+	};
+};
+
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 61ef00f4259e1..3a6e25e08c26a 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -155,6 +155,27 @@ usb3_data_ss: endpoint {
 		};
 	};
 
+	reg_1v5: regulator-1v5 {
+		compatible = "regulator-fixed";
+		regulator-name = "1v5";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+	};
+
+	reg_1v8: regulator-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	reg_2v8: regulator-2v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "2v8";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+	};
+
 	reg_usdhc2_vmmc: usdhc2-vmmc {
 		compatible = "regulator-fixed";
 		regulator-name = "SD1_SPWR";
@@ -727,6 +748,20 @@ IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31			0x0600004c
 		>;
 	};
 
+	pinctrl_i2c_mipi_csi0: i2c-mipi-csi0grp {
+		fsl,pins = <
+			IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL		0xc2000020
+			IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA		0xc2000020
+		>;
+	};
+
+	pinctrl_i2c_mipi_csi1: i2c-mipi-csi1grp {
+		fsl,pins = <
+			IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL		0xc2000020
+			IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA		0xc2000020
+		>;
+	};
+
 	pinctrl_i2c0: i2c0grp {
 		fsl,pins = <
 			IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL			0x06000021
@@ -905,6 +940,22 @@ IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA	0xc600004c
 		>;
 	};
 
+	pinctrl_mipi_csi0: mipi-csi0grp {
+		fsl,pins = <
+			IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27		0xC0000041
+			IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28		0xC0000041
+			IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT	0xC0000041
+		>;
+	};
+
+	pinctrl_mipi_csi1: mipi-csi1grp {
+		fsl,pins = <
+			IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30		0xC0000041
+			IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31		0xC0000041
+			IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT	0xC0000041
+		>;
+	};
+
 	pinctrl_pciea: pcieagrp {
 		fsl,pins = <
 			IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28		0x04000021
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso
new file mode 100644
index 0000000000000..0546a2dc2a543
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/video-interfaces.h>
+
+&i2c_mipi_csi0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-0 = <&pinctrl_i2c_mipi_csi0>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	ov5640_mipi: camera@3c {
+		compatible = "ovti,ov5640";
+		reg = <0x3c>;
+		clocks = <&xtal24m>;
+		clock-names = "xclk";
+		pinctrl-0 = <&pinctrl_mipi_csi0>;
+		pinctrl-names = "default";
+		powerdown-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&lsio_gpio3 8 GPIO_ACTIVE_LOW>;
+		AVDD-supply = <&reg_2v8>;
+		DVDD-supply = <&reg_1v5>;
+		DOVDD-supply = <&reg_1v8>;
+		status = "okay";
+
+		port {
+			ov5640_mipi_ep: endpoint {
+				bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+				data-lanes = <1 2>;
+				remote-endpoint = <&mipi_csi0_in>;
+			};
+		};
+	};
+};
+
+&irqsteer_csi0 {
+	status = "okay";
+};
+
+&isi {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@2 {
+			reg = <2>;
+
+			isi_in_2: endpoint {
+				remote-endpoint = <&mipi_csi0_out>;
+			};
+		};
+	};
+};
+
+&mipi_csi_0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			mipi_csi0_in: endpoint {
+				data-lanes = <1 2>;
+				remote-endpoint = <&ov5640_mipi_ep>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+
+			mipi_csi0_out: endpoint {
+				remote-endpoint = <&isi_in_2>;
+			};
+		};
+	};
+};
+
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 89c6516c5ba90..a356c491375cb 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -90,6 +90,27 @@ usb3_data_ss: endpoint {
 		};
 	};
 
+	reg_1v5: regulator-1v5 {
+		compatible = "regulator-fixed";
+		regulator-name = "1v5";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+	};
+
+	reg_1v8: regulator-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	reg_2v8: regulator-2v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "2v8";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+	};
+
 	reg_pcieb: regulator-pcie {
 		compatible = "regulator-fixed";
 		regulator-max-microvolt = <3300000>;
@@ -749,6 +770,13 @@ IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX			0x21
 		>;
 	};
 
+	pinctrl_i2c_mipi_csi0: i2c-mipi-csi0grp {
+		fsl,pins = <
+			IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL		0xc2000020
+			IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA		0xc2000020
+		>;
+	};
+
 	pinctrl_ioexp_rst: ioexprstgrp {
 		fsl,pins = <
 			IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01			0x06000021
@@ -789,6 +817,14 @@ IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX       0x06000020
 		>;
 	};
 
+	pinctrl_mipi_csi0: mipi-csi0grp {
+		fsl,pins = <
+			IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07		0xC0000041
+			IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08		0xC0000041
+			IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT	0xC0000041
+		>;
+	};
+
 	pinctrl_pcieb: pcieagrp {
 		fsl,pins = <
 			IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000021

-- 
2.34.1

Re: [PATCH v3 01/12] dt-bindings: firmware: imx: add property reset-controller

[Rob Herring (Arm)]

On Mon, 10 Feb 2025 15:59:20 -0500, Frank Li wrote:
> System Controller Firmware(SCU) reset some peripherals, such as CSI. So add
> reset-controller for it.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change from v2 to v3
> -none
> 
> change from v1 to v2
> - new patch, move reset-controller in top fsl,scu.yaml
> ---
>  Documentation/devicetree/bindings/firmware/fsl,scu.yaml | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v3 03/12] media: dt-bindings: Add binding doc for i.MX8QXP and i.MX8QM ISI

[Rob Herring (Arm)]

On Mon, 10 Feb 2025 15:59:22 -0500, Frank Li wrote:
> Add binding documentation for i.MX8QXP and i.MX8QM ISI. The clock-names,
> power-domains, and ports differ significantly from the existing
> nxp,imx8-isi.yaml. Create a new file to avoid complex if-else branches.
> 
> Add new file to MAINTAINERS.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change from v2 to v3
> - none
> change from v1 to v2
> - create new file for 8qm and 8qxp accroding rob's suggestion.
> ---
>  .../devicetree/bindings/media/fsl,imx8qm-isi.yaml  | 117 +++++++++++++++++++++
>  .../devicetree/bindings/media/fsl,imx8qxp-isi.yaml | 103 ++++++++++++++++++
>  MAINTAINERS                                        |   1 +
>  3 files changed, 221 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v3 06/12] media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8QM(QXP) compatible strings

[Rob Herring (Arm)]

On Mon, 10 Feb 2025 15:59:25 -0500, Frank Li wrote:
> From: Robert Chiras <robert.chiras@nxp.com>
> 
> Add compatible strings for i.MX8QM/i.MX8QXP platform. Remove
> fsl,mipi-phy-gpr from required properties and add new reg space, since
> i.MX8QM and i.MX8QXP use dedicate control and status register(csr) space.
> 
> Keep the same restriction for other compatible strings.
> 
> Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change from v2 to v3
> - use dedicate csr register space
> change from v1 to v2
> - remove internal review tags
> - remove reg maxitems:1
> - remove 8ulp part
> - add 8qxp compatible string and make 8qm failback to 8qxp
> - limit reset and power domain number to 1 for 8qxp and 8qm
> - remove power-domains change because 8qm/8qxp only need 1 power domain
> ---
>  .../bindings/media/nxp,imx8mq-mipi-csi2.yaml       | 38 +++++++++++++++++++---
>  1 file changed, 34 insertions(+), 4 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v3 00/12] media: imx8: add camera support

[Frank Li]

On Mon, Feb 10, 2025 at 03:59:19PM -0500, Frank Li wrote:
> Add SCU reset driver for i.MX8QM/i.MX8QXP.
> Update binding doc.
> Update driver for imx8qxp and imx8qm.
> Add dts files for it.

Laurent Pinchart:

	Do you have any comments about this version?

Frank

>
> To: Rob Herring <robh@kernel.org>
> To: Krzysztof Kozlowski <krzk+dt@kernel.org>
> To: Conor Dooley <conor+dt@kernel.org>
> To: Dong Aisheng <aisheng.dong@nxp.com>
> To: Philipp Zabel <p.zabel@pengutronix.de>
> To: Shawn Guo <shawnguo@kernel.org>
> To: Sascha Hauer <s.hauer@pengutronix.de>
> To: Pengutronix Kernel Team <kernel@pengutronix.de>
> To: Fabio Estevam <festevam@gmail.com>
> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> To: Mauro Carvalho Chehab <mchehab@kernel.org>
> To: Rui Miguel Silva <rmfrfs@gmail.com>
> To: Martin Kepplinger <martink@posteo.de>
> To: Purism Kernel Team <kernel@puri.sm>
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: imx@lists.linux.dev
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-media@vger.kernel.org
> Cc: Robert Chiras <robert.chiras@nxp.com>
> Cc: "Guoniu.zhou" <guoniu.zhou@nxp.com>
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
>
> Changes in v3:
> - Remove phy driver parts.
> - csr is dedicate for mipi csi2, so add it as second register space. csr is
> mixed with PHY and link control with csi2.
> - Link to v2: https://lore.kernel.org/r/20250205-8qxp_camera-v2-0-731a3edf2744@nxp.com
>
> Changes in v2:
> - move scu reset binding doc to top scu doc.
> - isi use seperate binding doc for imx8qxp and imx8qm.
> - phy and csi2, compatible string 8qm fallback to qxp
> - remove internal review tags
> - Link to v1: https://lore.kernel.org/r/20250131-8qxp_camera-v1-0-319402ab606a@nxp.com
>
> ---
> Frank Li (9):
>       dt-bindings: firmware: imx: add property reset-controller
>       reset: imx: Add SCU reset driver for i.MX8QXP and i.MX8QM
>       media: dt-bindings: Add binding doc for i.MX8QXP and i.MX8QM ISI
>       media: nxp: imx8-isi: Allow num_sources to be greater than num_sink
>       media: imx8mq-mipi-csi2: Add support for i.MX8QXP
>       arm64: dts: imx8: add capture controller for i.MX8's img subsystem
>       arm64: dts: imx8qm: add 24MHz clock-xtal24m
>       arm64: dts: imx8q: add linux,cma node for imx8qm-mek and imx8qxp-mek
>       arm64: dts: imx8q: add camera ov5640 support for imx8qm-mek and imx8qxp-mek
>
> Guoniu.zhou (1):
>       media: imx8mq-mipi-csi2: Add imx8mq_plat_data for different compatible strings
>
> Robert Chiras (2):
>       media: imx8-isi: Add support for i.MX8QM and i.MX8QXP
>       media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8QM(QXP) compatible strings
>
>  .../devicetree/bindings/firmware/fsl,scu.yaml      |  12 +
>  .../devicetree/bindings/media/fsl,imx8qm-isi.yaml  | 117 +++++++
>  .../devicetree/bindings/media/fsl,imx8qxp-isi.yaml | 103 ++++++
>  .../bindings/media/nxp,imx8mq-mipi-csi2.yaml       |  38 ++-
>  MAINTAINERS                                        |   1 +
>  arch/arm64/boot/dts/freescale/Makefile             |  12 +
>  arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi     | 376 +++++++++++++++++++++
>  .../boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso |  90 +++++
>  .../boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso |  90 +++++
>  arch/arm64/boot/dts/freescale/imx8qm-mek.dts       |  60 ++++
>  arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi   |  45 +++
>  arch/arm64/boot/dts/freescale/imx8qm.dtsi          |  12 +
>  .../boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso |  89 +++++
>  arch/arm64/boot/dts/freescale/imx8qxp-mek.dts      |  44 +++
>  arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi  |  60 ++++
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi         |   5 +
>  .../media/platform/nxp/imx8-isi/imx8-isi-core.c    |  47 +++
>  .../media/platform/nxp/imx8-isi/imx8-isi-core.h    |   2 +
>  .../platform/nxp/imx8-isi/imx8-isi-crossbar.c      |   8 +-
>  drivers/media/platform/nxp/imx8mq-mipi-csi2.c      | 179 +++++++++-
>  drivers/reset/Kconfig                              |   7 +
>  drivers/reset/Makefile                             |   1 +
>  drivers/reset/reset-imx-scu.c                      | 101 ++++++
>  23 files changed, 1477 insertions(+), 22 deletions(-)
> ---
> base-commit: ce37eebeae8fa9e6c53f7f1ccd182ad5f27d66cd
> change-id: 20250114-8qxp_camera-c1af5749d304
>
> Best regards,
> ---
> Frank Li <Frank.Li@nxp.com>
>

Re: [PATCH v3 02/12] reset: imx: Add SCU reset driver for i.MX8QXP and i.MX8QM

[Philipp Zabel]

On Mo, 2025-02-10 at 15:59 -0500, Frank Li wrote:
> Add System Controller Firmware(SCU) reset driver for i.MX8QM and i.MX8QXP.
> SCU Manage resets for peripherals such as MIPI CSI. Currently, support two
> reset sources: IMX_SC_R_CSI_0 and IMX_SC_R_CSI_1.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>

Applied to reset/next, thanks!

[01/12] dt-bindings: firmware: imx: add property reset-controller
        https://git.pengutronix.de/cgit/pza/linux/commit/?id=778752759bd0
[02/12] reset: imx: Add SCU reset driver for i.MX8QXP and i.MX8QM
        https://git.pengutronix.de/cgit/pza/linux/commit/?id=6b64fde5c183

regards
Philipp

Re: [PATCH v3 00/12] media: imx8: add camera support

[Frank Li]

On Mon, Feb 10, 2025 at 03:59:19PM -0500, Frank Li wrote:
> Add SCU reset driver for i.MX8QM/i.MX8QXP.
> Update binding doc.
> Update driver for imx8qxp and imx8qm.
> Add dts files for it.
>

Laurent Pinchart:

	I saw Philipp Zabel already pick up SCU reset part. Do you have
more concern about media part? Could you please take care this patches?

Frank


> To: Rob Herring <robh@kernel.org>
> To: Krzysztof Kozlowski <krzk+dt@kernel.org>
> To: Conor Dooley <conor+dt@kernel.org>
> To: Dong Aisheng <aisheng.dong@nxp.com>
> To: Philipp Zabel <p.zabel@pengutronix.de>
> To: Shawn Guo <shawnguo@kernel.org>
> To: Sascha Hauer <s.hauer@pengutronix.de>
> To: Pengutronix Kernel Team <kernel@pengutronix.de>
> To: Fabio Estevam <festevam@gmail.com>
> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> To: Mauro Carvalho Chehab <mchehab@kernel.org>
> To: Rui Miguel Silva <rmfrfs@gmail.com>
> To: Martin Kepplinger <martink@posteo.de>
> To: Purism Kernel Team <kernel@puri.sm>
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: imx@lists.linux.dev
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-media@vger.kernel.org
> Cc: Robert Chiras <robert.chiras@nxp.com>
> Cc: "Guoniu.zhou" <guoniu.zhou@nxp.com>
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
>
> Changes in v3:
> - Remove phy driver parts.
> - csr is dedicate for mipi csi2, so add it as second register space. csr is
> mixed with PHY and link control with csi2.
> - Link to v2: https://lore.kernel.org/r/20250205-8qxp_camera-v2-0-731a3edf2744@nxp.com
>
> Changes in v2:
> - move scu reset binding doc to top scu doc.
> - isi use seperate binding doc for imx8qxp and imx8qm.
> - phy and csi2, compatible string 8qm fallback to qxp
> - remove internal review tags
> - Link to v1: https://lore.kernel.org/r/20250131-8qxp_camera-v1-0-319402ab606a@nxp.com
>
> ---
> Frank Li (9):
>       dt-bindings: firmware: imx: add property reset-controller
>       reset: imx: Add SCU reset driver for i.MX8QXP and i.MX8QM
>       media: dt-bindings: Add binding doc for i.MX8QXP and i.MX8QM ISI
>       media: nxp: imx8-isi: Allow num_sources to be greater than num_sink
>       media: imx8mq-mipi-csi2: Add support for i.MX8QXP
>       arm64: dts: imx8: add capture controller for i.MX8's img subsystem
>       arm64: dts: imx8qm: add 24MHz clock-xtal24m
>       arm64: dts: imx8q: add linux,cma node for imx8qm-mek and imx8qxp-mek
>       arm64: dts: imx8q: add camera ov5640 support for imx8qm-mek and imx8qxp-mek
>
> Guoniu.zhou (1):
>       media: imx8mq-mipi-csi2: Add imx8mq_plat_data for different compatible strings
>
> Robert Chiras (2):
>       media: imx8-isi: Add support for i.MX8QM and i.MX8QXP
>       media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8QM(QXP) compatible strings
>
>  .../devicetree/bindings/firmware/fsl,scu.yaml      |  12 +
>  .../devicetree/bindings/media/fsl,imx8qm-isi.yaml  | 117 +++++++
>  .../devicetree/bindings/media/fsl,imx8qxp-isi.yaml | 103 ++++++
>  .../bindings/media/nxp,imx8mq-mipi-csi2.yaml       |  38 ++-
>  MAINTAINERS                                        |   1 +
>  arch/arm64/boot/dts/freescale/Makefile             |  12 +
>  arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi     | 376 +++++++++++++++++++++
>  .../boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso |  90 +++++
>  .../boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso |  90 +++++
>  arch/arm64/boot/dts/freescale/imx8qm-mek.dts       |  60 ++++
>  arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi   |  45 +++
>  arch/arm64/boot/dts/freescale/imx8qm.dtsi          |  12 +
>  .../boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso |  89 +++++
>  arch/arm64/boot/dts/freescale/imx8qxp-mek.dts      |  44 +++
>  arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi  |  60 ++++
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi         |   5 +
>  .../media/platform/nxp/imx8-isi/imx8-isi-core.c    |  47 +++
>  .../media/platform/nxp/imx8-isi/imx8-isi-core.h    |   2 +
>  .../platform/nxp/imx8-isi/imx8-isi-crossbar.c      |   8 +-
>  drivers/media/platform/nxp/imx8mq-mipi-csi2.c      | 179 +++++++++-
>  drivers/reset/Kconfig                              |   7 +
>  drivers/reset/Makefile                             |   1 +
>  drivers/reset/reset-imx-scu.c                      | 101 ++++++
>  23 files changed, 1477 insertions(+), 22 deletions(-)
> ---
> base-commit: ce37eebeae8fa9e6c53f7f1ccd182ad5f27d66cd
> change-id: 20250114-8qxp_camera-c1af5749d304
>
> Best regards,
> ---
> Frank Li <Frank.Li@nxp.com>
>

Re: [PATCH v3 03/12] media: dt-bindings: Add binding doc for i.MX8QXP and i.MX8QM ISI

[Laurent Pinchart]

Hi Frank,

Thank you for the patch.

On Mon, Feb 10, 2025 at 03:59:22PM -0500, Frank Li wrote:
> Add binding documentation for i.MX8QXP and i.MX8QM ISI. The clock-names,
> power-domains, and ports differ significantly from the existing
> nxp,imx8-isi.yaml. Create a new file to avoid complex if-else branches.

Mixed feelings about having different bindings files for what is
essentially the same IP, but I won't object.

> Add new file to MAINTAINERS.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change from v2 to v3
> - none
> change from v1 to v2
> - create new file for 8qm and 8qxp accroding rob's suggestion.
> ---
>  .../devicetree/bindings/media/fsl,imx8qm-isi.yaml  | 117 +++++++++++++++++++++
>  .../devicetree/bindings/media/fsl,imx8qxp-isi.yaml | 103 ++++++++++++++++++
>  MAINTAINERS                                        |   1 +
>  3 files changed, 221 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml
> new file mode 100644
> index 0000000000000..61c551673e2a4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml
> @@ -0,0 +1,117 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/fsl,imx8qm-isi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: i.MX8QM Image Sensing Interface
> +
> +maintainers:
> +  - Frank Li <Frank.Li@nxp.com>
> +
> +description:
> +  The Image Sensing Interface (ISI) combines image processing pipelines with
> +  DMA engines to process and capture frames originating from a variety of
> +  sources. The inputs to the ISI go through Pixel Link interfaces, and their
> +  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
> +  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,imx8qm-isi
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 8
> +
> +  clock-names:
> +    items:
> +      - const: per0
> +      - const: per1
> +      - const: per2
> +      - const: per3
> +      - const: per4
> +      - const: per5
> +      - const: per6
> +      - const: per7
> +
> +  interrupts:
> +    maxItems: 8
> +
> +  power-domains:
> +    maxItems: 8

This surprises me. The reference manual does list 8 clocks and
interrupts, but only 6 channels in the ISI section (for instance in
15.6.1.1.4). Which one is wrong ?

> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +    properties:
> +      port@2:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: MIPI CSI-2 RX 0
> +      port@3:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: MIPI CSI-2 RX 1
> +      port@4:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: HDMI RX

Figure 15-59 in the reference manual list MIPI CSI-2 RX 0 and RX 1 as
connected to inputs 0 and 1 respectively.

> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - power-domains
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/clock/imx8-clock.h>
> +    #include <dt-bindings/clock/imx8-lpcg.h>
> +    #include <dt-bindings/firmware/imx/rsrc.h>
> +
> +    image-controller@58100000 {
> +        compatible = "fsl,imx8qm-isi";
> +        reg = <0x58100000 0x90000>;

The memory map in the reference manual lists the "Pixel DMA" region as
ending at 0x5817ffff. Shouldn't the length of the region be 0x80000 ?

> +        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
> +                 <&pdma1_lpcg IMX_LPCG_CLK_0>,
> +                 <&pdma2_lpcg IMX_LPCG_CLK_0>,
> +                 <&pdma3_lpcg IMX_LPCG_CLK_0>,
> +                 <&pdma4_lpcg IMX_LPCG_CLK_0>,
> +                 <&pdma5_lpcg IMX_LPCG_CLK_0>,
> +                 <&pdma6_lpcg IMX_LPCG_CLK_0>,
> +                 <&pdma7_lpcg IMX_LPCG_CLK_0>;
> +        clock-names = "per0", "per1", "per2", "per3",
> +                      "per4", "per5", "per6", "per7";
> +        power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>,
> +                        <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>,
> +                        <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>,
> +                        <&pd IMX_SC_R_ISI_CH6>, <&pd IMX_SC_R_ISI_CH7>;
> +
> +        ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            port@2 {
> +                reg = <2>;
> +                endpoint {
> +                    remote-endpoint = <&mipi_csi0_out>;
> +                };
> +            };
> +        };
> +    };
> +...
> diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml
> new file mode 100644
> index 0000000000000..818fea0e4679f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml
> @@ -0,0 +1,103 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/fsl,imx8qxp-isi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: i.MX8QXP Image Sensing Interface
> +
> +maintainers:
> +  - Frank Li <Frank.Li@nxp.com>
> +
> +description:
> +  The Image Sensing Interface (ISI) combines image processing pipelines with
> +  DMA engines to process and capture frames originating from a variety of
> +  sources. The inputs to the ISI go through Pixel Link interfaces, and their
> +  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
> +  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,imx8qxp-isi
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 5
> +
> +  clock-names:
> +    items:
> +      - const: per0
> +      - const: per4
> +      - const: per5
> +      - const: per6
> +      - const: per7
> +
> +  interrupts:
> +    maxItems: 5
> +
> +  power-domains:
> +    maxItems: 5

Here you have 5 channels, while the reference manual lists 8 interrupts
and 6 channels in the ISI documentation.

> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +    properties:
> +      port@2:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: MIPI CSI-2 RX 0
> +      port@6:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: CSI-2 Parallel RX

Table 15-6 in the reference manual lists the parallel port as input 4.

> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - power-domains
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/clock/imx8-clock.h>
> +    #include <dt-bindings/clock/imx8-lpcg.h>
> +    #include <dt-bindings/firmware/imx/rsrc.h>
> +
> +    image-controller@58100000 {
> +        compatible = "fsl,imx8qxp-isi";
> +        reg = <0x58100000 0x90000>;

Same comment here about the registers range.

> +        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
> +                 <&pdma4_lpcg IMX_LPCG_CLK_0>,
> +                 <&pdma5_lpcg IMX_LPCG_CLK_0>,
> +                 <&pdma6_lpcg IMX_LPCG_CLK_0>,
> +                 <&pdma7_lpcg IMX_LPCG_CLK_0>;
> +        clock-names = "per0", "per4", "per5", "per6", "per7";
> +        power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH4>,
> +                        <&pd IMX_SC_R_ISI_CH5>, <&pd IMX_SC_R_ISI_CH6>,
> +                        <&pd IMX_SC_R_ISI_CH7>;
> +
> +        ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            port@2 {
> +                reg = <2>;
> +                endpoint {
> +                    remote-endpoint = <&mipi_csi0_out>;
> +                };
> +            };
> +        };
> +    };
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 40d1b7ec30fde..f243257ef7653 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -17000,6 +17000,7 @@ NXP i.MX 8M ISI DRIVER
>  M:	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>  L:	linux-media@vger.kernel.org
>  S:	Maintained
> +F:	Documentation/devicetree/bindings/media/fsl,imx8*-isi.yaml
>  F:	Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml

Should nxp,imx8-isi.yaml be renamed to fsl,imx8-isi.yaml ?

>  F:	drivers/media/platform/nxp/imx8-isi/
>  

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 10/12] arm64: dts: imx8qm: add 24MHz clock-xtal24m

[Laurent Pinchart]

Hi Frank,

Thank you for the patch.

On Mon, Feb 10, 2025 at 03:59:29PM -0500, Frank Li wrote:
> Add fixed clock node clock-xtal24m to prepare to add camera support.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change from v1 to v3
> - none
> ---
>  arch/arm64/boot/dts/freescale/imx8qm.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> index c6a17a0d739c5..40cd45cd9f88f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> @@ -590,6 +590,13 @@ mipi_pll_div2_clk: clock-controller-mipi-div2-pll {
>  		clock-output-names = "mipi_pll_div2_clk";
>  	};
>  
> +	xtal24m: clock-xtal24m {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <24000000>;
> +		clock-output-names = "xtal_24MHz";
> +	};

This is a clock oscillator mounted on the PCB, isn't it ? It shouldn't
be in imx8qm.dtsi, but in board-specific DT sources.

> +
>  	vpu_subsys_dsp: bus@55000000 {
>  		compatible = "simple-bus";
>  		#address-cells = <1>;

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 11/12] arm64: dts: imx8q: add linux,cma node for imx8qm-mek and imx8qxp-mek

[Laurent Pinchart]

Hi Frank,

Thank you for the patch.

On Mon, Feb 10, 2025 at 03:59:30PM -0500, Frank Li wrote:
> Add linux,cma node because some devices, such as camera, need big continue
> physical memory.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change from v1 to v3
> - none
> ---
>  arch/arm64/boot/dts/freescale/imx8qm-mek.dts  | 9 +++++++++
>  arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 8 ++++++++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> index 50fd3370f7dce..61ef00f4259e1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> @@ -113,6 +113,15 @@ dsp_vdev0buffer: memory@94300000 {
>  			reg = <0 0x94300000 0 0x100000>;
>  			no-map;
>  		};
> +
> +		/* global autoconfigured region for contiguous allocations */
> +		linux,cma {
> +			compatible = "shared-dma-pool";
> +			alloc-ranges = <0 0xc0000000 0 0x3c000000>;
> +			size = <0 0x3c000000>;
> +			linux,cma-default;
> +			reusable;
> +		};

This is system memory. Why is it reserved here, hardcoding a specific
use case in a board DT, instead of specifying an overall CMA size in the
kernel configuration or through the kernel command line ?

>  	};
>  
>  	lvds_backlight0: backlight-lvds0 {
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> index be79c793213a5..89c6516c5ba90 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> @@ -56,6 +56,14 @@ dsp_vdev0buffer: memory@94300000 {
>  			reg = <0 0x94300000 0 0x100000>;
>  			no-map;
>  		};
> +
> +		linux,cma {
> +			compatible = "shared-dma-pool";
> +			alloc-ranges = <0 0xc0000000 0 0x3c000000>;
> +			size = <0 0x3c000000>;
> +			linux,cma-default;
> +			reusable;
> +		};
>  	};
>  
>  	reg_usdhc2_vmmc: usdhc2-vmmc {

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 10/12] arm64: dts: imx8qm: add 24MHz clock-xtal24m

[Laurent Pinchart]

On Thu, Mar 27, 2025 at 08:58:14PM +0200, Laurent Pinchart wrote:
> Hi Frank,
> 
> Thank you for the patch.
> 
> On Mon, Feb 10, 2025 at 03:59:29PM -0500, Frank Li wrote:
> > Add fixed clock node clock-xtal24m to prepare to add camera support.
> > 
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > change from v1 to v3
> > - none
> > ---
> >  arch/arm64/boot/dts/freescale/imx8qm.dtsi | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> > index c6a17a0d739c5..40cd45cd9f88f 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> > @@ -590,6 +590,13 @@ mipi_pll_div2_clk: clock-controller-mipi-div2-pll {
> >  		clock-output-names = "mipi_pll_div2_clk";
> >  	};
> >  
> > +	xtal24m: clock-xtal24m {
> > +		compatible = "fixed-clock";
> > +		#clock-cells = <0>;
> > +		clock-frequency = <24000000>;
> > +		clock-output-names = "xtal_24MHz";
> > +	};
> 
> This is a clock oscillator mounted on the PCB, isn't it ? It shouldn't
> be in imx8qm.dtsi, but in board-specific DT sources.

You add fixed regulators to arch/arm64/boot/dts/freescale/imx8qm-mek.dts
and arch/arm64/boot/dts/freescale/imx8qxp-mek.dts in patch 12/12, the
additional of the fixed clock could go there too, in the same patch.

> > +
> >  	vpu_subsys_dsp: bus@55000000 {
> >  		compatible = "simple-bus";
> >  		#address-cells = <1>;

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 06/12] media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8QM(QXP) compatible strings

[Laurent Pinchart]

Hi Frank,

Thank you for the patch.

On Mon, Feb 10, 2025 at 03:59:25PM -0500, Frank Li wrote:
> From: Robert Chiras <robert.chiras@nxp.com>
> 
> Add compatible strings for i.MX8QM/i.MX8QXP platform. Remove
> fsl,mipi-phy-gpr from required properties and add new reg space, since
> i.MX8QM and i.MX8QXP use dedicate control and status register(csr) space.
> 
> Keep the same restriction for other compatible strings.
> 
> Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change from v2 to v3
> - use dedicate csr register space
> change from v1 to v2
> - remove internal review tags
> - remove reg maxitems:1
> - remove 8ulp part
> - add 8qxp compatible string and make 8qm failback to 8qxp
> - limit reset and power domain number to 1 for 8qxp and 8qm
> - remove power-domains change because 8qm/8qxp only need 1 power domain
> ---
>  .../bindings/media/nxp,imx8mq-mipi-csi2.yaml       | 38 +++++++++++++++++++---
>  1 file changed, 34 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> index 2a14e3b0e0040..522449e50079e 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> @@ -16,11 +16,19 @@ description: |-
>  
>  properties:
>    compatible:
> -    enum:
> -      - fsl,imx8mq-mipi-csi2
> +    oneOf:
> +      - enum:
> +          - fsl,imx8mq-mipi-csi2
> +          - fsl,imx8qxp-mipi-csi2
> +      - items:
> +          - const: fsl,imx8qm-mipi-csi2
> +          - const: fsl,imx8qxp-mipi-csi2
>  
>    reg:
> -    maxItems: 1
> +    items:
> +      - description: mipi csi2 rx host controller register.

s/mipi csi2 rx/MIPI CSI-2 RX/

> +      - description: mipi csi2 control and status register (csr).

Same here, and s/csr/CSR/

> +    minItems: 1
>  
>    clocks:
>      items:
> @@ -46,6 +54,7 @@ properties:
>        - description: CORE_RESET reset register bit definition
>        - description: PHY_REF_RESET reset register bit definition
>        - description: ESC_RESET reset register bit definition
> +    minItems: 1

Is this because on QM and QXP the three resets are handled by the SCU,
which exposes them as a single reset ? The reset description is then not
very accurate anymore, but I suppose we can live with that.

With the above small changes,

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

>  
>    fsl,mipi-phy-gpr:
>      description: |
> @@ -113,9 +122,30 @@ required:
>    - clock-names
>    - power-domains
>    - resets
> -  - fsl,mipi-phy-gpr
>    - ports
>  
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,imx8qxp-mipi-csi2
> +    then:
> +      properties:
> +        reg:
> +          minItems: 2
> +        resets:
> +          maxItems: 1
> +    else:
> +      properties:
> +        reg:
> +          maxItems: 1
> +        resets:
> +          minItems: 3
> +      required:
> +        - fsl,mipi-phy-gpr
> +
>  additionalProperties: false
>  
>  examples:

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 09/12] arm64: dts: imx8: add capture controller for i.MX8's img subsystem

[Laurent Pinchart]

Hi Frank,

Thank you for the patch.

On Mon, Feb 10, 2025 at 03:59:28PM -0500, Frank Li wrote:
> Add CSI related nodes (i2c, irqsteer, csi, lpcg) for i.MX8 img subsystem.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> Change from v2 to v3
> - remove phy and put csr register space under mipi csi2
> 
> change from v1 to v2
> - move scu reset under scu node
> - add 8qm comaptible string for mipi csi2 and mipi csi phys.
> ---
>  arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi    | 376 ++++++++++++++++++++++
>  arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi  |  45 +++
>  arch/arm64/boot/dts/freescale/imx8qm.dtsi         |   5 +
>  arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi |  60 ++++
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi        |   5 +
>  5 files changed, 491 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
> index d39242c1b9f79..eb41a6fcaf5b8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
> @@ -3,6 +3,14 @@
>   * Copyright 2019-2021 NXP
>   * Zhou Guoniu <guoniu.zhou@nxp.com>
>   */
> +
> +img_axi_clk: clock-img-axi {
> +	compatible = "fixed-clock";
> +	#clock-cells = <0>;
> +	clock-frequency = <400000000>;
> +	clock-output-names = "img_axi_clk";
> +};
> +

This doesn't seem to be used.

>  img_ipg_clk: clock-img-ipg {
>  	compatible = "fixed-clock";
>  	#clock-cells = <0>;
> @@ -10,12 +18,270 @@ img_ipg_clk: clock-img-ipg {
>  	clock-output-names = "img_ipg_clk";
>  };
>  
> +img_pxl_clk: clock-img-pxl {
> +	compatible = "fixed-clock";
> +	#clock-cells = <0>;
> +	clock-frequency = <600000000>;
> +	clock-output-names = "img_pxl_clk";
> +};
> +
>  img_subsys: bus@58000000 {
>  	compatible = "simple-bus";
>  	#address-cells = <1>;
>  	#size-cells = <1>;
>  	ranges = <0x58000000 0x0 0x58000000 0x1000000>;
>  
> +	isi: isi@58100000 {
> +		reg = <0x58100000 0x90000>;
> +		interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
> +			 <&pdma1_lpcg IMX_LPCG_CLK_0>,
> +			 <&pdma2_lpcg IMX_LPCG_CLK_0>,
> +			 <&pdma3_lpcg IMX_LPCG_CLK_0>,
> +			 <&pdma4_lpcg IMX_LPCG_CLK_0>,
> +			 <&pdma5_lpcg IMX_LPCG_CLK_0>,
> +			 <&pdma6_lpcg IMX_LPCG_CLK_0>,
> +			 <&pdma7_lpcg IMX_LPCG_CLK_0>;
> +		clock-names = "per0",
> +			      "per1",
> +			      "per2",
> +			      "per3",
> +			      "per4",
> +			      "per5",
> +			      "per6",
> +			      "per7";
> +		interrupt-parent = <&gic>;
> +		power-domains = <&pd IMX_SC_R_ISI_CH0>,
> +				<&pd IMX_SC_R_ISI_CH1>,
> +				<&pd IMX_SC_R_ISI_CH2>,
> +				<&pd IMX_SC_R_ISI_CH3>,
> +				<&pd IMX_SC_R_ISI_CH4>,
> +				<&pd IMX_SC_R_ISI_CH5>,
> +				<&pd IMX_SC_R_ISI_CH6>,
> +				<&pd IMX_SC_R_ISI_CH7>;
> +		status = "disabled";
> +	};
> +
> +	irqsteer_csi0: irqsteer@58220000 {
> +		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
> +		reg = <0x58220000 0x1000>;
> +		#interrupt-cells = <1>;
> +		interrupt-controller;
> +		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&img_ipg_clk>;
> +		clock-names = "ipg";
> +		interrupt-parent = <&gic>;
> +		power-domains = <&pd IMX_SC_R_CSI_0>;
> +		fsl,channel = <0>;
> +		fsl,num-irqs = <32>;
> +		status = "disabled";
> +	};
> +
> +	gpio0_mipi_csi0: gpio@58222000 {
> +		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
> +		reg = <0x58222000 0x1000>;
> +		#interrupt-cells = <2>;
> +		interrupt-controller;
> +		interrupts = <0>;
> +		#gpio-cells = <2>;
> +		gpio-controller;
> +		interrupt-parent = <&irqsteer_csi0>;
> +		power-domains = <&pd IMX_SC_R_CSI_0>;
> +	};
> +
> +	csi0_core_lpcg: clock-controller@58223018 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58223018 0x4>;
> +		clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_4>;
> +		clock-output-names = "csi0_lpcg_core_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH0>;
> +	};
> +
> +	csi0_esc_lpcg: clock-controller@5822301c {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x5822301c 0x4>;
> +		clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_4>;
> +		clock-output-names = "csi0_lpcg_esc_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH0>;
> +	};
> +
> +	i2c_mipi_csi0: i2c@58226000 {
> +		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +		reg = <0x58226000 0x1000>;
> +		interrupts = <8>;
> +		clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>,
> +			 <&img_ipg_clk>;
> +		clock-names = "per", "ipg";
> +		assigned-clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates = <24000000>;
> +		interrupt-parent = <&irqsteer_csi0>;
> +		power-domains = <&pd IMX_SC_R_CSI_0_I2C_0>;
> +		status = "disabled";
> +	};
> +
> +	mipi_csi_0: csi@58227000 {
> +		compatible = "fsl,imx8qxp-mipi-csi2";
> +		reg = <0x58227000 0x1000>,
> +		      <0x58221000 0x1000>;
> +		clocks = <&csi0_core_lpcg IMX_LPCG_CLK_4>,
> +			 <&csi0_esc_lpcg IMX_LPCG_CLK_4>,
> +			 <&csi0_pxl_lpcg IMX_LPCG_CLK_0>;
> +		clock-names = "core", "esc", "ui";
> +		assigned-clocks = <&csi0_core_lpcg IMX_LPCG_CLK_4>,
> +				  <&csi0_esc_lpcg IMX_LPCG_CLK_4>;
> +		assigned-clock-rates = <360000000>, <72000000>;
> +		power-domains = <&pd IMX_SC_R_ISI_CH0>;
> +		resets = <&scu_reset IMX_SC_R_CSI_0>;
> +		status = "disabled";
> +	};
> +
> +	irqsteer_csi1: irqsteer@58240000 {
> +		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
> +		reg = <0x58240000 0x1000>;
> +		#interrupt-cells = <1>;
> +		interrupt-controller;
> +		interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&img_ipg_clk>;
> +		clock-names = "ipg";
> +		interrupt-parent = <&gic>;
> +		power-domains = <&pd IMX_SC_R_CSI_1>;
> +		fsl,channel = <0>;
> +		fsl,num-irqs = <32>;
> +		status = "disabled";
> +	};
> +
> +	gpio0_mipi_csi1: gpio@58242000 {
> +		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
> +		reg = <0x58242000 0x1000>;
> +		#interrupt-cells = <2>;
> +		interrupt-controller;
> +		interrupts = <0>;
> +		#gpio-cells = <2>;
> +		gpio-controller;
> +		interrupt-parent = <&irqsteer_csi1>;
> +		power-domains = <&pd IMX_SC_R_CSI_1>;
> +	};
> +
> +	csi1_core_lpcg: clock-controller@58243018 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58243018 0x4>;
> +		clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_4>;
> +		clock-output-names = "csi1_lpcg_core_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH0>;
> +	};
> +
> +	csi1_esc_lpcg: clock-controller@5824301c {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x5824301c 0x4>;
> +		clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_4>;
> +		clock-output-names = "csi1_lpcg_esc_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH0>;
> +	};
> +
> +	i2c_mipi_csi1: i2c@58246000 {
> +		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +		reg = <0x58246000 0x1000>;
> +		interrupts = <8>;
> +		clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>,
> +			 <&img_ipg_clk>;
> +		clock-names = "per", "ipg";
> +		assigned-clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates = <24000000>;
> +		interrupt-parent = <&irqsteer_csi1>;
> +		power-domains = <&pd IMX_SC_R_CSI_1_I2C_0>;
> +		status = "disabled";
> +	};
> +
> +	mipi_csi_1: csi@58247000 {
> +		compatible = "fsl,imx8qxp-mipi-csi2";
> +		reg = <0x58247000 0x1000>,
> +		      <0x58241000 0x1000>;
> +		clocks = <&csi1_core_lpcg IMX_LPCG_CLK_4>,
> +			 <&csi1_esc_lpcg IMX_LPCG_CLK_4>,
> +			 <&csi1_pxl_lpcg IMX_LPCG_CLK_0>;
> +		clock-names = "core", "esc", "ui";
> +		assigned-clocks = <&csi1_core_lpcg IMX_LPCG_CLK_4>,
> +				  <&csi1_esc_lpcg IMX_LPCG_CLK_4>;
> +		assigned-clock-rates = <360000000>, <72000000>;
> +		power-domains = <&pd IMX_SC_R_ISI_CH0>;
> +		resets = <&scu_reset IMX_SC_R_CSI_1>;
> +		status = "disabled";
> +	};
> +
> +	irqsteer_parallel: irqsteer@58260000 {
> +		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
> +		reg = <0x58260000 0x1000>;
> +		#interrupt-cells = <1>;
> +		interrupt-controller;
> +		interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&clk_dummy>;
> +		clock-names = "ipg";
> +		interrupt-parent = <&gic>;
> +		power-domains = <&pd IMX_SC_R_PI_0>;
> +		fsl,channel = <0>;
> +		fsl,num-irqs = <32>;
> +		status = "disabled";
> +	};
> +
> +	pi0_ipg_lpcg: clock-controller@58263004 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58263004 0x4>;
> +		clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_4>;
> +		clock-output-names = "pi0_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH0>;
> +	};
> +
> +	pi0_pxl_lpcg: clock-controller@58263018 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58263018 0x4>;
> +		clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "pi0_lpcg_pxl_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH0>;
> +	};
> +
> +	pi0_misc_lpcg: clock-controller@5826301c {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x5826301c 0x4>;
> +		clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "pi0_lpcg_misc_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH0>;
> +	};
> +
> +	i2c0_parallel: i2c@58266000 {
> +		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +		reg = <0x58266000 0x1000>;
> +		interrupts = <8>;
> +		clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>,
> +			 <&img_ipg_clk>;
> +		clock-names = "per", "ipg";
> +		assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates = <24000000>;
> +		interrupt-parent = <&irqsteer_parallel>;
> +		power-domains = <&pd IMX_SC_R_PI_0_I2C_0>;
> +		status = "disabled";
> +	};
> +
>  	jpegdec: jpegdec@58400000 {
>  		reg = <0x58400000 0x00050000>;
>  		interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
> @@ -40,6 +306,116 @@ jpegenc: jpegenc@58450000 {
>  				<&pd IMX_SC_R_MJPEG_ENC_S0>;
>  	};
>  
> +	pdma0_lpcg: clock-controller@58500000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58500000 0x10000>;
> +		clocks = <&img_pxl_clk>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "pdma0_lpcg_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH0>;
> +	};
> +
> +	pdma1_lpcg: clock-controller@58510000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58510000 0x10000>;
> +		clocks = <&img_pxl_clk>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "pdma1_lpcg_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH1>;
> +	};
> +
> +	pdma2_lpcg: clock-controller@58520000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58520000 0x10000>;
> +		clocks = <&img_pxl_clk>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "pdma2_lpcg_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH2>;
> +	};
> +
> +	pdma3_lpcg: clock-controller@58530000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58530000 0x10000>;
> +		clocks = <&img_pxl_clk>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "pdma3_lpcg_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH3>;
> +	};
> +
> +	pdma4_lpcg: clock-controller@58540000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58540000 0x10000>;
> +		clocks = <&img_pxl_clk>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "pdma4_lpcg_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH4>;
> +	};
> +
> +	pdma5_lpcg: clock-controller@58550000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58550000 0x10000>;
> +		clocks = <&img_pxl_clk>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "pdma5_lpcg_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH5>;
> +	};
> +
> +	pdma6_lpcg: clock-controller@58560000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58560000 0x10000>;
> +		clocks = <&img_pxl_clk>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "pdma6_lpcg_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH6>;
> +	};
> +
> +	pdma7_lpcg: clock-controller@58570000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58570000 0x10000>;
> +		clocks = <&img_pxl_clk>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "pdma7_lpcg_clk";
> +		power-domains = <&pd IMX_SC_R_ISI_CH7>;
> +	};
> +
> +	csi0_pxl_lpcg: clock-controller@58580000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58580000 0x10000>;
> +		clocks = <&img_pxl_clk>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "csi0_lpcg_pxl_clk";
> +		power-domains = <&pd IMX_SC_R_CSI_0>;
> +	};
> +
> +	csi1_pxl_lpcg: clock-controller@58590000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x58590000 0x10000>;
> +		clocks = <&img_pxl_clk>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "csi1_lpcg_pxl_clk";
> +		power-domains = <&pd IMX_SC_R_CSI_1>;
> +	};
> +
> +	hdmi_rx_pxl_link_lpcg: clock-controller@585a0000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x585a0000 0x10000>;
> +		clocks = <&img_pxl_clk>;
> +		#clock-cells = <1>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "hdmi_rx_lpcg_pxl_link_clk";
> +		power-domains = <&pd IMX_SC_R_HDMI_RX>;
> +	};
> +
>  	img_jpeg_dec_lpcg: clock-controller@585d0000 {
>  		compatible = "fsl,imx8qxp-lpcg";
>  		reg = <0x585d0000 0x10000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
> index 2bbdacb1313f9..efca0baec4b47 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
> @@ -3,6 +3,31 @@
>   * Copyright 2021 NXP
>   */
>  
> +&isi {
> +	compatible = "fsl,imx8qm-isi";
> +
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port@0 {
> +			reg = <0>;
> +		};
> +
> +		port@1 {
> +			reg = <1>;
> +		};
> +
> +		port@2 {
> +			reg = <2>;
> +		};
> +
> +		port@3 {
> +			reg = <3>;
> +		};

This doesn't match the ports listed in the bindings.

I think you should connect ports to the CSI-2 RX controllers in this
file. Same for imx8qxp-ss-img.dtsi.

> +	};
> +};
> +
>  &jpegdec {
>  	compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgdec";
>  };
> @@ -10,3 +35,23 @@ &jpegdec {
>  &jpegenc {
>  	compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
>  };
> +
> +&mipi_csi_0 {
> +	compatible = "fsl,imx8qm-mipi-csi2", "fsl,imx8qxp-mipi-csi2";
> +};
> +
> +&mipi_csi_1 {
> +	compatible = "fsl,imx8qm-mipi-csi2", "fsl,imx8qxp-mipi-csi2";
> +};
> +
> +&pi0_ipg_lpcg {
> +	status = "disabled";
> +};
> +
> +&pi0_misc_lpcg {
> +	status = "disabled";
> +};
> +
> +&pi0_pxl_lpcg {
> +	status = "disabled";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> index 6fa31bc9ece8f..c6a17a0d739c5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> @@ -333,6 +333,11 @@ iomuxc: pinctrl {
>  			compatible = "fsl,imx8qm-iomuxc";
>  		};
>  
> +		scu_reset: reset-controller {
> +			compatible = "fsl,imx-scu-reset";
> +			#reset-cells = <1>;
> +		};
> +
>  		rtc: rtc {
>  			compatible = "fsl,imx8qxp-sc-rtc";
>  		};
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
> index 3a087317591d8..4c15e4569a51a 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
> @@ -4,6 +4,62 @@
>   *	Dong Aisheng <aisheng.dong@nxp.com>
>   */
>  
> +&csi1_pxl_lpcg {
> +	status = "disabled";
> +};
> +
> +&csi1_core_lpcg {
> +	status = "disabled";
> +};
> +
> +&csi1_esc_lpcg {
> +	status = "disabled";
> +};
> +
> +&gpio0_mipi_csi1 {
> +	status = "disabled";
> +};
> +
> +&i2c_mipi_csi1 {
> +	status = "disabled";
> +};
> +
> +&irqsteer_csi1 {
> +	status = "disabled";
> +};
> +
> +&isi {
> +	compatible = "fsl,imx8qxp-isi";
> +	interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> +		     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> +		     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> +		     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> +		     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
> +	clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>, <&pdma4_lpcg IMX_LPCG_CLK_0>,
> +		 <&pdma5_lpcg IMX_LPCG_CLK_0>, <&pdma6_lpcg IMX_LPCG_CLK_0>,
> +		 <&pdma7_lpcg IMX_LPCG_CLK_0>;
> +	clock-names = "per0", "per4", "per5", "per6", "per7";
> +	power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>,
> +			<&pd IMX_SC_R_ISI_CH6>, <&pd IMX_SC_R_ISI_CH7>;
> +
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port@0 {
> +			reg = <0>;
> +		};
> +
> +		port@1 {
> +			reg = <1>;
> +		};
> +
> +		port@2 {
> +			reg = <2>;
> +		};
> +	};
> +};
> +
>  &jpegdec {
>  	compatible = "nxp,imx8qxp-jpgdec";
>  };
> @@ -11,3 +67,7 @@ &jpegdec {
>  &jpegenc {
>  	compatible = "nxp,imx8qxp-jpgenc";
>  };
> +
> +&mipi_csi_1 {
> +	status = "disabled";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 05138326f0a57..c078d92f76c0e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -241,6 +241,11 @@ scu_key: keys {
>  			status = "disabled";
>  		};
>  
> +		scu_reset: reset-controller {
> +			compatible = "fsl,imx-scu-reset";
> +			#reset-cells = <1>;
> +		};
> +
>  		rtc: rtc {
>  			compatible = "fsl,imx8qxp-sc-rtc";
>  		};

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 04/12] media: nxp: imx8-isi: Allow num_sources to be greater than num_sink

[Laurent Pinchart]

Hi Frank,

Thank you for the patch.

On Mon, Feb 10, 2025 at 03:59:23PM -0500, Frank Li wrote:
> Allow num_sources (drvdata: num_channels) to be greater than num_sink
> (drvdata: num_ports + 1).
> 
> ISI support stream multiplexing, such as differentiates multiple cameras
> from a single 2-lane MIPI input, or duplicates input stream into multiple
> outputs. So num_channels may be greater than num_ports at some platform.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change from v1 to v3
> - none
> ---
>  drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c b/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c
> index 93a55c97cd173..ba5b2d3617a23 100644
> --- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c
> +++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c
> @@ -188,11 +188,11 @@ static int mxc_isi_crossbar_init_state(struct v4l2_subdev *sd,
>  	 * Create a 1:1 mapping between pixel link inputs and outputs to
>  	 * pipelines by default.
>  	 */

Move

	routing.num_routes = xbar->num_sinks - 1;

here, and use routing.num_routes below to replace xbar->num_sinks - 1.

This assumes that there will always be as many or more pipelines than
pixel links. It's true for all the currently supported SoCs and the ones
you add in this series, but maybe we could make it safer with

	routing.num_routes = min(xbar->num_sinks - 1, xbar->num_sources);

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> -	routes = kcalloc(xbar->num_sources, sizeof(*routes), GFP_KERNEL);
> +	routes = kcalloc(xbar->num_sinks - 1, sizeof(*routes), GFP_KERNEL);
>  	if (!routes)
>  		return -ENOMEM;
>  
> -	for (i = 0; i < xbar->num_sources; ++i) {
> +	for (i = 0; i < xbar->num_sinks - 1; ++i) {
>  		struct v4l2_subdev_route *route = &routes[i];
>  
>  		route->sink_pad = i;
> @@ -200,7 +200,7 @@ static int mxc_isi_crossbar_init_state(struct v4l2_subdev *sd,
>  		route->flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE;
>  	}
>  
> -	routing.num_routes = xbar->num_sources;
> +	routing.num_routes = xbar->num_sinks - 1;
>  	routing.routes = routes;
>  
>  	ret = __mxc_isi_crossbar_set_routing(sd, state, &routing);
> @@ -453,7 +453,7 @@ int mxc_isi_crossbar_init(struct mxc_isi_dev *isi)
>  	 * the memory input.
>  	 */
>  	xbar->num_sinks = isi->pdata->num_ports + 1;
> -	xbar->num_sources = isi->pdata->num_ports;
> +	xbar->num_sources = isi->pdata->num_channels;
>  	num_pads = xbar->num_sinks + xbar->num_sources;
>  
>  	xbar->pads = kcalloc(num_pads, sizeof(*xbar->pads), GFP_KERNEL);

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 04/12] media: nxp: imx8-isi: Allow num_sources to be greater than num_sink

[Adam Ford]

On Mon, Feb 10, 2025 at 3:01 PM Frank Li <Frank.Li@nxp.com> wrote:
>
> Allow num_sources (drvdata: num_channels) to be greater than num_sink
> (drvdata: num_ports + 1).
>
> ISI support stream multiplexing, such as differentiates multiple cameras
> from a single 2-lane MIPI input, or duplicates input stream into multiple
> outputs. So num_channels may be greater than num_ports at some platform.

Can you tell me which platforms support this?   Is this through
virtual channels, or do you physically connect lanes 1 and 2 to one
camera and lanes 3 and 4 to another?

adam
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change from v1 to v3
> - none
> ---
>  drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c b/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c
> index 93a55c97cd173..ba5b2d3617a23 100644
> --- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c
> +++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c
> @@ -188,11 +188,11 @@ static int mxc_isi_crossbar_init_state(struct v4l2_subdev *sd,
>          * Create a 1:1 mapping between pixel link inputs and outputs to
>          * pipelines by default.
>          */
> -       routes = kcalloc(xbar->num_sources, sizeof(*routes), GFP_KERNEL);
> +       routes = kcalloc(xbar->num_sinks - 1, sizeof(*routes), GFP_KERNEL);
>         if (!routes)
>                 return -ENOMEM;
>
> -       for (i = 0; i < xbar->num_sources; ++i) {
> +       for (i = 0; i < xbar->num_sinks - 1; ++i) {
>                 struct v4l2_subdev_route *route = &routes[i];
>
>                 route->sink_pad = i;
> @@ -200,7 +200,7 @@ static int mxc_isi_crossbar_init_state(struct v4l2_subdev *sd,
>                 route->flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE;
>         }
>
> -       routing.num_routes = xbar->num_sources;
> +       routing.num_routes = xbar->num_sinks - 1;
>         routing.routes = routes;
>
>         ret = __mxc_isi_crossbar_set_routing(sd, state, &routing);
> @@ -453,7 +453,7 @@ int mxc_isi_crossbar_init(struct mxc_isi_dev *isi)
>          * the memory input.
>          */
>         xbar->num_sinks = isi->pdata->num_ports + 1;
> -       xbar->num_sources = isi->pdata->num_ports;
> +       xbar->num_sources = isi->pdata->num_channels;
>         num_pads = xbar->num_sinks + xbar->num_sources;
>
>         xbar->pads = kcalloc(num_pads, sizeof(*xbar->pads), GFP_KERNEL);
>
> --
> 2.34.1
>
>

Re: [PATCH v3 05/12] media: imx8-isi: Add support for i.MX8QM and i.MX8QXP

[Laurent Pinchart]

Hi Frank,

Thank you for the patch.

On Mon, Feb 10, 2025 at 03:59:24PM -0500, Frank Li wrote:
> From: Robert Chiras <robert.chiras@nxp.com>
> 
> Add compatibles and platform data for i.MX8QM and i.MX8QXP platforms.
> There are 8 ISI channels on i.MX8QM while there are only 5 channels on
> i.MX8QXP.

There's a discrepancy between this series and the reference manuals.
I've raised that issue in the review of the DT bindings, let's discuss
it there. I'll skip that part of this patch for now.

> Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change from v2 to v3
> - none
> 
> change from v1 to v2
> - remove intenal review tags
> ---
>  .../media/platform/nxp/imx8-isi/imx8-isi-core.c    | 47 ++++++++++++++++++++++
>  .../media/platform/nxp/imx8-isi/imx8-isi-core.h    |  2 +
>  2 files changed, 49 insertions(+)
> 
> diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c
> index 1e79b1211b603..a3237d76f7aa5 100644
> --- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c
> +++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c
> @@ -274,6 +274,25 @@ static const struct mxc_isi_set_thd mxc_imx8_isi_thd_v1 = {
>  	.panic_set_thd_v = { .mask = 0xf0000, .offset = 16, .threshold = 0x7 },
>  };
>  
> +static const struct clk_bulk_data mxc_imx8qm_clks[] = {
> +	{ .id = "per0" },
> +	{ .id = "per1" },
> +	{ .id = "per2" },
> +	{ .id = "per3" },
> +	{ .id = "per4" },
> +	{ .id = "per5" },
> +	{ .id = "per6" },
> +	{ .id = "per7" },
> +};
> +
> +static const struct clk_bulk_data mxc_imx8qxp_clks[] = {
> +	{ .id = "per0" },
> +	{ .id = "per4" },
> +	{ .id = "per5" },
> +	{ .id = "per6" },
> +	{ .id = "per7" },
> +};
> +
>  static const struct clk_bulk_data mxc_imx8mn_clks[] = {
>  	{ .id = "axi" },
>  	{ .id = "apb" },
> @@ -334,6 +353,32 @@ static const struct mxc_isi_plat_data mxc_imx93_data = {
>  	.has_36bit_dma		= false,
>  };
>  
> +static const struct mxc_isi_plat_data mxc_imx8qm_data = {
> +	.model			= MXC_ISI_IMX8QM,
> +	.num_ports		= 5,
> +	.num_channels		= 8,
> +	.reg_offset		= 0x10000,
> +	.ier_reg		= &mxc_imx8_isi_ier_v1,

Are you sure about this ? According to the reference manual, QXP seems
to match mxc_imx8_isi_ier_v2, and QM doesn't seem to match either v1 or
v2.

> +	.set_thd		= &mxc_imx8_isi_thd_v1,
> +	.clks			= mxc_imx8qm_clks,
> +	.num_clks		= ARRAY_SIZE(mxc_imx8qm_clks),
> +	.buf_active_reverse	= true,

I'll trust you on this value, I can't verify it.

> +	.has_36bit_dma		= false,
> +};
> +
> +static const struct mxc_isi_plat_data mxc_imx8qxp_data = {
> +	.model			= MXC_ISI_IMX8QXP,
> +	.num_ports		= 5,
> +	.num_channels		= 5,
> +	.reg_offset		= 0x10000,
> +	.ier_reg		= &mxc_imx8_isi_ier_v1,
> +	.set_thd		= &mxc_imx8_isi_thd_v1,
> +	.clks			= mxc_imx8qxp_clks,
> +	.num_clks		= ARRAY_SIZE(mxc_imx8qxp_clks),
> +	.buf_active_reverse	= true,
> +	.has_36bit_dma		= false,
> +};
> +
>  /* -----------------------------------------------------------------------------
>   * Power management
>   */
> @@ -541,6 +586,8 @@ static void mxc_isi_remove(struct platform_device *pdev)
>  static const struct of_device_id mxc_isi_of_match[] = {
>  	{ .compatible = "fsl,imx8mn-isi", .data = &mxc_imx8mn_data },
>  	{ .compatible = "fsl,imx8mp-isi", .data = &mxc_imx8mp_data },
> +	{ .compatible = "fsl,imx8qm-isi", .data = &mxc_imx8qm_data },
> +	{ .compatible = "fsl,imx8qxp-isi", .data = &mxc_imx8qxp_data },
>  	{ .compatible = "fsl,imx8ulp-isi", .data = &mxc_imx8ulp_data },
>  	{ .compatible = "fsl,imx93-isi", .data = &mxc_imx93_data },
>  	{ /* sentinel */ },
> diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h
> index 9c7fe9e5f941f..496cad3f9423d 100644
> --- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h
> +++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h
> @@ -158,6 +158,8 @@ struct mxc_gasket_ops {
>  enum model {
>  	MXC_ISI_IMX8MN,
>  	MXC_ISI_IMX8MP,
> +	MXC_ISI_IMX8QM,
> +	MXC_ISI_IMX8QXP,
>  	MXC_ISI_IMX8ULP,
>  	MXC_ISI_IMX93,
>  };

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 03/12] media: dt-bindings: Add binding doc for i.MX8QXP and i.MX8QM ISI

[Frank Li]

On Thu, Mar 27, 2025 at 08:44:25PM +0200, Laurent Pinchart wrote:
> Hi Frank,
>
> Thank you for the patch.
>
> On Mon, Feb 10, 2025 at 03:59:22PM -0500, Frank Li wrote:
> > Add binding documentation for i.MX8QXP and i.MX8QM ISI. The clock-names,
> > power-domains, and ports differ significantly from the existing
> > nxp,imx8-isi.yaml. Create a new file to avoid complex if-else branches.
>
> Mixed feelings about having different bindings files for what is
> essentially the same IP, but I won't object.

Rob suggest split it at v1.

https://lore.kernel.org/all/20250203221659.GA130749-robh@kernel.org/

"I think this addition is borderline whether it should be its own schema
doc. The if/then schemas are larger than the main part. The ports are
not even the same."

>
> > Add new file to MAINTAINERS.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > change from v2 to v3
> > - none
> > change from v1 to v2
> > - create new file for 8qm and 8qxp accroding rob's suggestion.
> > ---
> >  .../devicetree/bindings/media/fsl,imx8qm-isi.yaml  | 117 +++++++++++++++++++++
> >  .../devicetree/bindings/media/fsl,imx8qxp-isi.yaml | 103 ++++++++++++++++++
> >  MAINTAINERS                                        |   1 +
> >  3 files changed, 221 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml
> > new file mode 100644
> > index 0000000000000..61c551673e2a4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml
> > @@ -0,0 +1,117 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/media/fsl,imx8qm-isi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: i.MX8QM Image Sensing Interface
> > +
> > +maintainers:
> > +  - Frank Li <Frank.Li@nxp.com>
> > +
> > +description:
> > +  The Image Sensing Interface (ISI) combines image processing pipelines with
> > +  DMA engines to process and capture frames originating from a variety of
> > +  sources. The inputs to the ISI go through Pixel Link interfaces, and their
> > +  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
> > +  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - fsl,imx8qm-isi
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 8
> > +
> > +  clock-names:
> > +    items:
> > +      - const: per0
> > +      - const: per1
> > +      - const: per2
> > +      - const: per3
> > +      - const: per4
> > +      - const: per5
> > +      - const: per6
> > +      - const: per7
> > +
> > +  interrupts:
> > +    maxItems: 8
> > +
> > +  power-domains:
> > +    maxItems: 8
>
> This surprises me. The reference manual does list 8 clocks and
> interrupts, but only 6 channels in the ISI section (for instance in
> 15.6.1.1.4). Which one is wrong ?

Support 6 input, 8 output.

"The crossbar is a 6 input 8 output multiplexer where each output port can
be configured to connect to any of the 6 inputs."

8 irq and clocks is for output dmac.

>
> > +
> > +  ports:
> > +    $ref: /schemas/graph.yaml#/properties/ports
> > +    properties:
> > +      port@2:
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: MIPI CSI-2 RX 0
> > +      port@3:
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: MIPI CSI-2 RX 1
> > +      port@4:
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: HDMI RX
>
> Figure 15-59 in the reference manual list MIPI CSI-2 RX 0 and RX 1 as
> connected to inputs 0 and 1 respectively.

Reference document should be wrong, I reference another internal document

0: display control 0
1: display control 1
2: csi2 rx0
3: csi2 rx1
4: hdmi rx

>
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - interrupts
> > +  - power-domains
> > +  - ports
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +    #include <dt-bindings/clock/imx8-clock.h>
> > +    #include <dt-bindings/clock/imx8-lpcg.h>
> > +    #include <dt-bindings/firmware/imx/rsrc.h>
> > +
> > +    image-controller@58100000 {
> > +        compatible = "fsl,imx8qm-isi";
> > +        reg = <0x58100000 0x90000>;
>
> The memory map in the reference manual lists the "Pixel DMA" region as
> ending at 0x5817ffff. Shouldn't the length of the region be 0x80000 ?

Yes, it should be 0x80000.

>
> > +        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
> > +        clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
> > +                 <&pdma1_lpcg IMX_LPCG_CLK_0>,
> > +                 <&pdma2_lpcg IMX_LPCG_CLK_0>,
> > +                 <&pdma3_lpcg IMX_LPCG_CLK_0>,
> > +                 <&pdma4_lpcg IMX_LPCG_CLK_0>,
> > +                 <&pdma5_lpcg IMX_LPCG_CLK_0>,
> > +                 <&pdma6_lpcg IMX_LPCG_CLK_0>,
> > +                 <&pdma7_lpcg IMX_LPCG_CLK_0>;
> > +        clock-names = "per0", "per1", "per2", "per3",
> > +                      "per4", "per5", "per6", "per7";
> > +        power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>,
> > +                        <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>,
> > +                        <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>,
> > +                        <&pd IMX_SC_R_ISI_CH6>, <&pd IMX_SC_R_ISI_CH7>;
> > +
> > +        ports {
> > +            #address-cells = <1>;
> > +            #size-cells = <0>;
> > +
> > +            port@2 {
> > +                reg = <2>;
> > +                endpoint {
> > +                    remote-endpoint = <&mipi_csi0_out>;
> > +                };
> > +            };
> > +        };
> > +    };
> > +...
> > diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml
> > new file mode 100644
> > index 0000000000000..818fea0e4679f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml
> > @@ -0,0 +1,103 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/media/fsl,imx8qxp-isi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: i.MX8QXP Image Sensing Interface
> > +
> > +maintainers:
> > +  - Frank Li <Frank.Li@nxp.com>
> > +
> > +description:
> > +  The Image Sensing Interface (ISI) combines image processing pipelines with
> > +  DMA engines to process and capture frames originating from a variety of
> > +  sources. The inputs to the ISI go through Pixel Link interfaces, and their
> > +  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
> > +  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - fsl,imx8qxp-isi
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 5
> > +
> > +  clock-names:
> > +    items:
> > +      - const: per0
> > +      - const: per4
> > +      - const: per5
> > +      - const: per6
> > +      - const: per7
> > +
> > +  interrupts:
> > +    maxItems: 5
> > +
> > +  power-domains:
> > +    maxItems: 5
>
> Here you have 5 channels, while the reference manual lists 8 interrupts
> and 6 channels in the ISI documentation.

QXP should only have 5 irqs and clocks. QM have 8, see above reply.

>
> > +
> > +  ports:
> > +    $ref: /schemas/graph.yaml#/properties/ports
> > +    properties:
> > +      port@2:
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: MIPI CSI-2 RX 0
> > +      port@6:
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: CSI-2 Parallel RX
>
> Table 15-6 in the reference manual lists the parallel port as input 4.

Reference manual is wrong.

>
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - interrupts
> > +  - power-domains
> > +  - ports
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +    #include <dt-bindings/clock/imx8-clock.h>
> > +    #include <dt-bindings/clock/imx8-lpcg.h>
> > +    #include <dt-bindings/firmware/imx/rsrc.h>
> > +
> > +    image-controller@58100000 {
> > +        compatible = "fsl,imx8qxp-isi";
> > +        reg = <0x58100000 0x90000>;
>
> Same comment here about the registers range.
>
> > +        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> > +                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
> > +        clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
> > +                 <&pdma4_lpcg IMX_LPCG_CLK_0>,
> > +                 <&pdma5_lpcg IMX_LPCG_CLK_0>,
> > +                 <&pdma6_lpcg IMX_LPCG_CLK_0>,
> > +                 <&pdma7_lpcg IMX_LPCG_CLK_0>;
> > +        clock-names = "per0", "per4", "per5", "per6", "per7";
> > +        power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH4>,
> > +                        <&pd IMX_SC_R_ISI_CH5>, <&pd IMX_SC_R_ISI_CH6>,
> > +                        <&pd IMX_SC_R_ISI_CH7>;
> > +
> > +        ports {
> > +            #address-cells = <1>;
> > +            #size-cells = <0>;
> > +
> > +            port@2 {
> > +                reg = <2>;
> > +                endpoint {
> > +                    remote-endpoint = <&mipi_csi0_out>;
> > +                };
> > +            };
> > +        };
> > +    };
> > +...
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 40d1b7ec30fde..f243257ef7653 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -17000,6 +17000,7 @@ NXP i.MX 8M ISI DRIVER
> >  M:	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> >  L:	linux-media@vger.kernel.org
> >  S:	Maintained
> > +F:	Documentation/devicetree/bindings/media/fsl,imx8*-isi.yaml
> >  F:	Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml
>
> Should nxp,imx8-isi.yaml be renamed to fsl,imx8-isi.yaml ?

Suppose yes, it should match one of compatible string name. This patch
have not touch nxp,imx8-isi.yaml. we may rename it later

Frank
>
> >  F:	drivers/media/platform/nxp/imx8-isi/
> >
>
> --
> Regards,
>
> Laurent Pinchart

Re: [PATCH v3 11/12] arm64: dts: imx8q: add linux,cma node for imx8qm-mek and imx8qxp-mek

[Frank Li]

On Thu, Mar 27, 2025 at 09:00:37PM +0200, Laurent Pinchart wrote:
> Hi Frank,
>
> Thank you for the patch.
>
> On Mon, Feb 10, 2025 at 03:59:30PM -0500, Frank Li wrote:
> > Add linux,cma node because some devices, such as camera, need big continue
> > physical memory.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > change from v1 to v3
> > - none
> > ---
> >  arch/arm64/boot/dts/freescale/imx8qm-mek.dts  | 9 +++++++++
> >  arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 8 ++++++++
> >  2 files changed, 17 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> > index 50fd3370f7dce..61ef00f4259e1 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> > @@ -113,6 +113,15 @@ dsp_vdev0buffer: memory@94300000 {
> >  			reg = <0 0x94300000 0 0x100000>;
> >  			no-map;
> >  		};
> > +
> > +		/* global autoconfigured region for contiguous allocations */
> > +		linux,cma {
> > +			compatible = "shared-dma-pool";
> > +			alloc-ranges = <0 0xc0000000 0 0x3c000000>;
> > +			size = <0 0x3c000000>;
> > +			linux,cma-default;
> > +			reusable;
> > +		};
>
> This is system memory. Why is it reserved here, hardcoding a specific
> use case in a board DT, instead of specifying an overall CMA size in the
> kernel configuration or through the kernel command line ?

Other imx boards dts also have linux,cma, which provide a default CMA size.
Generally we use one linux kernel image for difference boards. DTS should
provide default cma value for specific board.

kernel command line is more like debug methods. we don't want to depend on
uboot too much.

Frank

>
> >  	};
> >
> >  	lvds_backlight0: backlight-lvds0 {
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > index be79c793213a5..89c6516c5ba90 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > @@ -56,6 +56,14 @@ dsp_vdev0buffer: memory@94300000 {
> >  			reg = <0 0x94300000 0 0x100000>;
> >  			no-map;
> >  		};
> > +
> > +		linux,cma {
> > +			compatible = "shared-dma-pool";
> > +			alloc-ranges = <0 0xc0000000 0 0x3c000000>;
> > +			size = <0 0x3c000000>;
> > +			linux,cma-default;
> > +			reusable;
> > +		};
> >  	};
> >
> >  	reg_usdhc2_vmmc: usdhc2-vmmc {
>
> --
> Regards,
>
> Laurent Pinchart

Re: [PATCH v3 04/12] media: nxp: imx8-isi: Allow num_sources to be greater than num_sink

[Frank Li]

On Thu, Mar 27, 2025 at 03:02:29PM -0500, Adam Ford wrote:
> On Mon, Feb 10, 2025 at 3:01 PM Frank Li <Frank.Li@nxp.com> wrote:
> >
> > Allow num_sources (drvdata: num_channels) to be greater than num_sink
> > (drvdata: num_ports + 1).
> >
> > ISI support stream multiplexing, such as differentiates multiple cameras
> > from a single 2-lane MIPI input, or duplicates input stream into multiple
> > outputs. So num_channels may be greater than num_ports at some platform.
>
> Can you tell me which platforms support this?

iMX8QM.

>  Is this through
> virtual channels, or do you physically connect lanes 1 and 2 to one
> camera and lanes 3 and 4 to another?

Not like that.  for example, camera 0 as input0

channels 0 can covert input0 to RGB format to memory 1
channels 1 can scale down input0 to to memory 2

I think it most likely use for channel0 to preview image, channel1 to save
input to file on storage.

Frank
>
> adam
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > change from v1 to v3
> > - none
> > ---
> >  drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c b/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c
> > index 93a55c97cd173..ba5b2d3617a23 100644
> > --- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c
> > +++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-crossbar.c
> > @@ -188,11 +188,11 @@ static int mxc_isi_crossbar_init_state(struct v4l2_subdev *sd,
> >          * Create a 1:1 mapping between pixel link inputs and outputs to
> >          * pipelines by default.
> >          */
> > -       routes = kcalloc(xbar->num_sources, sizeof(*routes), GFP_KERNEL);
> > +       routes = kcalloc(xbar->num_sinks - 1, sizeof(*routes), GFP_KERNEL);
> >         if (!routes)
> >                 return -ENOMEM;
> >
> > -       for (i = 0; i < xbar->num_sources; ++i) {
> > +       for (i = 0; i < xbar->num_sinks - 1; ++i) {
> >                 struct v4l2_subdev_route *route = &routes[i];
> >
> >                 route->sink_pad = i;
> > @@ -200,7 +200,7 @@ static int mxc_isi_crossbar_init_state(struct v4l2_subdev *sd,
> >                 route->flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE;
> >         }
> >
> > -       routing.num_routes = xbar->num_sources;
> > +       routing.num_routes = xbar->num_sinks - 1;
> >         routing.routes = routes;
> >
> >         ret = __mxc_isi_crossbar_set_routing(sd, state, &routing);
> > @@ -453,7 +453,7 @@ int mxc_isi_crossbar_init(struct mxc_isi_dev *isi)
> >          * the memory input.
> >          */
> >         xbar->num_sinks = isi->pdata->num_ports + 1;
> > -       xbar->num_sources = isi->pdata->num_ports;
> > +       xbar->num_sources = isi->pdata->num_channels;
> >         num_pads = xbar->num_sinks + xbar->num_sources;
> >
> >         xbar->pads = kcalloc(num_pads, sizeof(*xbar->pads), GFP_KERNEL);
> >
> > --
> > 2.34.1
> >
> >

Re: [PATCH v3 07/12] media: imx8mq-mipi-csi2: Add imx8mq_plat_data for different compatible strings

[Laurent Pinchart]

On Mon, Feb 10, 2025 at 03:59:26PM -0500, Frank Li wrote:
> From: "Guoniu.zhou" <guoniu.zhou@nxp.com>
> 
> Introduce `imx8mq_plat_data` along with enable/disable callback operations
> to facilitate support for new chips. No functional changes.
> 
> Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> Change from v2 to v3
> - none
> change from v1 to v2
> - remove internal review tags
> ---
>  drivers/media/platform/nxp/imx8mq-mipi-csi2.c | 60 ++++++++++++++++++++-------
>  1 file changed, 46 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/media/platform/nxp/imx8mq-mipi-csi2.c b/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
> index 1f2657cf6e824..b5eae56d92f49 100644
> --- a/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
> +++ b/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
> @@ -62,6 +62,8 @@
>  #define CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL	0x188
>  #define CSI2RX_CFG_DISABLE_PAYLOAD_1		0x130
>  
> +struct csi_state;
> +
>  enum {
>  	ST_POWERED	= 1,
>  	ST_STREAMING	= 2,
> @@ -83,11 +85,11 @@ static const char * const imx8mq_mipi_csi_clk_id[CSI2_NUM_CLKS] = {
>  
>  #define CSI2_NUM_CLKS	ARRAY_SIZE(imx8mq_mipi_csi_clk_id)
>  
> -#define	GPR_CSI2_1_RX_ENABLE		BIT(13)
> -#define	GPR_CSI2_1_VID_INTFC_ENB	BIT(12)
> -#define	GPR_CSI2_1_HSEL			BIT(10)
> -#define	GPR_CSI2_1_CONT_CLK_MODE	BIT(8)
> -#define	GPR_CSI2_1_S_PRG_RXHS_SETTLE(x)	(((x) & 0x3f) << 2)
> +struct imx8mq_plat_data {
> +	const char *name;

The name is not used, drop it.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>


> +	int (*enable)(struct csi_state *state, u32 hs_settle);
> +	void (*disable)(struct csi_state *state);
> +};
>  
>  /*
>   * The send level configures the number of entries that must accumulate in
> @@ -106,6 +108,7 @@ static const char * const imx8mq_mipi_csi_clk_id[CSI2_NUM_CLKS] = {
>  
>  struct csi_state {
>  	struct device *dev;
> +	const struct imx8mq_plat_data *pdata;
>  	void __iomem *regs;
>  	struct clk_bulk_data clks[CSI2_NUM_CLKS];
>  	struct reset_control *rst;
> @@ -137,6 +140,35 @@ struct csi2_pix_format {
>  	u8 width;
>  };
>  
> +/* -----------------------------------------------------------------------------
> + * i.MX8MQ GPR
> + */
> +
> +#define	GPR_CSI2_1_RX_ENABLE		BIT(13)
> +#define	GPR_CSI2_1_VID_INTFC_ENB	BIT(12)
> +#define	GPR_CSI2_1_HSEL			BIT(10)
> +#define	GPR_CSI2_1_CONT_CLK_MODE	BIT(8)
> +#define	GPR_CSI2_1_S_PRG_RXHS_SETTLE(x)	(((x) & 0x3f) << 2)
> +
> +static int imx8mq_gpr_enable(struct csi_state *state, u32 hs_settle)
> +{
> +	regmap_update_bits(state->phy_gpr,
> +			   state->phy_gpr_reg,
> +			   0x3fff,
> +			   GPR_CSI2_1_RX_ENABLE |
> +			   GPR_CSI2_1_VID_INTFC_ENB |
> +			   GPR_CSI2_1_HSEL |
> +			   GPR_CSI2_1_CONT_CLK_MODE |
> +			   GPR_CSI2_1_S_PRG_RXHS_SETTLE(hs_settle));
> +
> +	return 0;
> +}
> +
> +static const struct imx8mq_plat_data imx8mq_data = {
> +	.name = "i.MX8MQ",
> +	.enable = imx8mq_gpr_enable,
> +};
> +
>  static const struct csi2_pix_format imx8mq_mipi_csi_formats[] = {
>  	/* RAW (Bayer and greyscale) formats. */
>  	{
> @@ -364,14 +396,9 @@ static int imx8mq_mipi_csi_start_stream(struct csi_state *state,
>  	if (ret)
>  		return ret;
>  
> -	regmap_update_bits(state->phy_gpr,
> -			   state->phy_gpr_reg,
> -			   0x3fff,
> -			   GPR_CSI2_1_RX_ENABLE |
> -			   GPR_CSI2_1_VID_INTFC_ENB |
> -			   GPR_CSI2_1_HSEL |
> -			   GPR_CSI2_1_CONT_CLK_MODE |
> -			   GPR_CSI2_1_S_PRG_RXHS_SETTLE(hs_settle));
> +	ret = state->pdata->enable(state, hs_settle);
> +	if (ret)
> +		return ret;
>  
>  	return 0;
>  }
> @@ -379,6 +406,9 @@ static int imx8mq_mipi_csi_start_stream(struct csi_state *state,
>  static void imx8mq_mipi_csi_stop_stream(struct csi_state *state)
>  {
>  	imx8mq_mipi_csi_write(state, CSI2RX_CFG_DISABLE_DATA_LANES, 0xf);
> +
> +	if (state->pdata->disable)
> +		state->pdata->disable(state);
>  }
>  
>  /* -----------------------------------------------------------------------------
> @@ -869,6 +899,8 @@ static int imx8mq_mipi_csi_probe(struct platform_device *pdev)
>  
>  	state->dev = dev;
>  
> +	state->pdata = of_device_get_match_data(dev);
> +
>  	ret = imx8mq_mipi_csi_parse_dt(state);
>  	if (ret < 0) {
>  		dev_err(dev, "Failed to parse device tree: %d\n", ret);
> @@ -946,7 +978,7 @@ static void imx8mq_mipi_csi_remove(struct platform_device *pdev)
>  }
>  
>  static const struct of_device_id imx8mq_mipi_csi_of_match[] = {
> -	{ .compatible = "fsl,imx8mq-mipi-csi2", },
> +	{ .compatible = "fsl,imx8mq-mipi-csi2", .data = &imx8mq_data },
>  	{ /* sentinel */ },
>  };
>  MODULE_DEVICE_TABLE(of, imx8mq_mipi_csi_of_match);

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 08/12] media: imx8mq-mipi-csi2: Add support for i.MX8QXP

[Laurent Pinchart]

Hi Frank,

Thank you for the patch.

On Mon, Feb 10, 2025 at 03:59:27PM -0500, Frank Li wrote:
> Add support for i.MX8QXP, which has a dedicated control and status register
> (csr) space. Enable obtaining the second register space and initializing

s/csr/CSR/

> PHY and link settings accordingly.
> 
> Add reset delay for i.MX8QXP. It needs a delay after toggle reset.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change from v2 to v3
> - use dedicate csr reg to control phy and link settings.
> 
> Change from v1 to v2
> - change 8QM go 8QXP, 8QM will failback to 8QXP to keep consisense with
> phy drivers
> ---
>  drivers/media/platform/nxp/imx8mq-mipi-csi2.c | 119 ++++++++++++++++++++++++++
>  1 file changed, 119 insertions(+)
> 
> diff --git a/drivers/media/platform/nxp/imx8mq-mipi-csi2.c b/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
> index b5eae56d92f49..788dabe5a0870 100644
> --- a/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
> +++ b/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
> @@ -89,6 +89,8 @@ struct imx8mq_plat_data {
>  	const char *name;
>  	int (*enable)(struct csi_state *state, u32 hs_settle);
>  	void (*disable)(struct csi_state *state);
> +	bool use_reg_csr: 1;

Drop :1.

> +	int reset_delay;

	unsigned int reset_delay_us;

as it can't be negative, and to have more clarity on the unit.

>  };
>  
>  /*
> @@ -169,6 +171,101 @@ static const struct imx8mq_plat_data imx8mq_data = {
>  	.enable = imx8mq_gpr_enable,
>  };
>  
> +/* -----------------------------------------------------------------------------
> + * i.MX8QXP
> + */
> +
> +#define CSI2SS_PL_CLK_INTERVAL_US		10000
> +#define CSI2SS_PL_CLK_TIMEOUT_US		100000
> +
> +#define CSI2SS_PLM_CTRL				0x0
> +#define CSI2SS_PLM_CTRL_PL_CLK_RUN		BIT(31)
> +#define CSI2SS_PLM_CTRL_VSYNC_OVERRIDE		BIT(9)
> +#define CSI2SS_PLM_CTRL_HSYNC_OVERRIDE		BIT(10)
> +#define CSI2SS_PLM_CTRL_VALID_OVERRIDE		BIT(11)
> +#define CSI2SS_PLM_CTRL_POLARITY_MASK		BIT(12)

#define CSI2SS_PLM_CTRL_POLARITY		BIT(12)

or POLARITY_HIGH if you prefer.

> +#define CSI2SS_PLM_CTRL_ENABLE_PL		BIT(0)

Sort the bits in numerical order, the middle ones are swapped.

> +
> +#define CSI2SS_PHY_CTRL				0x4
> +#define CSI2SS_PHY_CTRL_PD			BIT(22)
> +#define CSI2SS_PHY_CTRL_RTERM_SEL		BIT(21)
> +#define CSI2SS_PLM_CTRL_POLARITY		BIT(12)

PLM ? Bit 12 is documented as reserved in PHY_CTRL. Is this a bad copy &
paste ?

> +#define CSI2SS_PHY_CTRL_RX_HS_SETTLE_MASK	GENMASK(9, 4)
> +#define CSI2SS_PHY_CTRL_CONT_CLK_MODE		BIT(3)
> +#define CSI2SS_PHY_CTRL_DDRCLK_EN		BIT(2)
> +#define CSI2SS_PHY_CTRL_AUTO_PD_EN		BIT(1)
> +#define CSI2SS_PHY_CTRL_RX_ENABLE		BIT(0)
> +
> +#define CSI2SS_DATA_TYPE			0x38

According to the reference manual, the register is called
DATA_TYPE_DISABLE_BF.

> +#define CSI2SS_DATA_TYPE_MASK			GENMASK(23, 0)
> +
> +#define CSI2SS_CTRL_CLK_RESET			0x44
> +#define CSI2SS_CTRL_CLK_RESET_EN		BIT(0)
> +
> +static int imx8qxp_gpr_enable(struct csi_state *state, u32 hs_settle)
> +{
> +	int ret;
> +	u32 val;
> +
> +	/* clear format */

s/clear/Clear/

Same where applicable elsewhere.

> +	regmap_clear_bits(state->phy_gpr, CSI2SS_DATA_TYPE, CSI2SS_DATA_TYPE_MASK);
> +
> +	/* clear polarity */
> +	regmap_clear_bits(state->phy_gpr, CSI2SS_PLM_CTRL,
> +			  CSI2SS_PLM_CTRL_VSYNC_OVERRIDE |
> +			  CSI2SS_PLM_CTRL_HSYNC_OVERRIDE |
> +			  CSI2SS_PLM_CTRL_VALID_OVERRIDE |
> +			  CSI2SS_PLM_CTRL_POLARITY_MASK);

Given that you write the full register to 0 in imx8qxp_gpr_disable(), I
think you can use regmap_write() here.

> +
> +	regmap_update_bits(state->phy_gpr, CSI2SS_PHY_CTRL, CSI2SS_PHY_CTRL_RX_HS_SETTLE_MASK,
> +			   FIELD_PREP(CSI2SS_PHY_CTRL_RX_HS_SETTLE_MASK, hs_settle));

You need to include linux/bitfield.h for this. It can probably use
regmap_write() too, combining it with the next line.

> +
> +	regmap_set_bits(state->phy_gpr, CSI2SS_PHY_CTRL,
> +			CSI2SS_PHY_CTRL_RX_ENABLE | CSI2SS_PHY_CTRL_DDRCLK_EN |
> +			CSI2SS_PHY_CTRL_CONT_CLK_MODE | CSI2SS_PHY_CTRL_PD |
> +			CSI2SS_PHY_CTRL_RTERM_SEL | CSI2SS_PHY_CTRL_AUTO_PD_EN);
> +
> +	ret = regmap_read_poll_timeout(state->phy_gpr, CSI2SS_PLM_CTRL,
> +				       val, !(val & CSI2SS_PLM_CTRL_PL_CLK_RUN),
> +				       CSI2SS_PL_CLK_INTERVAL_US,
> +				       CSI2SS_PL_CLK_TIMEOUT_US);

How many iterations does this typically require ?

> +
> +	if (ret) {
> +		dev_err(state->dev, "Timeout waiting for Pixel-Link clock");
> +		return ret;
> +	}
> +
> +	/* Enable Pixel link Master*/

s/Master/Master /

> +	regmap_set_bits(state->phy_gpr, CSI2SS_PLM_CTRL,
> +			CSI2SS_PLM_CTRL_ENABLE_PL | CSI2SS_PLM_CTRL_VALID_OVERRIDE);
> +
> +	/* PHY Enable */
> +	regmap_clear_bits(state->phy_gpr, CSI2SS_PHY_CTRL,
> +			  CSI2SS_PHY_CTRL_PD | CSI2SS_PLM_CTRL_POLARITY);
> +
> +	/* Release Reset */
> +	regmap_set_bits(state->phy_gpr, CSI2SS_CTRL_CLK_RESET, CSI2SS_CTRL_CLK_RESET_EN);

No need to clear this bit in imx8qxp_gpr_disable() ?

> +
> +	return ret;
> +}
> +
> +static void imx8qxp_gpr_disable(struct csi_state *state)
> +{
> +	/* Disable Pixel Link */
> +	regmap_write(state->phy_gpr, CSI2SS_PLM_CTRL, 0x0);
> +
> +	/* Disable  PHY */

s/  / /

> +	regmap_write(state->phy_gpr, CSI2SS_PHY_CTRL, 0x0);
> +};
> +
> +static const struct imx8mq_plat_data imx8qxp_data = {
> +	.name = "i.MX8QXP",
> +	.enable = imx8qxp_gpr_enable,
> +	.disable = imx8qxp_gpr_disable,
> +	.use_reg_csr = 1,

s/1/true/

> +	.reset_delay = 10000,

Is this documented somewhere ?

> +};
> +
>  static const struct csi2_pix_format imx8mq_mipi_csi_formats[] = {
>  	/* RAW (Bayer and greyscale) formats. */
>  	{
> @@ -273,6 +370,8 @@ static int imx8mq_mipi_csi_sw_reset(struct csi_state *state)
>  		return ret;
>  	}
>  
> +	fsleep(state->pdata->reset_delay);
> +
>  	return 0;
>  }
>  
> @@ -860,6 +959,25 @@ static int imx8mq_mipi_csi_parse_dt(struct csi_state *state)
>  		return PTR_ERR(state->rst);
>  	}
>  
> +	if (state->pdata->use_reg_csr) {
> +		const struct regmap_config regmap_config = {
> +			.reg_bits = 32,
> +			.val_bits = 32,
> +			.reg_stride = 4,
> +		};
> +		void __iomem *base;
> +
> +		base = devm_platform_ioremap_resource(to_platform_device(dev), 1);
> +		if (IS_ERR(base))
> +			return dev_err_probe(dev, IS_ERR(base), "missed csr register\n");

s/missed csr/Missing CSR/

> +
> +		state->phy_gpr = devm_regmap_init_mmio(dev, base, &regmap_config);
> +		if (IS_ERR(state->phy_gpr))
> +			return dev_err_probe(dev, PTR_ERR(state->phy_gpr),
> +					     "Fail to init mmio regmap\n");

"Failed to init CSI MMIO regmap\n"

> +		return 0;
> +	}
> +
>  	ret = of_property_read_u32_array(np, "fsl,mipi-phy-gpr", out_val,
>  					 ARRAY_SIZE(out_val));
>  	if (ret) {
> @@ -979,6 +1097,7 @@ static void imx8mq_mipi_csi_remove(struct platform_device *pdev)
>  
>  static const struct of_device_id imx8mq_mipi_csi_of_match[] = {
>  	{ .compatible = "fsl,imx8mq-mipi-csi2", .data = &imx8mq_data },
> +	{ .compatible = "fsl,imx8qxp-mipi-csi2", .data = &imx8qxp_data },
>  	{ /* sentinel */ },
>  };
>  MODULE_DEVICE_TABLE(of, imx8mq_mipi_csi_of_match);

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 07/12] media: imx8mq-mipi-csi2: Add imx8mq_plat_data for different compatible strings

[Daniel Baluta]

On Mon, Feb 10, 2025 at 11:02 PM Frank Li <Frank.Li@nxp.com> wrote:
>
> From: "Guoniu.zhou" <guoniu.zhou@nxp.com>
>
> Introduce `imx8mq_plat_data` along with enable/disable callback operations
> to facilitate support for new chips. No functional changes.
>
> Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> Change from v2 to v3
> - none
> change from v1 to v2
> - remove internal review tags
> ---
>  drivers/media/platform/nxp/imx8mq-mipi-csi2.c | 60 ++++++++++++++++++++-------
>  1 file changed, 46 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/media/platform/nxp/imx8mq-mipi-csi2.c b/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
> index 1f2657cf6e824..b5eae56d92f49 100644
> --- a/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
> +++ b/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
> @@ -62,6 +62,8 @@
>  #define CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL       0x188
>  #define CSI2RX_CFG_DISABLE_PAYLOAD_1           0x130
>
> +struct csi_state;
> +
>  enum {
>         ST_POWERED      = 1,
>         ST_STREAMING    = 2,
> @@ -83,11 +85,11 @@ static const char * const imx8mq_mipi_csi_clk_id[CSI2_NUM_CLKS] = {
>
>  #define CSI2_NUM_CLKS  ARRAY_SIZE(imx8mq_mipi_csi_clk_id)
>
> -#define        GPR_CSI2_1_RX_ENABLE            BIT(13)
> -#define        GPR_CSI2_1_VID_INTFC_ENB        BIT(12)
> -#define        GPR_CSI2_1_HSEL                 BIT(10)
> -#define        GPR_CSI2_1_CONT_CLK_MODE        BIT(8)
> -#define        GPR_CSI2_1_S_PRG_RXHS_SETTLE(x) (((x) & 0x3f) << 2)
> +struct imx8mq_plat_data {
> +       const char *name;
> +       int (*enable)(struct csi_state *state, u32 hs_settle);
> +       void (*disable)(struct csi_state *state);
> +};
>
>  /*
>   * The send level configures the number of entries that must accumulate in
> @@ -106,6 +108,7 @@ static const char * const imx8mq_mipi_csi_clk_id[CSI2_NUM_CLKS] = {
>
>  struct csi_state {
>         struct device *dev;
> +       const struct imx8mq_plat_data *pdata;
>         void __iomem *regs;
>         struct clk_bulk_data clks[CSI2_NUM_CLKS];
>         struct reset_control *rst;
> @@ -137,6 +140,35 @@ struct csi2_pix_format {
>         u8 width;
>  };
>
> +/* -----------------------------------------------------------------------------

I would drop this line. It doesn't make code easier to read.
> + * i.MX8MQ GPR
> + */

Just say: /* i.MX8MQ GPR */

This pattern happens in a lot of places.

Re: [PATCH v3 07/12] media: imx8mq-mipi-csi2: Add imx8mq_plat_data for different compatible strings

[Laurent Pinchart]

On Fri, Mar 28, 2025 at 10:35:44AM +0200, Daniel Baluta wrote:
> On Mon, Feb 10, 2025 at 11:02 PM Frank Li <Frank.Li@nxp.com> wrote:
> >
> > From: "Guoniu.zhou" <guoniu.zhou@nxp.com>
> >
> > Introduce `imx8mq_plat_data` along with enable/disable callback operations
> > to facilitate support for new chips. No functional changes.
> >
> > Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > Change from v2 to v3
> > - none
> > change from v1 to v2
> > - remove internal review tags
> > ---
> >  drivers/media/platform/nxp/imx8mq-mipi-csi2.c | 60 ++++++++++++++++++++-------
> >  1 file changed, 46 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/media/platform/nxp/imx8mq-mipi-csi2.c b/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
> > index 1f2657cf6e824..b5eae56d92f49 100644
> > --- a/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
> > +++ b/drivers/media/platform/nxp/imx8mq-mipi-csi2.c
> > @@ -62,6 +62,8 @@
> >  #define CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL       0x188
> >  #define CSI2RX_CFG_DISABLE_PAYLOAD_1           0x130
> >
> > +struct csi_state;
> > +
> >  enum {
> >         ST_POWERED      = 1,
> >         ST_STREAMING    = 2,
> > @@ -83,11 +85,11 @@ static const char * const imx8mq_mipi_csi_clk_id[CSI2_NUM_CLKS] = {
> >
> >  #define CSI2_NUM_CLKS  ARRAY_SIZE(imx8mq_mipi_csi_clk_id)
> >
> > -#define        GPR_CSI2_1_RX_ENABLE            BIT(13)
> > -#define        GPR_CSI2_1_VID_INTFC_ENB        BIT(12)
> > -#define        GPR_CSI2_1_HSEL                 BIT(10)
> > -#define        GPR_CSI2_1_CONT_CLK_MODE        BIT(8)
> > -#define        GPR_CSI2_1_S_PRG_RXHS_SETTLE(x) (((x) & 0x3f) << 2)
> > +struct imx8mq_plat_data {
> > +       const char *name;
> > +       int (*enable)(struct csi_state *state, u32 hs_settle);
> > +       void (*disable)(struct csi_state *state);
> > +};
> >
> >  /*
> >   * The send level configures the number of entries that must accumulate in
> > @@ -106,6 +108,7 @@ static const char * const imx8mq_mipi_csi_clk_id[CSI2_NUM_CLKS] = {
> >
> >  struct csi_state {
> >         struct device *dev;
> > +       const struct imx8mq_plat_data *pdata;
> >         void __iomem *regs;
> >         struct clk_bulk_data clks[CSI2_NUM_CLKS];
> >         struct reset_control *rst;
> > @@ -137,6 +140,35 @@ struct csi2_pix_format {
> >         u8 width;
> >  };
> >
> > +/* -----------------------------------------------------------------------------
> 
> I would drop this line. It doesn't make code easier to read.

I personally find that clear section markers make the code easier to
read. It's a personal preference though, so I leave it to individual
driver maintainers, and aim for consistency within drivers.

> > + * i.MX8MQ GPR
> > + */
> 
> Just say: /* i.MX8MQ GPR */
> 
> This pattern happens in a lot of places.

-- 
Regards,

Laurent Pinchart

Re: [PATCH v3 05/12] media: imx8-isi: Add support for i.MX8QM and i.MX8QXP

[Frank Li]

On Thu, Mar 27, 2025 at 10:11:24PM +0200, Laurent Pinchart wrote:
> Hi Frank,
>
> Thank you for the patch.
>
> On Mon, Feb 10, 2025 at 03:59:24PM -0500, Frank Li wrote:
> > From: Robert Chiras <robert.chiras@nxp.com>
> >
> > Add compatibles and platform data for i.MX8QM and i.MX8QXP platforms.
> > There are 8 ISI channels on i.MX8QM while there are only 5 channels on
> > i.MX8QXP.
>
> There's a discrepancy between this series and the reference manuals.
> I've raised that issue in the review of the DT bindings, let's discuss
> it there. I'll skip that part of this patch for now.
>
> > Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > change from v2 to v3
> > - none
> >
> > change from v1 to v2
> > - remove intenal review tags
> > ---
> >  .../media/platform/nxp/imx8-isi/imx8-isi-core.c    | 47 ++++++++++++++++++++++
> >  .../media/platform/nxp/imx8-isi/imx8-isi-core.h    |  2 +
> >  2 files changed, 49 insertions(+)
> >
> > diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c
> > index 1e79b1211b603..a3237d76f7aa5 100644
> > --- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c
> > +++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.c
> > @@ -274,6 +274,25 @@ static const struct mxc_isi_set_thd mxc_imx8_isi_thd_v1 = {
> >  	.panic_set_thd_v = { .mask = 0xf0000, .offset = 16, .threshold = 0x7 },
> >  };
> >
> > +static const struct clk_bulk_data mxc_imx8qm_clks[] = {
> > +	{ .id = "per0" },
> > +	{ .id = "per1" },
> > +	{ .id = "per2" },
> > +	{ .id = "per3" },
> > +	{ .id = "per4" },
> > +	{ .id = "per5" },
> > +	{ .id = "per6" },
> > +	{ .id = "per7" },
> > +};
> > +
> > +static const struct clk_bulk_data mxc_imx8qxp_clks[] = {
> > +	{ .id = "per0" },
> > +	{ .id = "per4" },
> > +	{ .id = "per5" },
> > +	{ .id = "per6" },
> > +	{ .id = "per7" },
> > +};
> > +
> >  static const struct clk_bulk_data mxc_imx8mn_clks[] = {
> >  	{ .id = "axi" },
> >  	{ .id = "apb" },
> > @@ -334,6 +353,32 @@ static const struct mxc_isi_plat_data mxc_imx93_data = {
> >  	.has_36bit_dma		= false,
> >  };
> >
> > +static const struct mxc_isi_plat_data mxc_imx8qm_data = {
> > +	.model			= MXC_ISI_IMX8QM,
> > +	.num_ports		= 5,
> > +	.num_channels		= 8,
> > +	.reg_offset		= 0x10000,
> > +	.ier_reg		= &mxc_imx8_isi_ier_v1,
>
> Are you sure about this ? According to the reference manual, QXP seems
> to match mxc_imx8_isi_ier_v2, and QM doesn't seem to match either v1 or
> v2.

Thank you for found it. After check old code base and compared RM, you
are right, let me fix at next version.

Frank

>
> > +	.set_thd		= &mxc_imx8_isi_thd_v1,
> > +	.clks			= mxc_imx8qm_clks,
> > +	.num_clks		= ARRAY_SIZE(mxc_imx8qm_clks),
> > +	.buf_active_reverse	= true,
>
> I'll trust you on this value, I can't verify it.
>
> > +	.has_36bit_dma		= false,
> > +};
> > +
> > +static const struct mxc_isi_plat_data mxc_imx8qxp_data = {
> > +	.model			= MXC_ISI_IMX8QXP,
> > +	.num_ports		= 5,
> > +	.num_channels		= 5,
> > +	.reg_offset		= 0x10000,
> > +	.ier_reg		= &mxc_imx8_isi_ier_v1,
> > +	.set_thd		= &mxc_imx8_isi_thd_v1,
> > +	.clks			= mxc_imx8qxp_clks,
> > +	.num_clks		= ARRAY_SIZE(mxc_imx8qxp_clks),
> > +	.buf_active_reverse	= true,
> > +	.has_36bit_dma		= false,
> > +};
> > +
> >  /* -----------------------------------------------------------------------------
> >   * Power management
> >   */
> > @@ -541,6 +586,8 @@ static void mxc_isi_remove(struct platform_device *pdev)
> >  static const struct of_device_id mxc_isi_of_match[] = {
> >  	{ .compatible = "fsl,imx8mn-isi", .data = &mxc_imx8mn_data },
> >  	{ .compatible = "fsl,imx8mp-isi", .data = &mxc_imx8mp_data },
> > +	{ .compatible = "fsl,imx8qm-isi", .data = &mxc_imx8qm_data },
> > +	{ .compatible = "fsl,imx8qxp-isi", .data = &mxc_imx8qxp_data },
> >  	{ .compatible = "fsl,imx8ulp-isi", .data = &mxc_imx8ulp_data },
> >  	{ .compatible = "fsl,imx93-isi", .data = &mxc_imx93_data },
> >  	{ /* sentinel */ },
> > diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h
> > index 9c7fe9e5f941f..496cad3f9423d 100644
> > --- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h
> > +++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-core.h
> > @@ -158,6 +158,8 @@ struct mxc_gasket_ops {
> >  enum model {
> >  	MXC_ISI_IMX8MN,
> >  	MXC_ISI_IMX8MP,
> > +	MXC_ISI_IMX8QM,
> > +	MXC_ISI_IMX8QXP,
> >  	MXC_ISI_IMX8ULP,
> >  	MXC_ISI_IMX93,
> >  };
>
> --
> Regards,
>
> Laurent Pinchart

Re: [PATCH v3 03/12] media: dt-bindings: Add binding doc for i.MX8QXP and i.MX8QM ISI

[Laurent Pinchart]

Hi Frank,

On Thu, Mar 27, 2025 at 04:21:56PM -0400, Frank Li wrote:
> On Thu, Mar 27, 2025 at 08:44:25PM +0200, Laurent Pinchart wrote:
> > On Mon, Feb 10, 2025 at 03:59:22PM -0500, Frank Li wrote:
> > > Add binding documentation for i.MX8QXP and i.MX8QM ISI. The clock-names,
> > > power-domains, and ports differ significantly from the existing
> > > nxp,imx8-isi.yaml. Create a new file to avoid complex if-else branches.
> >
> > Mixed feelings about having different bindings files for what is
> > essentially the same IP, but I won't object.
> 
> Rob suggest split it at v1.
> 
> https://lore.kernel.org/all/20250203221659.GA130749-robh@kernel.org/
> 
> "I think this addition is borderline whether it should be its own schema
> doc. The if/then schemas are larger than the main part. The ports are
> not even the same."
> 
> >
> > > Add new file to MAINTAINERS.
> > >
> > > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > > ---
> > > change from v2 to v3
> > > - none
> > > change from v1 to v2
> > > - create new file for 8qm and 8qxp accroding rob's suggestion.
> > > ---
> > >  .../devicetree/bindings/media/fsl,imx8qm-isi.yaml  | 117 +++++++++++++++++++++
> > >  .../devicetree/bindings/media/fsl,imx8qxp-isi.yaml | 103 ++++++++++++++++++
> > >  MAINTAINERS                                        |   1 +
> > >  3 files changed, 221 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml
> > > new file mode 100644
> > > index 0000000000000..61c551673e2a4
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/media/fsl,imx8qm-isi.yaml
> > > @@ -0,0 +1,117 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/media/fsl,imx8qm-isi.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: i.MX8QM Image Sensing Interface
> > > +
> > > +maintainers:
> > > +  - Frank Li <Frank.Li@nxp.com>
> > > +
> > > +description:
> > > +  The Image Sensing Interface (ISI) combines image processing pipelines with
> > > +  DMA engines to process and capture frames originating from a variety of
> > > +  sources. The inputs to the ISI go through Pixel Link interfaces, and their
> > > +  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
> > > +  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
> > > +
> > > +properties:
> > > +  compatible:
> > > +    enum:
> > > +      - fsl,imx8qm-isi
> > > +
> > > +  reg:
> > > +    maxItems: 1
> > > +
> > > +  clocks:
> > > +    maxItems: 8
> > > +
> > > +  clock-names:
> > > +    items:
> > > +      - const: per0
> > > +      - const: per1
> > > +      - const: per2
> > > +      - const: per3
> > > +      - const: per4
> > > +      - const: per5
> > > +      - const: per6
> > > +      - const: per7
> > > +
> > > +  interrupts:
> > > +    maxItems: 8
> > > +
> > > +  power-domains:
> > > +    maxItems: 8
> >
> > This surprises me. The reference manual does list 8 clocks and
> > interrupts, but only 6 channels in the ISI section (for instance in
> > 15.6.1.1.4). Which one is wrong ?
> 
> Support 6 input, 8 output.
> 
> "The crossbar is a 6 input 8 output multiplexer where each output port can
> be configured to connect to any of the 6 inputs."

Which version of the reference manual are you looking at ? The latest
version I can find on the nxp.com website is "i.MX 8QuadMax Applications
Processor Reference Manual, Rev. 1.1, 05/2024", and it states on page 

    The crossbar is a 6 input, 6 output multiplexer where each output
    port can be configured to connect to any of the 6 inputs.

> 8 irq and clocks is for output dmac.
> 
> > > +
> > > +  ports:
> > > +    $ref: /schemas/graph.yaml#/properties/ports
> > > +    properties:
> > > +      port@2:
> > > +        $ref: /schemas/graph.yaml#/properties/port
> > > +        description: MIPI CSI-2 RX 0
> > > +      port@3:
> > > +        $ref: /schemas/graph.yaml#/properties/port
> > > +        description: MIPI CSI-2 RX 1
> > > +      port@4:
> > > +        $ref: /schemas/graph.yaml#/properties/port
> > > +        description: HDMI RX
> >
> > Figure 15-59 in the reference manual list MIPI CSI-2 RX 0 and RX 1 as
> > connected to inputs 0 and 1 respectively.
> 
> Reference document should be wrong, I reference another internal document

Ah, that answers my question above.

Could you report this issue, to get it fixed in the next version of the
reference manual ? Same for the QXP.

> 0: display control 0
> 1: display control 1
> 2: csi2 rx0
> 3: csi2 rx1
> 4: hdmi rx

I assume you've tested the driver, so I'll trust those values more than
the ones from the reference manual.

> > > +
> > > +required:
> > > +  - compatible
> > > +  - reg
> > > +  - clocks
> > > +  - clock-names
> > > +  - interrupts
> > > +  - power-domains
> > > +  - ports
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +    #include <dt-bindings/interrupt-controller/irq.h>
> > > +    #include <dt-bindings/clock/imx8-clock.h>
> > > +    #include <dt-bindings/clock/imx8-lpcg.h>
> > > +    #include <dt-bindings/firmware/imx/rsrc.h>
> > > +
> > > +    image-controller@58100000 {
> > > +        compatible = "fsl,imx8qm-isi";
> > > +        reg = <0x58100000 0x90000>;
> >
> > The memory map in the reference manual lists the "Pixel DMA" region as
> > ending at 0x5817ffff. Shouldn't the length of the region be 0x80000 ?
> 
> Yes, it should be 0x80000.
> 
> > > +        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> > > +                     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> > > +                     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
> > > +                     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
> > > +                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> > > +                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> > > +                     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> > > +                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
> > > +        clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
> > > +                 <&pdma1_lpcg IMX_LPCG_CLK_0>,
> > > +                 <&pdma2_lpcg IMX_LPCG_CLK_0>,
> > > +                 <&pdma3_lpcg IMX_LPCG_CLK_0>,
> > > +                 <&pdma4_lpcg IMX_LPCG_CLK_0>,
> > > +                 <&pdma5_lpcg IMX_LPCG_CLK_0>,
> > > +                 <&pdma6_lpcg IMX_LPCG_CLK_0>,
> > > +                 <&pdma7_lpcg IMX_LPCG_CLK_0>;
> > > +        clock-names = "per0", "per1", "per2", "per3",
> > > +                      "per4", "per5", "per6", "per7";
> > > +        power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>,
> > > +                        <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>,
> > > +                        <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>,
> > > +                        <&pd IMX_SC_R_ISI_CH6>, <&pd IMX_SC_R_ISI_CH7>;
> > > +
> > > +        ports {
> > > +            #address-cells = <1>;
> > > +            #size-cells = <0>;
> > > +
> > > +            port@2 {
> > > +                reg = <2>;
> > > +                endpoint {
> > > +                    remote-endpoint = <&mipi_csi0_out>;
> > > +                };
> > > +            };
> > > +        };
> > > +    };
> > > +...
> > > diff --git a/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml
> > > new file mode 100644
> > > index 0000000000000..818fea0e4679f
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/media/fsl,imx8qxp-isi.yaml
> > > @@ -0,0 +1,103 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/media/fsl,imx8qxp-isi.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: i.MX8QXP Image Sensing Interface
> > > +
> > > +maintainers:
> > > +  - Frank Li <Frank.Li@nxp.com>
> > > +
> > > +description:
> > > +  The Image Sensing Interface (ISI) combines image processing pipelines with
> > > +  DMA engines to process and capture frames originating from a variety of
> > > +  sources. The inputs to the ISI go through Pixel Link interfaces, and their
> > > +  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
> > > +  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
> > > +
> > > +properties:
> > > +  compatible:
> > > +    enum:
> > > +      - fsl,imx8qxp-isi
> > > +
> > > +  reg:
> > > +    maxItems: 1
> > > +
> > > +  clocks:
> > > +    maxItems: 5
> > > +
> > > +  clock-names:
> > > +    items:
> > > +      - const: per0
> > > +      - const: per4
> > > +      - const: per5
> > > +      - const: per6
> > > +      - const: per7
> > > +
> > > +  interrupts:
> > > +    maxItems: 5
> > > +
> > > +  power-domains:
> > > +    maxItems: 5
> >
> > Here you have 5 channels, while the reference manual lists 8 interrupts
> > and 6 channels in the ISI documentation.
> 
> QXP should only have 5 irqs and clocks. QM have 8, see above reply.
> 
> > > +
> > > +  ports:
> > > +    $ref: /schemas/graph.yaml#/properties/ports
> > > +    properties:
> > > +      port@2:
> > > +        $ref: /schemas/graph.yaml#/properties/port
> > > +        description: MIPI CSI-2 RX 0
> > > +      port@6:
> > > +        $ref: /schemas/graph.yaml#/properties/port
> > > +        description: CSI-2 Parallel RX
> >
> > Table 15-6 in the reference manual lists the parallel port as input 4.
> 
> Reference manual is wrong.
> 
> > > +
> > > +required:
> > > +  - compatible
> > > +  - reg
> > > +  - clocks
> > > +  - clock-names
> > > +  - interrupts
> > > +  - power-domains
> > > +  - ports
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +    #include <dt-bindings/interrupt-controller/irq.h>
> > > +    #include <dt-bindings/clock/imx8-clock.h>
> > > +    #include <dt-bindings/clock/imx8-lpcg.h>
> > > +    #include <dt-bindings/firmware/imx/rsrc.h>
> > > +
> > > +    image-controller@58100000 {
> > > +        compatible = "fsl,imx8qxp-isi";
> > > +        reg = <0x58100000 0x90000>;
> >
> > Same comment here about the registers range.
> >
> > > +        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> > > +                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> > > +                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> > > +                     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> > > +                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
> > > +        clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
> > > +                 <&pdma4_lpcg IMX_LPCG_CLK_0>,
> > > +                 <&pdma5_lpcg IMX_LPCG_CLK_0>,
> > > +                 <&pdma6_lpcg IMX_LPCG_CLK_0>,
> > > +                 <&pdma7_lpcg IMX_LPCG_CLK_0>;
> > > +        clock-names = "per0", "per4", "per5", "per6", "per7";
> > > +        power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH4>,
> > > +                        <&pd IMX_SC_R_ISI_CH5>, <&pd IMX_SC_R_ISI_CH6>,
> > > +                        <&pd IMX_SC_R_ISI_CH7>;
> > > +
> > > +        ports {
> > > +            #address-cells = <1>;
> > > +            #size-cells = <0>;
> > > +
> > > +            port@2 {
> > > +                reg = <2>;
> > > +                endpoint {
> > > +                    remote-endpoint = <&mipi_csi0_out>;
> > > +                };
> > > +            };
> > > +        };
> > > +    };
> > > +...
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index 40d1b7ec30fde..f243257ef7653 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -17000,6 +17000,7 @@ NXP i.MX 8M ISI DRIVER
> > >  M:	Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > >  L:	linux-media@vger.kernel.org
> > >  S:	Maintained
> > > +F:	Documentation/devicetree/bindings/media/fsl,imx8*-isi.yaml
> > >  F:	Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml
> >
> > Should nxp,imx8-isi.yaml be renamed to fsl,imx8-isi.yaml ?
> 
> Suppose yes, it should match one of compatible string name. This patch
> have not touch nxp,imx8-isi.yaml. we may rename it later
> 
> > >  F:	drivers/media/platform/nxp/imx8-isi/
> > >

-- 
Regards,

Laurent Pinchart