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Mon, 10 Feb 2025 01:20:16 -0800 (PST) Date: Mon, 10 Feb 2025 14:50:10 +0530 From: Manivannan Sadhasivam To: Krishna Chaitanya Chundru Cc: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Jingoo Han , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_vpernami@quicinc.com, mmareddy@quicinc.com Subject: Re: [PATCH v4 3/4] PCI: dwc: Reduce DT reads by allocating host bridge via DWC glue driver Message-ID: <20250210092010.nyt3n3tflipcrpt2@thinkpad> References: <20250207-ecam_v4-v4-0-94b5d5ec5017@oss.qualcomm.com> <20250207-ecam_v4-v4-3-94b5d5ec5017@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250207-ecam_v4-v4-3-94b5d5ec5017@oss.qualcomm.com> On Fri, Feb 07, 2025 at 04:58:58AM +0530, Krishna Chaitanya Chundru wrote: > dw_pcie_ecam_supported() needs to read bus-range to find the maximum > bus range value. The devm_pci_alloc_host_bridge() is already reading > bus range and storing it in host bridge.If devm_pci_alloc_host_bridge() What do you mean by 'storig in host bridge' here? Mention the exact structure name if that's what you are referring to. > moved to start of the controller probe, the dt reading can be avoided > and use values stored in the host bridge. Same here. > > Allow DWC glue drivers to allocate the host bridge, avoiding redundant > device tree reads primarily in dw_pcie_ecam_supported(). > This makes little sense to me. By this change, you essentially want DWC glue drivers to call devm_pci_alloc_host_bridge() just to get rid of one range parsing. I'd suggest to move dw_pcie_ecam_supported() inside dw_pcie_host_init() and call after devm_pci_alloc_host_bridge(). This way, the glue drivers can rely on DWC core to detect ECAM like other resources. And the API could be renamed as dw_pcie_ecam_detect() to match other resource detection like iATU, eDMA. More in patch 4. - Mani > Suggested-by: Bjorn Helgaas > Signed-off-by: Krishna Chaitanya Chundru > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 826ff9338646..a18cb1e411e4 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -484,8 +484,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > struct device *dev = pci->dev; > struct device_node *np = dev->of_node; > struct platform_device *pdev = to_platform_device(dev); > + struct pci_host_bridge *bridge = pp->bridge; > struct resource_entry *win; > - struct pci_host_bridge *bridge; > struct resource *res; > int ret; > > @@ -527,7 +527,12 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > if (!bridge) > return -ENOMEM; > > - pp->bridge = bridge; > + if (!pp->bridge) { > + bridge = devm_pci_alloc_host_bridge(dev, 0); > + if (!bridge) > + return -ENOMEM; > + pp->bridge = bridge; > + } > > /* Get the I/O range from DT */ > win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்