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Mon, 10 Feb 2025 01:22:46 -0800 (PST) Date: Mon, 10 Feb 2025 14:52:40 +0530 From: Manivannan Sadhasivam To: Krishna Chaitanya Chundru Cc: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Jingoo Han , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_vpernami@quicinc.com, mmareddy@quicinc.com Subject: Re: [PATCH v4 4/4] PCI: qcom: Enable ECAM feature Message-ID: <20250210092240.5b67fsdervb2tvxp@thinkpad> References: <20250207-ecam_v4-v4-0-94b5d5ec5017@oss.qualcomm.com> <20250207-ecam_v4-v4-4-94b5d5ec5017@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250207-ecam_v4-v4-4-94b5d5ec5017@oss.qualcomm.com> On Fri, Feb 07, 2025 at 04:58:59AM +0530, Krishna Chaitanya Chundru wrote: > The ELBI registers falls after the DBI space, PARF_SLV_DBI_ELBI register > gives us the offset from which ELBI starts. so use this offset and cfg > win to map these regions instead of doing the ioremap again. > > On root bus, we have only the root port. Any access other than that > should not go out of the link and should return all F's. Since the iATU > is configured for the buses which starts after root bus, block the > transactions starting from function 1 of the root bus to the end of > the root bus (i.e from dbi_base + 4kb to dbi_base + 1MB) from going > outside the link through ECAM blocker through PARF registers. > > Signed-off-by: Krishna Chaitanya Chundru > --- > drivers/pci/controller/dwc/pcie-qcom.c | 77 ++++++++++++++++++++++++++++++++-- > 1 file changed, 73 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index e4d3366ead1f..84297b308e7e 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -52,6 +52,7 @@ > #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 > #define PARF_Q2A_FLUSH 0x1ac > #define PARF_LTSSM 0x1b0 > +#define PARF_SLV_DBI_ELBI 0x1b4 > #define PARF_INT_ALL_STATUS 0x224 > #define PARF_INT_ALL_CLEAR 0x228 > #define PARF_INT_ALL_MASK 0x22c > @@ -61,6 +62,17 @@ > #define PARF_DBI_BASE_ADDR_V2_HI 0x354 > #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 > #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c > +#define PARF_BLOCK_SLV_AXI_WR_BASE 0x360 > +#define PARF_BLOCK_SLV_AXI_WR_BASE_HI 0x364 > +#define PARF_BLOCK_SLV_AXI_WR_LIMIT 0x368 > +#define PARF_BLOCK_SLV_AXI_WR_LIMIT_HI 0x36c > +#define PARF_BLOCK_SLV_AXI_RD_BASE 0x370 > +#define PARF_BLOCK_SLV_AXI_RD_BASE_HI 0x374 > +#define PARF_BLOCK_SLV_AXI_RD_LIMIT 0x378 > +#define PARF_BLOCK_SLV_AXI_RD_LIMIT_HI 0x37c > +#define PARF_ECAM_BASE 0x380 > +#define PARF_ECAM_BASE_HI 0x384 > + > #define PARF_NO_SNOOP_OVERIDE 0x3d4 > #define PARF_ATU_BASE_ADDR 0x634 > #define PARF_ATU_BASE_ADDR_HI 0x638 > @@ -84,6 +96,7 @@ > > /* PARF_SYS_CTRL register fields */ > #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) > +#define PCIE_ECAM_BLOCKER_EN BIT(26) > #define MST_WAKEUP_EN BIT(13) > #define SLV_WAKEUP_EN BIT(12) > #define MSTR_ACLK_CGC_DIS BIT(10) > @@ -294,6 +307,44 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) > usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); > } > > +static void qcom_pci_config_ecam(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct qcom_pcie *pcie = to_qcom_pcie(pci); > + u64 addr, addr_end; > + u32 val; > + > + /* Set the ECAM base */ > + writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE); > + writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI); > + > + /* > + * The only device on root bus is the Root Port. Any access other than that > + * should not go out of the link and should return all F's. Since the iATU > + * is configured for the buses which starts after root bus, block the transactions > + * starting from function 1 of the root bus to the end of the root bus (i.e from > + * dbi_base + 4kb to dbi_base + 1MB) from going outside the link. > + */ > + addr = pci->dbi_phys_addr + SZ_4K; > + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE); > + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI); > + > + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE); > + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI); > + > + addr_end = pci->dbi_phys_addr + SZ_1M - 1; > + > + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT); > + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI); > + > + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT); > + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI); > + > + val = readl_relaxed(pcie->parf + PARF_SYS_CTRL); > + val |= PCIE_ECAM_BLOCKER_EN; > + writel_relaxed(val, pcie->parf + PARF_SYS_CTRL); > +} > + > static int qcom_pcie_start_link(struct dw_pcie *pci) > { > struct qcom_pcie *pcie = to_qcom_pcie(pci); > @@ -303,6 +354,9 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) > qcom_pcie_common_set_16gt_lane_margining(pci); > } > > + if (pci->pp.ecam_mode) > + qcom_pci_config_ecam(&pci->pp); > + > /* Enable Link Training state machine */ > if (pcie->cfg->ops->ltssm_enable) > pcie->cfg->ops->ltssm_enable(pcie); > @@ -1233,6 +1287,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > struct qcom_pcie *pcie = to_qcom_pcie(pci); > + u16 offset; > int ret; > > qcom_ep_reset_assert(pcie); > @@ -1241,6 +1296,11 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) > if (ret) > return ret; > > + if (pp->ecam_mode) { > + offset = readl(pcie->parf + PARF_SLV_DBI_ELBI); > + pcie->elbi = pci->dbi_base + offset; > + } If you use the existing 'elbi' register offset defined in DT, you can just rely on the DWC core to call dw_pcie_ecam_supported() as I mentioned in my comment in patch 3. > + > ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); > if (ret) > goto err_deinit; > @@ -1615,6 +1675,13 @@ static int qcom_pcie_probe(struct platform_device *pdev) > pci->ops = &dw_pcie_ops; > pp = &pci->pp; > > + pp->bridge = devm_pci_alloc_host_bridge(dev, 0); > + if (!pp->bridge) { > + ret = -ENOMEM; > + goto err_pm_runtime_put; > + } > + This will also go away. > + pci->pp.ecam_mode = dw_pcie_ecam_supported(pp); This too. - Mani -- மணிவண்ணன் சதாசிவம்