* [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB
@ 2025-02-10 22:09 Alexander Sverdlin
2025-02-10 22:09 ` [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files Alexander Sverdlin
` (5 more replies)
0 siblings, 6 replies; 18+ messages in thread
From: Alexander Sverdlin @ 2025-02-10 22:09 UTC (permalink / raw)
To: soc
Cc: Alexander Sverdlin, Chen Wang, Inochi Amaoto, Lee Jones,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Catalin Marinas, Will Deacon, Arnd Bergmann, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Sebastian Reichel, devicetree,
Haylen Chu, linux-arm-kernel, linux-riscv, linux-pm,
Jisheng Zhang, Chao Wei
This series adds very basic support for Milk-V Duo Module 01 EVB [1] in
arm64 mode. The SoC (SG2000) is dual-arch, RiscV and ARM64, the latter has
been chosen because the upstream toolchain can be utilized.
Sophgo SG2000 seems to be a continuation of the Cvitek CV18xx series, same
peripherals with an addition of ARM64 core. Therefore it would be
beneficial not to copy-paste the peripherals' device-tree, but rather split
the most suitable riscv DT into ARCH-specific and peripherals parts and
just include the latter on the arm64 side.
This series adds the device-tree for Milk-V Duo Module 01 EVB, which
in turn contains Milk-V Duo Module 01 (separate .dtsi) on it, which has
SG2000 SoC inside (separate .dtsi).
This series has been tested with Sophgo-provided U-Boot binary [2]: it
boots from SD card; pinctrl, serial, GPIO drivers are functional (same
as for RiscV-based CV18xx SoCs).
Partial SoC documentation is available [3].
This series lacks the support of:
- USB
- Audio
- Ethernet
- WiFi
- Bluetooth
- eMMC
- Video
- "reboot" functionality
It would probably make sense that the series will go into ARM SOC tree.
Changelog:
v2:
- dropped all patches related to the new reboot driver and corresponding DT
and bindings;
- grouped DT-related and config-related patches together;
- added patch moving sophgo.yaml from riscv into soc (to share it with
ARM); added SG2000 SoC and Milk-V Duo Module 01 EVB into it;
- other changes are documented in the corresponding patches;
[1] https://milkv.io/docs/duo/getting-started/duo-module-01
[2] https://github.com/milkv-duo/duo-buildroot-sdk-v2/releases/
[3] https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf
Alexander Sverdlin (7):
riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi
files
dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add
SG2000
arm64: dts: sophgo: Add initial SG2000 SoC device tree
arm64: dts: sophgo: Add Duo Module 01
arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
arm64: Add SOPHGO SOC family Kconfig support
arm64: defconfig: Enable rudimentary Sophgo SG2000 support
.../{riscv => soc/sophgo}/sophgo.yaml | 7 +-
arch/arm64/Kconfig.platforms | 6 ++
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/sophgo/Makefile | 2 +
.../sophgo/sg2000-milkv-duo-module-01-evb.dts | 31 +++++++
.../sophgo/sg2000-milkv-duo-module-01.dtsi | 85 +++++++++++++++++
arch/arm64/boot/dts/sophgo/sg2000.dtsi | 75 +++++++++++++++
arch/arm64/configs/defconfig | 5 +
arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 64 ++++++++++---
arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 64 ++++++++++---
arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 +++++--------------
arch/riscv/boot/dts/sophgo/sg2002.dtsi | 64 ++++++++++---
14 files changed, 451 insertions(+), 103 deletions(-)
rename Documentation/devicetree/bindings/{riscv => soc/sophgo}/sophgo.yaml (80%)
create mode 100644 arch/arm64/boot/dts/sophgo/Makefile
create mode 100644 arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts
create mode 100644 arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi
create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
--
2.48.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files
2025-02-10 22:09 [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB Alexander Sverdlin
@ 2025-02-10 22:09 ` Alexander Sverdlin
2025-02-12 0:31 ` Inochi Amaoto
2025-02-10 22:09 ` [PATCH v2 2/7] dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 Alexander Sverdlin
` (4 subsequent siblings)
5 siblings, 1 reply; 18+ messages in thread
From: Alexander Sverdlin @ 2025-02-10 22:09 UTC (permalink / raw)
To: soc
Cc: Alexander Sverdlin, Chen Wang, Inochi Amaoto, linux-riscv,
devicetree, Haylen Chu, linux-arm-kernel, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Arnd Bergmann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jisheng Zhang, Chao Wei
Make the peripheral device tree re-usable on ARM64 platform by moving CPU
core and interrupt controllers' parts into the respective per-SoC .dtsi
files.
Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
into "plic" interrupt-controller numbering.
Have a nice refactoring side-effect that "plic" and "clint" "compatible"
property is not specified outside of the corresponding device itself.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
Changelog:
v2:
- instead of carving out peripherals' part, carve out ARCH-specifics (CPU
core, interrupt controllers) and spread them among 3 SoC .dtsi files which
included cv18xx.dtsi;
- define a label for the "soc" node and use it in the newly introduced DTs;
arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 64 ++++++++++++---
arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 64 ++++++++++++---
arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++++
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 ++++++----------------
arch/riscv/boot/dts/sophgo/sg2002.dtsi | 64 ++++++++++++---
6 files changed, 240 insertions(+), 102 deletions(-)
create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index aa1f5df100f0..eef2884b36f9 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
+#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
+
#include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
#include "cv18xx.dtsi"
@@ -14,22 +16,62 @@ memory@80000000 {
reg = <0x80000000 0x4000000>;
};
- soc {
- pinctrl: pinctrl@3001000 {
- compatible = "sophgo,cv1800b-pinctrl";
- reg = <0x03001000 0x1000>,
- <0x05027000 0x1000>;
- reg-names = "sys", "rtc";
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <25000000>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
};
-&plic {
- compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
-};
+&soc {
+ interrupt-parent = <&plic>;
+ dma-noncoherent;
-&clint {
- compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
+ pinctrl: pinctrl@3001000 {
+ compatible = "sophgo,cv1800b-pinctrl";
+ reg = <0x03001000 0x1000>,
+ <0x05027000 0x1000>;
+ reg-names = "sys", "rtc";
+ };
+
+ plic: interrupt-controller@70000000 {
+ compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
+ reg = <0x70000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <101>;
+ };
+
+ clint: timer@74000000 {
+ compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
+ reg = <0x74000000 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
};
&clk {
diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
index 8a1b95c5116b..54f7e229bcd8 100644
--- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
+#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
+
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
#include "cv18xx.dtsi"
@@ -16,22 +18,62 @@ memory@80000000 {
reg = <0x80000000 0x10000000>;
};
- soc {
- pinctrl: pinctrl@3001000 {
- compatible = "sophgo,cv1812h-pinctrl";
- reg = <0x03001000 0x1000>,
- <0x05027000 0x1000>;
- reg-names = "sys", "rtc";
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <25000000>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
};
-&plic {
- compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
-};
+&soc {
+ interrupt-parent = <&plic>;
+ dma-noncoherent;
-&clint {
- compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
+ pinctrl: pinctrl@3001000 {
+ compatible = "sophgo,cv1812h-pinctrl";
+ reg = <0x03001000 0x1000>,
+ <0x05027000 0x1000>;
+ reg-names = "sys", "rtc";
+ };
+
+ plic: interrupt-controller@70000000 {
+ compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
+ reg = <0x70000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <101>;
+ };
+
+ clint: timer@74000000 {
+ compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
+ reg = <0x74000000 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
};
&clk {
diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
index 5fd14dd1b14f..bbdb30653e9a 100644
--- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
@@ -11,7 +11,7 @@ soc {
emmc: mmc@4300000 {
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4300000 0x1000>;
- interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_EMMC>,
<&clk CLK_EMMC>;
clock-names = "core", "bus";
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
new file mode 100644
index 000000000000..a68d61131efb
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
+
+/ {
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <25000000>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+};
+
+&soc {
+ interrupt-parent = <&plic>;
+ dma-noncoherent;
+
+ plic: interrupt-controller@70000000 {
+ reg = <0x70000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <101>;
+ };
+
+ clint: timer@74000000 {
+ reg = <0x74000000 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
+};
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index c18822ec849f..62c1464a0490 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -12,47 +12,16 @@ / {
#address-cells = <1>;
#size-cells = <1>;
- cpus: cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- timebase-frequency = <25000000>;
-
- cpu0: cpu@0 {
- compatible = "thead,c906", "riscv";
- device_type = "cpu";
- reg = <0>;
- d-cache-block-size = <64>;
- d-cache-sets = <512>;
- d-cache-size = <65536>;
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <32768>;
- mmu-type = "riscv,sv39";
- riscv,isa = "rv64imafdc";
- riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm";
-
- cpu0_intc: interrupt-controller {
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
- };
-
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_25m";
#clock-cells = <0>;
};
- soc {
+ soc: soc {
compatible = "simple-bus";
- interrupt-parent = <&plic>;
#address-cells = <1>;
#size-cells = <1>;
- dma-noncoherent;
ranges;
clk: clock-controller@3002000 {
@@ -75,7 +44,7 @@ porta: gpio-controller@0 {
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
- interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -93,7 +62,7 @@ portb: gpio-controller@0 {
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
- interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -111,7 +80,7 @@ portc: gpio-controller@0 {
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
- interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -129,7 +98,7 @@ portd: gpio-controller@0 {
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
- interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -137,7 +106,7 @@ saradc: adc@30f0000 {
compatible = "sophgo,cv1800b-saradc";
reg = <0x030f0000 0x1000>;
clocks = <&clk CLK_SARADC>;
- interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -162,7 +131,7 @@ i2c0: i2c@4000000 {
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
clock-names = "ref", "pclk";
- interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -173,7 +142,7 @@ i2c1: i2c@4010000 {
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
clock-names = "ref", "pclk";
- interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -184,7 +153,7 @@ i2c2: i2c@4020000 {
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
clock-names = "ref", "pclk";
- interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -195,7 +164,7 @@ i2c3: i2c@4030000 {
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
clock-names = "ref", "pclk";
- interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -206,14 +175,14 @@ i2c4: i2c@4040000 {
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
clock-names = "ref", "pclk";
- interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart0: serial@4140000 {
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
- interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
@@ -224,7 +193,7 @@ uart0: serial@4140000 {
uart1: serial@4150000 {
compatible = "snps,dw-apb-uart";
reg = <0x04150000 0x100>;
- interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
@@ -235,7 +204,7 @@ uart1: serial@4150000 {
uart2: serial@4160000 {
compatible = "snps,dw-apb-uart";
reg = <0x04160000 0x100>;
- interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
@@ -246,7 +215,7 @@ uart2: serial@4160000 {
uart3: serial@4170000 {
compatible = "snps,dw-apb-uart";
reg = <0x04170000 0x100>;
- interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
@@ -261,7 +230,7 @@ spi0: spi@4180000 {
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
clock-names = "ssi_clk", "pclk";
- interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -272,7 +241,7 @@ spi1: spi@4190000 {
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
clock-names = "ssi_clk", "pclk";
- interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -283,7 +252,7 @@ spi2: spi@41a0000 {
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
clock-names = "ssi_clk", "pclk";
- interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -294,14 +263,14 @@ spi3: spi@41b0000 {
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
clock-names = "ssi_clk", "pclk";
- interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart4: serial@41c0000 {
compatible = "snps,dw-apb-uart";
reg = <0x041c0000 0x100>;
- interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
@@ -312,7 +281,7 @@ uart4: serial@41c0000 {
sdhci0: mmc@4310000 {
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4310000 0x1000>;
- interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_SD0>,
<&clk CLK_SD0>;
clock-names = "core", "bus";
@@ -322,7 +291,7 @@ sdhci0: mmc@4310000 {
sdhci1: mmc@4320000 {
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4320000 0x1000>;
- interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_SD1>,
<&clk CLK_SD1>;
clock-names = "core", "bus";
@@ -332,7 +301,7 @@ sdhci1: mmc@4320000 {
dmac: dma-controller@4330000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x04330000 0x1000>;
- interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
clock-names = "core-clk", "cfgr-clk";
#dma-cells = <1>;
@@ -344,19 +313,5 @@ dmac: dma-controller@4330000 {
snps,data-width = <4>;
status = "disabled";
};
-
- plic: interrupt-controller@70000000 {
- reg = <0x70000000 0x4000000>;
- interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- riscv,ndev = <101>;
- };
-
- clint: timer@74000000 {
- reg = <0x74000000 0x10000>;
- interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
- };
};
};
diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
index 7f79de33163c..732d0e72cf13 100644
--- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
*/
+#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
+
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-sg2002.h>
#include "cv18xx.dtsi"
@@ -16,22 +18,62 @@ memory@80000000 {
reg = <0x80000000 0x10000000>;
};
- soc {
- pinctrl: pinctrl@3001000 {
- compatible = "sophgo,sg2002-pinctrl";
- reg = <0x03001000 0x1000>,
- <0x05027000 0x1000>;
- reg-names = "sys", "rtc";
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <25000000>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
};
};
};
-&plic {
- compatible = "sophgo,sg2002-plic", "thead,c900-plic";
-};
+&soc {
+ interrupt-parent = <&plic>;
+ dma-noncoherent;
-&clint {
- compatible = "sophgo,sg2002-clint", "thead,c900-clint";
+ pinctrl: pinctrl@3001000 {
+ compatible = "sophgo,sg2002-pinctrl";
+ reg = <0x03001000 0x1000>,
+ <0x05027000 0x1000>;
+ reg-names = "sys", "rtc";
+ };
+
+ plic: interrupt-controller@70000000 {
+ compatible = "sophgo,sg2002-plic", "thead,c900-plic";
+ reg = <0x70000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <101>;
+ };
+
+ clint: timer@74000000 {
+ compatible = "sophgo,sg2002-clint", "thead,c900-clint";
+ reg = <0x74000000 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
};
&clk {
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 2/7] dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
2025-02-10 22:09 [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB Alexander Sverdlin
2025-02-10 22:09 ` [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files Alexander Sverdlin
@ 2025-02-10 22:09 ` Alexander Sverdlin
2025-02-11 1:29 ` Chen Wang
2025-02-11 18:18 ` Conor Dooley
2025-02-10 22:09 ` [PATCH v2 3/7] arm64: dts: sophgo: Add initial SG2000 SoC device tree Alexander Sverdlin
` (3 subsequent siblings)
5 siblings, 2 replies; 18+ messages in thread
From: Alexander Sverdlin @ 2025-02-10 22:09 UTC (permalink / raw)
To: soc
Cc: Alexander Sverdlin, Jisheng Zhang, Chao Wei, Chen Wang,
Inochi Amaoto, linux-pm, linux-riscv, devicetree, Haylen Chu,
linux-arm-kernel, Sebastian Reichel, Arnd Bergmann, Philipp Zabel,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Move sophgo.yaml from riscv into soc/sophgo so that it can be shared for
all SoCs containing ARM cores as well. This already applies to SG2002.
Add SG2000 SoC, Milk-V Duo Module 01 and Milk-V Module 01 EVB.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
.../devicetree/bindings/{riscv => soc/sophgo}/sophgo.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
rename Documentation/devicetree/bindings/{riscv => soc/sophgo}/sophgo.yaml (80%)
diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml
similarity index 80%
rename from Documentation/devicetree/bindings/riscv/sophgo.yaml
rename to Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml
index a14cb10ff3f0..5d73d0ccc547 100644
--- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
+++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
+$id: http://devicetree.org/schemas/soc/sophgo/sophgo.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo SoC-based boards
@@ -26,6 +26,11 @@ properties:
- enum:
- sophgo,huashan-pi
- const: sophgo,cv1812h
+ - items:
+ - enum:
+ - milkv,duo-module-01-evb
+ - const: milkv,duo-module-01
+ - const: sophgo,sg2000
- items:
- enum:
- sipeed,licheerv-nano-b
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 3/7] arm64: dts: sophgo: Add initial SG2000 SoC device tree
2025-02-10 22:09 [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB Alexander Sverdlin
2025-02-10 22:09 ` [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files Alexander Sverdlin
2025-02-10 22:09 ` [PATCH v2 2/7] dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 Alexander Sverdlin
@ 2025-02-10 22:09 ` Alexander Sverdlin
2025-02-10 22:09 ` [PATCH v2 4/7] arm64: dts: sophgo: Add Duo Module 01 Alexander Sverdlin
` (2 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Alexander Sverdlin @ 2025-02-10 22:09 UTC (permalink / raw)
To: soc
Cc: Alexander Sverdlin, Jisheng Zhang, Chao Wei, Chen Wang,
Inochi Amaoto, linux-riscv, devicetree, Haylen Chu,
linux-arm-kernel, Arnd Bergmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV).
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
Changelog:
v2:
- relocated "memory" node according to DT coding style;
- moved GIC node into "soc";
- referring "soc" by label;
arch/arm64/boot/dts/sophgo/sg2000.dtsi | 75 ++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
new file mode 100644
index 000000000000..98c8d300347c
--- /dev/null
+++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr)
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <riscv/sophgo/cv18xx.dtsi>
+#include <riscv/sophgo/cv181x.dtsi>
+
+/ {
+ compatible = "sophgo,sg2000";
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x20000>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512MiB */
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ always-on;
+ clock-frequency = <25000000>;
+ };
+};
+
+&soc {
+ gic: interrupt-controller@1f01000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x01f01000 0x1000>,
+ <0x01f02000 0x2000>;
+ };
+
+ pinctrl: pinctrl@3001000 {
+ compatible = "sophgo,sg2000-pinctrl";
+ reg = <0x03001000 0x1000>,
+ <0x05027000 0x1000>;
+ reg-names = "sys", "rtc";
+ };
+};
+
+&clk {
+ compatible = "sophgo,sg2000-clk";
+};
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 4/7] arm64: dts: sophgo: Add Duo Module 01
2025-02-10 22:09 [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB Alexander Sverdlin
` (2 preceding siblings ...)
2025-02-10 22:09 ` [PATCH v2 3/7] arm64: dts: sophgo: Add initial SG2000 SoC device tree Alexander Sverdlin
@ 2025-02-10 22:09 ` Alexander Sverdlin
2025-02-10 22:09 ` [PATCH v2 5/7] arm64: dts: sophgo: Add Duo Module 01 Evaluation Board Alexander Sverdlin
2025-02-11 10:50 ` [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB Conor Dooley
5 siblings, 0 replies; 18+ messages in thread
From: Alexander Sverdlin @ 2025-02-10 22:09 UTC (permalink / raw)
To: soc
Cc: Alexander Sverdlin, Jisheng Zhang, Chao Wei, Chen Wang,
Inochi Amaoto, linux-riscv, devicetree, Haylen Chu,
linux-arm-kernel, Arnd Bergmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
The Duo Module 01 is a compact module with integrated SG2000,
WI-FI6/BTDM5.4, and eMMC.
Add only support for UART and SDHCI.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
Changelog:
v2:
- sorted all nodes according to DT coding style;
- added "compatible" property;
- renamed the new .dtsi not to use underscores;
- added status = "okay" instead of deleting it;
.../sophgo/sg2000-milkv-duo-module-01.dtsi | 85 +++++++++++++++++++
1 file changed, 85 insertions(+)
create mode 100644 arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi
diff --git a/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi b/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi
new file mode 100644
index 000000000000..bb52cdad990a
--- /dev/null
+++ b/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include <dt-bindings/pinctrl/pinctrl-sg2000.h>
+#include "sg2000.dtsi"
+
+/ {
+ model = "Milk-V Duo Module 01";
+ compatible = "milkv,duo-module-01", "sophgo,sg2000";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ };
+};
+
+&osc {
+ clock-frequency = <25000000>;
+};
+
+&pinctrl {
+ sdhci0_cfg: sdhci0-cfg {
+ sdhci0-cd-pins {
+ pinmux = <PINMUX(PIN_SD0_CD, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <10800>;
+ power-source = <3300>;
+ };
+
+ sdhci0-clk-pins {
+ pinmux = <PINMUX(PIN_SD0_CLK, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <16100>;
+ power-source = <3300>;
+ };
+
+ sdhci0-cmd-pins {
+ pinmux = <PINMUX(PIN_SD0_CMD, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <10800>;
+ power-source = <3300>;
+ };
+
+ sdhci0-data-pins {
+ pinmux = <PINMUX(PIN_SD0_D0, 0)>,
+ <PINMUX(PIN_SD0_D1, 0)>,
+ <PINMUX(PIN_SD0_D2, 0)>,
+ <PINMUX(PIN_SD0_D3, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <10800>;
+ power-source = <3300>;
+ };
+ };
+
+ uart0_cfg: uart0-cfg {
+ uart0-pins {
+ pinmux = <PINMUX(PIN_UART0_TX, 0)>,
+ <PINMUX(PIN_UART0_RX, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <10800>;
+ power-source = <3300>;
+ };
+ };
+};
+
+&emmc {
+ bus-width = <4>;
+ no-1-8-v;
+ cap-mmc-hw-reset;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+/* Wi-Fi */
+&sdhci1 {
+ bus-width = <4>;
+ cap-sdio-irq;
+ no-mmc;
+ no-sd;
+ non-removable;
+};
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2 5/7] arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
2025-02-10 22:09 [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB Alexander Sverdlin
` (3 preceding siblings ...)
2025-02-10 22:09 ` [PATCH v2 4/7] arm64: dts: sophgo: Add Duo Module 01 Alexander Sverdlin
@ 2025-02-10 22:09 ` Alexander Sverdlin
2025-02-11 10:50 ` [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB Conor Dooley
5 siblings, 0 replies; 18+ messages in thread
From: Alexander Sverdlin @ 2025-02-10 22:09 UTC (permalink / raw)
To: soc
Cc: Alexander Sverdlin, Jisheng Zhang, Chao Wei, Chen Wang,
Inochi Amaoto, linux-riscv, devicetree, Haylen Chu,
linux-arm-kernel, Arnd Bergmann, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Duo Module 01 Evaluation Board contains Sophgo Duo Module 01
SMD SoM, Ethernet+USB switch, microSD slot, etc...
Add only support for UART0 (console) and microSD slot.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
---
Changelog:
v2:
- sorted all nodes according to DT coding style;
- added "compatible" property;
- renamed the new .dts not to use underscores;
- added status = "okay" instead of deleting it;
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/sophgo/Makefile | 2 ++
.../sophgo/sg2000-milkv-duo-module-01-evb.dts | 31 +++++++++++++++++++
3 files changed, 34 insertions(+)
create mode 100644 arch/arm64/boot/dts/sophgo/Makefile
create mode 100644 arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 79b73a21ddc2..3a32b157ac8c 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -28,6 +28,7 @@ subdir-y += realtek
subdir-y += renesas
subdir-y += rockchip
subdir-y += socionext
+subdir-y += sophgo
subdir-y += sprd
subdir-y += st
subdir-y += synaptics
diff --git a/arch/arm64/boot/dts/sophgo/Makefile b/arch/arm64/boot/dts/sophgo/Makefile
new file mode 100644
index 000000000000..94f52cd7d994
--- /dev/null
+++ b/arch/arm64/boot/dts/sophgo/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SOPHGO) += sg2000-milkv-duo-module-01-evb.dtb
diff --git a/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts b/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts
new file mode 100644
index 000000000000..b1f8a5787861
--- /dev/null
+++ b/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "sg2000-milkv-duo-module-01.dtsi"
+
+/ {
+ model = "Milk-V Duo Module 01 Evaluation Board";
+ compatible = "milkv,duo-module-01-evb", "milkv,duo-module-01", "sophgo,sg2000";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_cfg>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sdhci0 {
+ bus-width = <4>;
+ no-1-8-v;
+ no-mmc;
+ no-sdio;
+ disable-wp;
+ pinctrl-0 = <&sdhci0_cfg>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
2.48.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
2025-02-10 22:09 ` [PATCH v2 2/7] dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 Alexander Sverdlin
@ 2025-02-11 1:29 ` Chen Wang
2025-02-11 18:18 ` Conor Dooley
1 sibling, 0 replies; 18+ messages in thread
From: Chen Wang @ 2025-02-11 1:29 UTC (permalink / raw)
To: Alexander Sverdlin, soc
Cc: Jisheng Zhang, Chao Wei, Inochi Amaoto, linux-pm, linux-riscv,
devicetree, Haylen Chu, linux-arm-kernel, Sebastian Reichel,
Arnd Bergmann, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
On 2025/2/11 6:09, Alexander Sverdlin wrote:
> Move sophgo.yaml from riscv into soc/sophgo so that it can be shared for
> all SoCs containing ARM cores as well. This already applies to SG2002.
>
> Add SG2000 SoC, Milk-V Duo Module 01 and Milk-V Module 01 EVB.
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
> ---
> .../devicetree/bindings/{riscv => soc/sophgo}/sophgo.yaml | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
> rename Documentation/devicetree/bindings/{riscv => soc/sophgo}/sophgo.yaml (80%)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml
> similarity index 80%
> rename from Documentation/devicetree/bindings/riscv/sophgo.yaml
> rename to Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml
> index a14cb10ff3f0..5d73d0ccc547 100644
> --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
> +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> %YAML 1.2
> ---
> -$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
> +$id: http://devicetree.org/schemas/soc/sophgo/sophgo.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> title: Sophgo SoC-based boards
> @@ -26,6 +26,11 @@ properties:
> - enum:
> - sophgo,huashan-pi
> - const: sophgo,cv1812h
> + - items:
> + - enum:
> + - milkv,duo-module-01-evb
> + - const: milkv,duo-module-01
> + - const: sophgo,sg2000
> - items:
> - enum:
> - sipeed,licheerv-nano-b
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB
2025-02-10 22:09 [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB Alexander Sverdlin
` (4 preceding siblings ...)
2025-02-10 22:09 ` [PATCH v2 5/7] arm64: dts: sophgo: Add Duo Module 01 Evaluation Board Alexander Sverdlin
@ 2025-02-11 10:50 ` Conor Dooley
2025-02-11 12:43 ` Alexander Sverdlin
5 siblings, 1 reply; 18+ messages in thread
From: Conor Dooley @ 2025-02-11 10:50 UTC (permalink / raw)
To: Alexander Sverdlin
Cc: soc, Chen Wang, Inochi Amaoto, Lee Jones, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Catalin Marinas,
Will Deacon, Arnd Bergmann, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Sebastian Reichel, devicetree, Haylen Chu,
linux-arm-kernel, linux-riscv, linux-pm, Jisheng Zhang, Chao Wei
[-- Attachment #1: Type: text/plain, Size: 1776 bytes --]
On Mon, Feb 10, 2025 at 11:09:40PM +0100, Alexander Sverdlin wrote:
> This series adds very basic support for Milk-V Duo Module 01 EVB [1] in
> arm64 mode. The SoC (SG2000) is dual-arch, RiscV and ARM64, the latter has
> been chosen because the upstream toolchain can be utilized.
> .../{riscv => soc/sophgo}/sophgo.yaml | 7 +-
> arch/arm64/Kconfig.platforms | 6 ++
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/sophgo/Makefile | 2 +
I'd expect this to be maintained alongside the riscv support, how come
there's no maintainers entry change here?
> .../sophgo/sg2000-milkv-duo-module-01-evb.dts | 31 +++++++
> .../sophgo/sg2000-milkv-duo-module-01.dtsi | 85 +++++++++++++++++
> arch/arm64/boot/dts/sophgo/sg2000.dtsi | 75 +++++++++++++++
> arch/arm64/configs/defconfig | 5 +
> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 64 ++++++++++---
> arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 64 ++++++++++---
> arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
> arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++
> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 +++++--------------
> arch/riscv/boot/dts/sophgo/sg2002.dtsi | 64 ++++++++++---
> 14 files changed, 451 insertions(+), 103 deletions(-)
> rename Documentation/devicetree/bindings/{riscv => soc/sophgo}/sophgo.yaml (80%)
> create mode 100644 arch/arm64/boot/dts/sophgo/Makefile
> create mode 100644 arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts
> create mode 100644 arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi
> create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB
2025-02-11 10:50 ` [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB Conor Dooley
@ 2025-02-11 12:43 ` Alexander Sverdlin
2025-02-11 13:48 ` Conor Dooley
0 siblings, 1 reply; 18+ messages in thread
From: Alexander Sverdlin @ 2025-02-11 12:43 UTC (permalink / raw)
To: Conor Dooley
Cc: soc, Chen Wang, Inochi Amaoto, Lee Jones, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Catalin Marinas,
Will Deacon, Arnd Bergmann, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Sebastian Reichel, devicetree, Haylen Chu,
linux-arm-kernel, linux-riscv, linux-pm, Jisheng Zhang, Chao Wei
Hi Conor!
On Tue, 2025-02-11 at 10:50 +0000, Conor Dooley wrote:
> On Mon, Feb 10, 2025 at 11:09:40PM +0100, Alexander Sverdlin wrote:
> > This series adds very basic support for Milk-V Duo Module 01 EVB [1] in
> > arm64 mode. The SoC (SG2000) is dual-arch, RiscV and ARM64, the latter has
> > been chosen because the upstream toolchain can be utilized.
>
> > .../{riscv => soc/sophgo}/sophgo.yaml | 7 +-
> > arch/arm64/Kconfig.platforms | 6 ++
> > arch/arm64/boot/dts/Makefile | 1 +
> > arch/arm64/boot/dts/sophgo/Makefile | 2 +
>
> I'd expect this to be maintained alongside the riscv support, how come
> there's no maintainers entry change here?
MAINTAINERS file has "K: sophgo" entry already, I suppose new files will
fall into this category? That's why I've ignored this specific checkpatch warning
in all patches. Am I wrong?
> > .../sophgo/sg2000-milkv-duo-module-01-evb.dts | 31 +++++++
> > .../sophgo/sg2000-milkv-duo-module-01.dtsi | 85 +++++++++++++++++
> > arch/arm64/boot/dts/sophgo/sg2000.dtsi | 75 +++++++++++++++
> > arch/arm64/configs/defconfig | 5 +
> > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 64 ++++++++++---
> > arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 64 ++++++++++---
> > arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
> > arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++
> > arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 +++++--------------
> > arch/riscv/boot/dts/sophgo/sg2002.dtsi | 64 ++++++++++---
> > 14 files changed, 451 insertions(+), 103 deletions(-)
> > rename Documentation/devicetree/bindings/{riscv => soc/sophgo}/sophgo.yaml (80%)
> > create mode 100644 arch/arm64/boot/dts/sophgo/Makefile
> > create mode 100644 arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts
> > create mode 100644 arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi
> > create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
> > create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
--
Alexander Sverdlin.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB
2025-02-11 12:43 ` Alexander Sverdlin
@ 2025-02-11 13:48 ` Conor Dooley
0 siblings, 0 replies; 18+ messages in thread
From: Conor Dooley @ 2025-02-11 13:48 UTC (permalink / raw)
To: Alexander Sverdlin
Cc: soc, Chen Wang, Inochi Amaoto, Lee Jones, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Catalin Marinas,
Will Deacon, Arnd Bergmann, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Sebastian Reichel, devicetree, Haylen Chu,
linux-arm-kernel, linux-riscv, linux-pm, Jisheng Zhang, Chao Wei
[-- Attachment #1: Type: text/plain, Size: 2349 bytes --]
On Tue, Feb 11, 2025 at 01:43:31PM +0100, Alexander Sverdlin wrote:
> Hi Conor!
>
> On Tue, 2025-02-11 at 10:50 +0000, Conor Dooley wrote:
> > On Mon, Feb 10, 2025 at 11:09:40PM +0100, Alexander Sverdlin wrote:
> > > This series adds very basic support for Milk-V Duo Module 01 EVB [1] in
> > > arm64 mode. The SoC (SG2000) is dual-arch, RiscV and ARM64, the latter has
> > > been chosen because the upstream toolchain can be utilized.
> >
> > > .../{riscv => soc/sophgo}/sophgo.yaml | 7 +-
> > > arch/arm64/Kconfig.platforms | 6 ++
> > > arch/arm64/boot/dts/Makefile | 1 +
> > > arch/arm64/boot/dts/sophgo/Makefile | 2 +
> >
> > I'd expect this to be maintained alongside the riscv support, how come
> > there's no maintainers entry change here?
>
> MAINTAINERS file has "K: sophgo" entry already, I suppose new files will
> fall into this category? That's why I've ignored this specific checkpatch warning
> in all patches. Am I wrong?
Ah, I didn't realise.
>
> > > .../sophgo/sg2000-milkv-duo-module-01-evb.dts | 31 +++++++
> > > .../sophgo/sg2000-milkv-duo-module-01.dtsi | 85 +++++++++++++++++
> > > arch/arm64/boot/dts/sophgo/sg2000.dtsi | 75 +++++++++++++++
> > > arch/arm64/configs/defconfig | 5 +
> > > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 64 ++++++++++---
> > > arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 64 ++++++++++---
> > > arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
> > > arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++
> > > arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 +++++--------------
> > > arch/riscv/boot/dts/sophgo/sg2002.dtsi | 64 ++++++++++---
> > > 14 files changed, 451 insertions(+), 103 deletions(-)
> > > rename Documentation/devicetree/bindings/{riscv => soc/sophgo}/sophgo.yaml (80%)
> > > create mode 100644 arch/arm64/boot/dts/sophgo/Makefile
> > > create mode 100644 arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01-evb.dts
> > > create mode 100644 arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-module-01.dtsi
> > > create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
> > > create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
>
> --
> Alexander Sverdlin.
>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
2025-02-10 22:09 ` [PATCH v2 2/7] dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 Alexander Sverdlin
2025-02-11 1:29 ` Chen Wang
@ 2025-02-11 18:18 ` Conor Dooley
1 sibling, 0 replies; 18+ messages in thread
From: Conor Dooley @ 2025-02-11 18:18 UTC (permalink / raw)
To: Alexander Sverdlin
Cc: soc, Jisheng Zhang, Chao Wei, Chen Wang, Inochi Amaoto, linux-pm,
linux-riscv, devicetree, Haylen Chu, linux-arm-kernel,
Sebastian Reichel, Arnd Bergmann, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
[-- Attachment #1: Type: text/plain, Size: 1823 bytes --]
On Mon, Feb 10, 2025 at 11:09:42PM +0100, Alexander Sverdlin wrote:
> Move sophgo.yaml from riscv into soc/sophgo so that it can be shared for
> all SoCs containing ARM cores as well. This already applies to SG2002.
>
> Add SG2000 SoC, Milk-V Duo Module 01 and Milk-V Module 01 EVB.
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../devicetree/bindings/{riscv => soc/sophgo}/sophgo.yaml | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
> rename Documentation/devicetree/bindings/{riscv => soc/sophgo}/sophgo.yaml (80%)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml
> similarity index 80%
> rename from Documentation/devicetree/bindings/riscv/sophgo.yaml
> rename to Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml
> index a14cb10ff3f0..5d73d0ccc547 100644
> --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
> +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> %YAML 1.2
> ---
> -$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
> +$id: http://devicetree.org/schemas/soc/sophgo/sophgo.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> title: Sophgo SoC-based boards
> @@ -26,6 +26,11 @@ properties:
> - enum:
> - sophgo,huashan-pi
> - const: sophgo,cv1812h
> + - items:
> + - enum:
> + - milkv,duo-module-01-evb
> + - const: milkv,duo-module-01
> + - const: sophgo,sg2000
> - items:
> - enum:
> - sipeed,licheerv-nano-b
> --
> 2.48.1
>
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files
2025-02-10 22:09 ` [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files Alexander Sverdlin
@ 2025-02-12 0:31 ` Inochi Amaoto
2025-02-12 9:26 ` Alexander Sverdlin
0 siblings, 1 reply; 18+ messages in thread
From: Inochi Amaoto @ 2025-02-12 0:31 UTC (permalink / raw)
To: Alexander Sverdlin, soc
Cc: Chen Wang, Inochi Amaoto, linux-riscv, devicetree, Haylen Chu,
linux-arm-kernel, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Arnd Bergmann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jisheng Zhang, Chao Wei, Inochi Amaoto
On Mon, Feb 10, 2025 at 11:09:41PM +0100, Alexander Sverdlin wrote:
> Make the peripheral device tree re-usable on ARM64 platform by moving CPU
> core and interrupt controllers' parts into the respective per-SoC .dtsi
> files.
>
> Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
> into "plic" interrupt-controller numbering.
>
> Have a nice refactoring side-effect that "plic" and "clint" "compatible"
> property is not specified outside of the corresponding device itself.
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
> Changelog:
> v2:
> - instead of carving out peripherals' part, carve out ARCH-specifics (CPU
> core, interrupt controllers) and spread them among 3 SoC .dtsi files which
> included cv18xx.dtsi;
> - define a label for the "soc" node and use it in the newly introduced DTs;
>
> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 64 ++++++++++++---
> arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 64 ++++++++++++---
> arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
> arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++++
> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 ++++++----------------
> arch/riscv/boot/dts/sophgo/sg2002.dtsi | 64 ++++++++++++---
> 6 files changed, 240 insertions(+), 102 deletions(-)
> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index aa1f5df100f0..eef2884b36f9 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -3,6 +3,8 @@
> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> */
>
> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> +
> #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
> #include "cv18xx.dtsi"
>
> @@ -14,22 +16,62 @@ memory@80000000 {
> reg = <0x80000000 0x4000000>;
> };
>
> - soc {
> - pinctrl: pinctrl@3001000 {
> - compatible = "sophgo,cv1800b-pinctrl";
> - reg = <0x03001000 0x1000>,
> - <0x05027000 0x1000>;
> - reg-names = "sys", "rtc";
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <25000000>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <512>;
> + d-cache-size = <65536>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> + "zifencei", "zihpm";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> };
> };
> };
Make all soc definition include the common cpu file.
Not just copy it.
>
> -&plic {
> - compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> -};
> +&soc {
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
>
> -&clint {
> - compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> + pinctrl: pinctrl@3001000 {
> + compatible = "sophgo,cv1800b-pinctrl";
> + reg = <0x03001000 0x1000>,
> + <0x05027000 0x1000>;
> + reg-names = "sys", "rtc";
> + };
> +
> + plic: interrupt-controller@70000000 {
> + compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> + reg = <0x70000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <101>;
> + };
> +
> + clint: timer@74000000 {
> + compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> + reg = <0x74000000 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> + };
> };
>
> &clk {
> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> index 8a1b95c5116b..54f7e229bcd8 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> @@ -3,6 +3,8 @@
> * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> */
>
> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> +
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
> #include "cv18xx.dtsi"
> @@ -16,22 +18,62 @@ memory@80000000 {
> reg = <0x80000000 0x10000000>;
> };
>
> - soc {
> - pinctrl: pinctrl@3001000 {
> - compatible = "sophgo,cv1812h-pinctrl";
> - reg = <0x03001000 0x1000>,
> - <0x05027000 0x1000>;
> - reg-names = "sys", "rtc";
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <25000000>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <512>;
> + d-cache-size = <65536>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> + "zifencei", "zihpm";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> };
> };
> };
>
> -&plic {
> - compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> -};
> +&soc {
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
>
> -&clint {
> - compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> + pinctrl: pinctrl@3001000 {
> + compatible = "sophgo,cv1812h-pinctrl";
> + reg = <0x03001000 0x1000>,
> + <0x05027000 0x1000>;
> + reg-names = "sys", "rtc";
> + };
> +
> + plic: interrupt-controller@70000000 {
> + compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> + reg = <0x70000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <101>;
> + };
> +
> + clint: timer@74000000 {
> + compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> + reg = <0x74000000 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> + };
> };
>
> &clk {
> diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> index 5fd14dd1b14f..bbdb30653e9a 100644
> --- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> @@ -11,7 +11,7 @@ soc {
> emmc: mmc@4300000 {
> compatible = "sophgo,cv1800b-dwcmshc";
> reg = <0x4300000 0x1000>;
> - interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_AXI4_EMMC>,
> <&clk CLK_EMMC>;
> clock-names = "core", "bus";
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
> new file mode 100644
> index 000000000000..a68d61131efb
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
> @@ -0,0 +1,57 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> + */
> +
> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> +
> +/ {
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <25000000>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <512>;
> + d-cache-size = <65536>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> + "zifencei", "zihpm";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +};
> +
> +&soc {
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
> +
> + plic: interrupt-controller@70000000 {
> + reg = <0x70000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <101>;
> + };
> +
> + clint: timer@74000000 {
> + reg = <0x74000000 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> + };
> +};
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index c18822ec849f..62c1464a0490 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -12,47 +12,16 @@ / {
> #address-cells = <1>;
> #size-cells = <1>;
>
> - cpus: cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - timebase-frequency = <25000000>;
> -
> - cpu0: cpu@0 {
> - compatible = "thead,c906", "riscv";
> - device_type = "cpu";
> - reg = <0>;
> - d-cache-block-size = <64>;
> - d-cache-sets = <512>;
> - d-cache-size = <65536>;
> - i-cache-block-size = <64>;
> - i-cache-sets = <128>;
> - i-cache-size = <32768>;
> - mmu-type = "riscv,sv39";
> - riscv,isa = "rv64imafdc";
> - riscv,isa-base = "rv64i";
> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm";
> -
> - cpu0_intc: interrupt-controller {
> - compatible = "riscv,cpu-intc";
> - interrupt-controller;
> - #interrupt-cells = <1>;
> - };
> - };
> - };
> -
> osc: oscillator {
> compatible = "fixed-clock";
> clock-output-names = "osc_25m";
> #clock-cells = <0>;
> };
>
> - soc {
> + soc: soc {
> compatible = "simple-bus";
> - interrupt-parent = <&plic>;
> #address-cells = <1>;
> #size-cells = <1>;
> - dma-noncoherent;
> ranges;
>
> clk: clock-controller@3002000 {
> @@ -75,7 +44,7 @@ porta: gpio-controller@0 {
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> - interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>;
> };
> };
>
> @@ -93,7 +62,7 @@ portb: gpio-controller@0 {
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> - interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
> };
> };
>
> @@ -111,7 +80,7 @@ portc: gpio-controller@0 {
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
> };
> };
>
> @@ -129,7 +98,7 @@ portd: gpio-controller@0 {
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> - interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>;
> };
> };
>
> @@ -137,7 +106,7 @@ saradc: adc@30f0000 {
> compatible = "sophgo,cv1800b-saradc";
> reg = <0x030f0000 0x1000>;
> clocks = <&clk CLK_SARADC>;
> - interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> status = "disabled";
> @@ -162,7 +131,7 @@ i2c0: i2c@4000000 {
> #size-cells = <0>;
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
> clock-names = "ref", "pclk";
> - interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -173,7 +142,7 @@ i2c1: i2c@4010000 {
> #size-cells = <0>;
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
> clock-names = "ref", "pclk";
> - interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -184,7 +153,7 @@ i2c2: i2c@4020000 {
> #size-cells = <0>;
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
> clock-names = "ref", "pclk";
> - interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -195,7 +164,7 @@ i2c3: i2c@4030000 {
> #size-cells = <0>;
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
> clock-names = "ref", "pclk";
> - interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -206,14 +175,14 @@ i2c4: i2c@4040000 {
> #size-cells = <0>;
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
> clock-names = "ref", "pclk";
> - interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> uart0: serial@4140000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x04140000 0x100>;
> - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> @@ -224,7 +193,7 @@ uart0: serial@4140000 {
> uart1: serial@4150000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x04150000 0x100>;
> - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> @@ -235,7 +204,7 @@ uart1: serial@4150000 {
> uart2: serial@4160000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x04160000 0x100>;
> - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> @@ -246,7 +215,7 @@ uart2: serial@4160000 {
> uart3: serial@4170000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x04170000 0x100>;
> - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> @@ -261,7 +230,7 @@ spi0: spi@4180000 {
> #size-cells = <0>;
> clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
> clock-names = "ssi_clk", "pclk";
> - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -272,7 +241,7 @@ spi1: spi@4190000 {
> #size-cells = <0>;
> clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
> clock-names = "ssi_clk", "pclk";
> - interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -283,7 +252,7 @@ spi2: spi@41a0000 {
> #size-cells = <0>;
> clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
> clock-names = "ssi_clk", "pclk";
> - interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -294,14 +263,14 @@ spi3: spi@41b0000 {
> #size-cells = <0>;
> clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
> clock-names = "ssi_clk", "pclk";
> - interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> uart4: serial@41c0000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x041c0000 0x100>;
> - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> @@ -312,7 +281,7 @@ uart4: serial@41c0000 {
> sdhci0: mmc@4310000 {
> compatible = "sophgo,cv1800b-dwcmshc";
> reg = <0x4310000 0x1000>;
> - interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_AXI4_SD0>,
> <&clk CLK_SD0>;
> clock-names = "core", "bus";
> @@ -322,7 +291,7 @@ sdhci0: mmc@4310000 {
> sdhci1: mmc@4320000 {
> compatible = "sophgo,cv1800b-dwcmshc";
> reg = <0x4320000 0x1000>;
> - interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_AXI4_SD1>,
> <&clk CLK_SD1>;
> clock-names = "core", "bus";
> @@ -332,7 +301,7 @@ sdhci1: mmc@4320000 {
> dmac: dma-controller@4330000 {
> compatible = "snps,axi-dma-1.01a";
> reg = <0x04330000 0x1000>;
> - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
> clock-names = "core-clk", "cfgr-clk";
> #dma-cells = <1>;
> @@ -344,19 +313,5 @@ dmac: dma-controller@4330000 {
> snps,data-width = <4>;
> status = "disabled";
> };
> -
> - plic: interrupt-controller@70000000 {
> - reg = <0x70000000 0x4000000>;
> - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> - interrupt-controller;
> - #address-cells = <0>;
> - #interrupt-cells = <2>;
> - riscv,ndev = <101>;
> - };
> -
> - clint: timer@74000000 {
> - reg = <0x74000000 0x10000>;
> - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> - };
> };
> };
> diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
> index 7f79de33163c..732d0e72cf13 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
> @@ -3,6 +3,8 @@
> * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> */
>
> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> +
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/pinctrl-sg2002.h>
> #include "cv18xx.dtsi"
> @@ -16,22 +18,62 @@ memory@80000000 {
> reg = <0x80000000 0x10000000>;
> };
>
> - soc {
> - pinctrl: pinctrl@3001000 {
> - compatible = "sophgo,sg2002-pinctrl";
> - reg = <0x03001000 0x1000>,
> - <0x05027000 0x1000>;
> - reg-names = "sys", "rtc";
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <25000000>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <512>;
> + d-cache-size = <65536>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> + "zifencei", "zihpm";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> };
> };
> };
>
> -&plic {
> - compatible = "sophgo,sg2002-plic", "thead,c900-plic";
> -};
> +&soc {
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
>
> -&clint {
> - compatible = "sophgo,sg2002-clint", "thead,c900-clint";
> + pinctrl: pinctrl@3001000 {
> + compatible = "sophgo,sg2002-pinctrl";
> + reg = <0x03001000 0x1000>,
> + <0x05027000 0x1000>;
> + reg-names = "sys", "rtc";
> + };
> +
> + plic: interrupt-controller@70000000 {
> + compatible = "sophgo,sg2002-plic", "thead,c900-plic";
> + reg = <0x70000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <101>;
> + };
> +
> + clint: timer@74000000 {
> + compatible = "sophgo,sg2002-clint", "thead,c900-clint";
> + reg = <0x74000000 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> + };
> };
>
> &clk {
> --
> 2.48.1
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files
2025-02-12 0:31 ` Inochi Amaoto
@ 2025-02-12 9:26 ` Alexander Sverdlin
2025-02-12 16:46 ` Krzysztof Kozlowski
0 siblings, 1 reply; 18+ messages in thread
From: Alexander Sverdlin @ 2025-02-12 9:26 UTC (permalink / raw)
To: Inochi Amaoto, soc
Cc: Chen Wang, Inochi Amaoto, linux-riscv, devicetree, Haylen Chu,
linux-arm-kernel, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Arnd Bergmann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jisheng Zhang, Chao Wei
Hi Inochi, Krzysztof,
On Wed, 2025-02-12 at 08:31 +0800, Inochi Amaoto wrote:
> On Mon, Feb 10, 2025 at 11:09:41PM +0100, Alexander Sverdlin wrote:
> > Make the peripheral device tree re-usable on ARM64 platform by moving CPU
> > core and interrupt controllers' parts into the respective per-SoC .dtsi
> > files.
> >
> > Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
> > into "plic" interrupt-controller numbering.
> >
> > Have a nice refactoring side-effect that "plic" and "clint" "compatible"
> > property is not specified outside of the corresponding device itself.
> >
> > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> > ---
> > Changelog:
> > v2:
> > - instead of carving out peripherals' part, carve out ARCH-specifics (CPU
> > core, interrupt controllers) and spread them among 3 SoC .dtsi files which
> > included cv18xx.dtsi;
> > - define a label for the "soc" node and use it in the newly introduced DTs;
> >
> > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 64 ++++++++++++---
> > arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 64 ++++++++++++---
> > arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
> > arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++++
> > arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 ++++++----------------
> > arch/riscv/boot/dts/sophgo/sg2002.dtsi | 64 ++++++++++++---
> > 6 files changed, 240 insertions(+), 102 deletions(-)
> > create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > index aa1f5df100f0..eef2884b36f9 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > @@ -3,6 +3,8 @@
> > * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> > */
> >
> > +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> > +
> > #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
> > #include "cv18xx.dtsi"
> >
> > @@ -14,22 +16,62 @@ memory@80000000 {
> > reg = <0x80000000 0x4000000>;
> > };
> >
>
> > - soc {
> > - pinctrl: pinctrl@3001000 {
> > - compatible = "sophgo,cv1800b-pinctrl";
> > - reg = <0x03001000 0x1000>,
> > - <0x05027000 0x1000>;
> > - reg-names = "sys", "rtc";
>
>
> > + cpus: cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <25000000>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "thead,c906", "riscv";
> > + device_type = "cpu";
> > + reg = <0>;
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <512>;
> > + d-cache-size = <65536>;
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <32768>;
> > + mmu-type = "riscv,sv39";
> > + riscv,isa = "rv64imafdc";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > + "zifencei", "zihpm";
> > +
> > + cpu0_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > };
> > };
> > };
>
> Make all soc definition include the common cpu file.
> Not just copy it.
I was acting according to Krzysztof's suggestion:
https://lore.kernel.org/soc/d3ba0ea5-0491-42d5-a18e-64cf21df696c@kernel.org/
Krzysztof, I can name the file cv18xx-cpu-intc.dtsi and pack CPU core + interrupt
controllers into it. Would it make sense?
> >
> > -&plic {
> > - compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> > -};
> > +&soc {
> > + interrupt-parent = <&plic>;
> > + dma-noncoherent;
> >
> > -&clint {
> > - compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> > + pinctrl: pinctrl@3001000 {
> > + compatible = "sophgo,cv1800b-pinctrl";
> > + reg = <0x03001000 0x1000>,
> > + <0x05027000 0x1000>;
> > + reg-names = "sys", "rtc";
> > + };
> > +
> > + plic: interrupt-controller@70000000 {
> > + compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> > + reg = <0x70000000 0x4000000>;
> > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> > + interrupt-controller;
> > + #address-cells = <0>;
> > + #interrupt-cells = <2>;
> > + riscv,ndev = <101>;
> > + };
> > +
> > + clint: timer@74000000 {
> > + compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> > + reg = <0x74000000 0x10000>;
> > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> > + };
> > };
> >
> > &clk {
> > diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> > index 8a1b95c5116b..54f7e229bcd8 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> > @@ -3,6 +3,8 @@
> > * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> > */
> >
> > +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> > +
> > #include <dt-bindings/interrupt-controller/irq.h>
> > #include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
> > #include "cv18xx.dtsi"
> > @@ -16,22 +18,62 @@ memory@80000000 {
> > reg = <0x80000000 0x10000000>;
> > };
> >
> > - soc {
> > - pinctrl: pinctrl@3001000 {
> > - compatible = "sophgo,cv1812h-pinctrl";
> > - reg = <0x03001000 0x1000>,
> > - <0x05027000 0x1000>;
> > - reg-names = "sys", "rtc";
> > + cpus: cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <25000000>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "thead,c906", "riscv";
> > + device_type = "cpu";
> > + reg = <0>;
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <512>;
> > + d-cache-size = <65536>;
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <32768>;
> > + mmu-type = "riscv,sv39";
> > + riscv,isa = "rv64imafdc";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > + "zifencei", "zihpm";
> > +
> > + cpu0_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > };
> > };
> > };
> >
> > -&plic {
> > - compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> > -};
> > +&soc {
> > + interrupt-parent = <&plic>;
> > + dma-noncoherent;
> >
> > -&clint {
> > - compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> > + pinctrl: pinctrl@3001000 {
> > + compatible = "sophgo,cv1812h-pinctrl";
> > + reg = <0x03001000 0x1000>,
> > + <0x05027000 0x1000>;
> > + reg-names = "sys", "rtc";
> > + };
> > +
> > + plic: interrupt-controller@70000000 {
> > + compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> > + reg = <0x70000000 0x4000000>;
> > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> > + interrupt-controller;
> > + #address-cells = <0>;
> > + #interrupt-cells = <2>;
> > + riscv,ndev = <101>;
> > + };
> > +
> > + clint: timer@74000000 {
> > + compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> > + reg = <0x74000000 0x10000>;
> > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> > + };
> > };
> >
> > &clk {
> > diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> > index 5fd14dd1b14f..bbdb30653e9a 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> > @@ -11,7 +11,7 @@ soc {
> > emmc: mmc@4300000 {
> > compatible = "sophgo,cv1800b-dwcmshc";
> > reg = <0x4300000 0x1000>;
> > - interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&clk CLK_AXI4_EMMC>,
> > <&clk CLK_EMMC>;
> > clock-names = "core", "bus";
> > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
> > new file mode 100644
> > index 000000000000..a68d61131efb
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
> > @@ -0,0 +1,57 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> > + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> > + */
> > +
> > +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> > +
> > +/ {
> > + cpus: cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <25000000>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "thead,c906", "riscv";
> > + device_type = "cpu";
> > + reg = <0>;
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <512>;
> > + d-cache-size = <65536>;
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <32768>;
> > + mmu-type = "riscv,sv39";
> > + riscv,isa = "rv64imafdc";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > + "zifencei", "zihpm";
> > +
> > + cpu0_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&soc {
> > + interrupt-parent = <&plic>;
> > + dma-noncoherent;
> > +
> > + plic: interrupt-controller@70000000 {
> > + reg = <0x70000000 0x4000000>;
> > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> > + interrupt-controller;
> > + #address-cells = <0>;
> > + #interrupt-cells = <2>;
> > + riscv,ndev = <101>;
> > + };
> > +
> > + clint: timer@74000000 {
> > + reg = <0x74000000 0x10000>;
> > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> > + };
> > +};
> > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> > index c18822ec849f..62c1464a0490 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> > @@ -12,47 +12,16 @@ / {
> > #address-cells = <1>;
> > #size-cells = <1>;
> >
> > - cpus: cpus {
> > - #address-cells = <1>;
> > - #size-cells = <0>;
> > - timebase-frequency = <25000000>;
> > -
> > - cpu0: cpu@0 {
> > - compatible = "thead,c906", "riscv";
> > - device_type = "cpu";
> > - reg = <0>;
> > - d-cache-block-size = <64>;
> > - d-cache-sets = <512>;
> > - d-cache-size = <65536>;
> > - i-cache-block-size = <64>;
> > - i-cache-sets = <128>;
> > - i-cache-size = <32768>;
> > - mmu-type = "riscv,sv39";
> > - riscv,isa = "rv64imafdc";
> > - riscv,isa-base = "rv64i";
> > - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > - "zifencei", "zihpm";
> > -
> > - cpu0_intc: interrupt-controller {
> > - compatible = "riscv,cpu-intc";
> > - interrupt-controller;
> > - #interrupt-cells = <1>;
> > - };
> > - };
> > - };
> > -
> > osc: oscillator {
> > compatible = "fixed-clock";
> > clock-output-names = "osc_25m";
> > #clock-cells = <0>;
> > };
> >
> > - soc {
> > + soc: soc {
> > compatible = "simple-bus";
> > - interrupt-parent = <&plic>;
> > #address-cells = <1>;
> > #size-cells = <1>;
> > - dma-noncoherent;
> > ranges;
> >
> > clk: clock-controller@3002000 {
> > @@ -75,7 +44,7 @@ porta: gpio-controller@0 {
> > reg = <0>;
> > interrupt-controller;
> > #interrupt-cells = <2>;
> > - interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>;
> > };
> > };
> >
> > @@ -93,7 +62,7 @@ portb: gpio-controller@0 {
> > reg = <0>;
> > interrupt-controller;
> > #interrupt-cells = <2>;
> > - interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
> > };
> > };
> >
> > @@ -111,7 +80,7 @@ portc: gpio-controller@0 {
> > reg = <0>;
> > interrupt-controller;
> > #interrupt-cells = <2>;
> > - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
> > };
> > };
> >
> > @@ -129,7 +98,7 @@ portd: gpio-controller@0 {
> > reg = <0>;
> > interrupt-controller;
> > #interrupt-cells = <2>;
> > - interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>;
> > };
> > };
> >
> > @@ -137,7 +106,7 @@ saradc: adc@30f0000 {
> > compatible = "sophgo,cv1800b-saradc";
> > reg = <0x030f0000 0x1000>;
> > clocks = <&clk CLK_SARADC>;
> > - interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>;
> > #address-cells = <1>;
> > #size-cells = <0>;
> > status = "disabled";
> > @@ -162,7 +131,7 @@ i2c0: i2c@4000000 {
> > #size-cells = <0>;
> > clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
> > clock-names = "ref", "pclk";
> > - interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
> > status = "disabled";
> > };
> >
> > @@ -173,7 +142,7 @@ i2c1: i2c@4010000 {
> > #size-cells = <0>;
> > clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
> > clock-names = "ref", "pclk";
> > - interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
> > status = "disabled";
> > };
> >
> > @@ -184,7 +153,7 @@ i2c2: i2c@4020000 {
> > #size-cells = <0>;
> > clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
> > clock-names = "ref", "pclk";
> > - interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
> > status = "disabled";
> > };
> >
> > @@ -195,7 +164,7 @@ i2c3: i2c@4030000 {
> > #size-cells = <0>;
> > clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
> > clock-names = "ref", "pclk";
> > - interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
> > status = "disabled";
> > };
> >
> > @@ -206,14 +175,14 @@ i2c4: i2c@4040000 {
> > #size-cells = <0>;
> > clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
> > clock-names = "ref", "pclk";
> > - interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
> > status = "disabled";
> > };
> >
> > uart0: serial@4140000 {
> > compatible = "snps,dw-apb-uart";
> > reg = <0x04140000 0x100>;
> > - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
> > clock-names = "baudclk", "apb_pclk";
> > reg-shift = <2>;
> > @@ -224,7 +193,7 @@ uart0: serial@4140000 {
> > uart1: serial@4150000 {
> > compatible = "snps,dw-apb-uart";
> > reg = <0x04150000 0x100>;
> > - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
> > clock-names = "baudclk", "apb_pclk";
> > reg-shift = <2>;
> > @@ -235,7 +204,7 @@ uart1: serial@4150000 {
> > uart2: serial@4160000 {
> > compatible = "snps,dw-apb-uart";
> > reg = <0x04160000 0x100>;
> > - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
> > clock-names = "baudclk", "apb_pclk";
> > reg-shift = <2>;
> > @@ -246,7 +215,7 @@ uart2: serial@4160000 {
> > uart3: serial@4170000 {
> > compatible = "snps,dw-apb-uart";
> > reg = <0x04170000 0x100>;
> > - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
> > clock-names = "baudclk", "apb_pclk";
> > reg-shift = <2>;
> > @@ -261,7 +230,7 @@ spi0: spi@4180000 {
> > #size-cells = <0>;
> > clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
> > clock-names = "ssi_clk", "pclk";
> > - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
> > status = "disabled";
> > };
> >
> > @@ -272,7 +241,7 @@ spi1: spi@4190000 {
> > #size-cells = <0>;
> > clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
> > clock-names = "ssi_clk", "pclk";
> > - interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
> > status = "disabled";
> > };
> >
> > @@ -283,7 +252,7 @@ spi2: spi@41a0000 {
> > #size-cells = <0>;
> > clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
> > clock-names = "ssi_clk", "pclk";
> > - interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
> > status = "disabled";
> > };
> >
> > @@ -294,14 +263,14 @@ spi3: spi@41b0000 {
> > #size-cells = <0>;
> > clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
> > clock-names = "ssi_clk", "pclk";
> > - interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
> > status = "disabled";
> > };
> >
> > uart4: serial@41c0000 {
> > compatible = "snps,dw-apb-uart";
> > reg = <0x041c0000 0x100>;
> > - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
> > clock-names = "baudclk", "apb_pclk";
> > reg-shift = <2>;
> > @@ -312,7 +281,7 @@ uart4: serial@41c0000 {
> > sdhci0: mmc@4310000 {
> > compatible = "sophgo,cv1800b-dwcmshc";
> > reg = <0x4310000 0x1000>;
> > - interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&clk CLK_AXI4_SD0>,
> > <&clk CLK_SD0>;
> > clock-names = "core", "bus";
> > @@ -322,7 +291,7 @@ sdhci0: mmc@4310000 {
> > sdhci1: mmc@4320000 {
> > compatible = "sophgo,cv1800b-dwcmshc";
> > reg = <0x4320000 0x1000>;
> > - interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&clk CLK_AXI4_SD1>,
> > <&clk CLK_SD1>;
> > clock-names = "core", "bus";
> > @@ -332,7 +301,7 @@ sdhci1: mmc@4320000 {
> > dmac: dma-controller@4330000 {
> > compatible = "snps,axi-dma-1.01a";
> > reg = <0x04330000 0x1000>;
> > - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
> > clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
> > clock-names = "core-clk", "cfgr-clk";
> > #dma-cells = <1>;
> > @@ -344,19 +313,5 @@ dmac: dma-controller@4330000 {
> > snps,data-width = <4>;
> > status = "disabled";
> > };
> > -
> > - plic: interrupt-controller@70000000 {
> > - reg = <0x70000000 0x4000000>;
> > - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> > - interrupt-controller;
> > - #address-cells = <0>;
> > - #interrupt-cells = <2>;
> > - riscv,ndev = <101>;
> > - };
> > -
> > - clint: timer@74000000 {
> > - reg = <0x74000000 0x10000>;
> > - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> > - };
> > };
> > };
> > diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
> > index 7f79de33163c..732d0e72cf13 100644
> > --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
> > @@ -3,6 +3,8 @@
> > * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> > */
> >
> > +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> > +
> > #include <dt-bindings/interrupt-controller/irq.h>
> > #include <dt-bindings/pinctrl/pinctrl-sg2002.h>
> > #include "cv18xx.dtsi"
> > @@ -16,22 +18,62 @@ memory@80000000 {
> > reg = <0x80000000 0x10000000>;
> > };
> >
> > - soc {
> > - pinctrl: pinctrl@3001000 {
> > - compatible = "sophgo,sg2002-pinctrl";
> > - reg = <0x03001000 0x1000>,
> > - <0x05027000 0x1000>;
> > - reg-names = "sys", "rtc";
> > + cpus: cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <25000000>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "thead,c906", "riscv";
> > + device_type = "cpu";
> > + reg = <0>;
> > + d-cache-block-size = <64>;
> > + d-cache-sets = <512>;
> > + d-cache-size = <65536>;
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <32768>;
> > + mmu-type = "riscv,sv39";
> > + riscv,isa = "rv64imafdc";
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > + "zifencei", "zihpm";
> > +
> > + cpu0_intc: interrupt-controller {
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > };
> > };
> > };
> >
> > -&plic {
> > - compatible = "sophgo,sg2002-plic", "thead,c900-plic";
> > -};
> > +&soc {
> > + interrupt-parent = <&plic>;
> > + dma-noncoherent;
> >
> > -&clint {
> > - compatible = "sophgo,sg2002-clint", "thead,c900-clint";
> > + pinctrl: pinctrl@3001000 {
> > + compatible = "sophgo,sg2002-pinctrl";
> > + reg = <0x03001000 0x1000>,
> > + <0x05027000 0x1000>;
> > + reg-names = "sys", "rtc";
> > + };
> > +
> > + plic: interrupt-controller@70000000 {
> > + compatible = "sophgo,sg2002-plic", "thead,c900-plic";
> > + reg = <0x70000000 0x4000000>;
> > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> > + interrupt-controller;
> > + #address-cells = <0>;
> > + #interrupt-cells = <2>;
> > + riscv,ndev = <101>;
> > + };
> > +
> > + clint: timer@74000000 {
> > + compatible = "sophgo,sg2002-clint", "thead,c900-clint";
> > + reg = <0x74000000 0x10000>;
> > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> > + };
> > };
> >
> > &clk {
> > --
> > 2.48.1
> >
--
Alexander Sverdlin.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files
2025-02-12 9:26 ` Alexander Sverdlin
@ 2025-02-12 16:46 ` Krzysztof Kozlowski
2025-02-12 17:44 ` Alexander Sverdlin
0 siblings, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-12 16:46 UTC (permalink / raw)
To: Alexander Sverdlin, Inochi Amaoto, soc
Cc: Chen Wang, Inochi Amaoto, linux-riscv, devicetree, Haylen Chu,
linux-arm-kernel, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Arnd Bergmann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jisheng Zhang, Chao Wei
On 12/02/2025 10:26, Alexander Sverdlin wrote:
> Hi Inochi, Krzysztof,
>
> On Wed, 2025-02-12 at 08:31 +0800, Inochi Amaoto wrote:
>> On Mon, Feb 10, 2025 at 11:09:41PM +0100, Alexander Sverdlin wrote:
>>> Make the peripheral device tree re-usable on ARM64 platform by moving CPU
>>> core and interrupt controllers' parts into the respective per-SoC .dtsi
>>> files.
>>>
>>> Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
>>> into "plic" interrupt-controller numbering.
>>>
>>> Have a nice refactoring side-effect that "plic" and "clint" "compatible"
>>> property is not specified outside of the corresponding device itself.
>>>
>>> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
>>> ---
>>> Changelog:
>>> v2:
>>> - instead of carving out peripherals' part, carve out ARCH-specifics (CPU
>>> core, interrupt controllers) and spread them among 3 SoC .dtsi files which
>>> included cv18xx.dtsi;
>>> - define a label for the "soc" node and use it in the newly introduced DTs;
>>>
>>> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 64 ++++++++++++---
>>> arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 64 ++++++++++++---
>>> arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
>>> arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++++
>>> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 ++++++----------------
>>> arch/riscv/boot/dts/sophgo/sg2002.dtsi | 64 ++++++++++++---
>>> 6 files changed, 240 insertions(+), 102 deletions(-)
>>> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
>>>
>>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>>> index aa1f5df100f0..eef2884b36f9 100644
>>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>>> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>>> @@ -3,6 +3,8 @@
>>> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
>>> */
>>>
>>> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
>>> +
>>> #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
>>> #include "cv18xx.dtsi"
>>>
>>> @@ -14,22 +16,62 @@ memory@80000000 {
>>> reg = <0x80000000 0x4000000>;
>>> };
>>>
>>
>>> - soc {
>>> - pinctrl: pinctrl@3001000 {
>>> - compatible = "sophgo,cv1800b-pinctrl";
>>> - reg = <0x03001000 0x1000>,
>>> - <0x05027000 0x1000>;
>>> - reg-names = "sys", "rtc";
>>
>>
>>> + cpus: cpus {
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> + timebase-frequency = <25000000>;
>>> +
>>> + cpu0: cpu@0 {
>>> + compatible = "thead,c906", "riscv";
>>> + device_type = "cpu";
>>> + reg = <0>;
>>> + d-cache-block-size = <64>;
>>> + d-cache-sets = <512>;
>>> + d-cache-size = <65536>;
>>> + i-cache-block-size = <64>;
>>> + i-cache-sets = <128>;
>>> + i-cache-size = <32768>;
>>> + mmu-type = "riscv,sv39";
>>> + riscv,isa = "rv64imafdc";
>>> + riscv,isa-base = "rv64i";
>>> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
>>> + "zifencei", "zihpm";
>>> +
>>> + cpu0_intc: interrupt-controller {
>>> + compatible = "riscv,cpu-intc";
>>> + interrupt-controller;
>>> + #interrupt-cells = <1>;
>>> + };
>>> };
>>> };
>>> };
>>
>> Make all soc definition include the common cpu file.
>> Not just copy it.
>
> I was acting according to Krzysztof's suggestion:
> https://lore.kernel.org/soc/d3ba0ea5-0491-42d5-a18e-64cf21df696c@kernel.org/
>
> Krzysztof, I can name the file cv18xx-cpu-intc.dtsi and pack CPU core + interrupt
> controllers into it. Would it make sense?
I don't understand the original suggestion.
Inochi, please trim unnecessary context from replies.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files
2025-02-12 16:46 ` Krzysztof Kozlowski
@ 2025-02-12 17:44 ` Alexander Sverdlin
2025-02-12 19:24 ` Krzysztof Kozlowski
2025-02-12 22:31 ` Inochi Amaoto
0 siblings, 2 replies; 18+ messages in thread
From: Alexander Sverdlin @ 2025-02-12 17:44 UTC (permalink / raw)
To: Krzysztof Kozlowski, Inochi Amaoto, soc
Cc: Chen Wang, Inochi Amaoto, linux-riscv, devicetree, Haylen Chu,
linux-arm-kernel, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Arnd Bergmann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jisheng Zhang, Chao Wei
Hi
On Wed, 2025-02-12 at 17:46 +0100, Krzysztof Kozlowski wrote:
> > > > Make the peripheral device tree re-usable on ARM64 platform by moving CPU
> > > > core and interrupt controllers' parts into the respective per-SoC .dtsi
> > > > files.
> > > >
> > > > Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
> > > > into "plic" interrupt-controller numbering.
> > > >
> > > > Have a nice refactoring side-effect that "plic" and "clint" "compatible"
> > > > property is not specified outside of the corresponding device itself.
> > > >
> > > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> > > > ---
> > > > Changelog:
> > > > v2:
> > > > - instead of carving out peripherals' part, carve out ARCH-specifics (CPU
> > > > core, interrupt controllers) and spread them among 3 SoC .dtsi files which
> > > > included cv18xx.dtsi;
> > > > - define a label for the "soc" node and use it in the newly introduced DTs;
> > > >
> > > > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 64 ++++++++++++---
> > > > arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 64 ++++++++++++---
> > > > arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
> > > > arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++++
> > > > arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 ++++++----------------
> > > > arch/riscv/boot/dts/sophgo/sg2002.dtsi | 64 ++++++++++++---
> > > > 6 files changed, 240 insertions(+), 102 deletions(-)
> > > > create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
> > > >
> > > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > > > index aa1f5df100f0..eef2884b36f9 100644
> > > > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > > > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > > > @@ -3,6 +3,8 @@
> > > > * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> > > > */
> > > >
> > > > +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> > > > +
> > > > #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
> > > > #include "cv18xx.dtsi"
> > > >
> > > > @@ -14,22 +16,62 @@ memory@80000000 {
> > > > reg = <0x80000000 0x4000000>;
> > > > };
> > > >
> > >
> > > > - soc {
> > > > - pinctrl: pinctrl@3001000 {
> > > > - compatible = "sophgo,cv1800b-pinctrl";
> > > > - reg = <0x03001000 0x1000>,
> > > > - <0x05027000 0x1000>;
> > > > - reg-names = "sys", "rtc";
> > >
> > >
> > > > + cpus: cpus {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + timebase-frequency = <25000000>;
> > > > +
> > > > + cpu0: cpu@0 {
> > > > + compatible = "thead,c906", "riscv";
> > > > + device_type = "cpu";
> > > > + reg = <0>;
> > > > + d-cache-block-size = <64>;
> > > > + d-cache-sets = <512>;
> > > > + d-cache-size = <65536>;
> > > > + i-cache-block-size = <64>;
> > > > + i-cache-sets = <128>;
> > > > + i-cache-size = <32768>;
> > > > + mmu-type = "riscv,sv39";
> > > > + riscv,isa = "rv64imafdc";
> > > > + riscv,isa-base = "rv64i";
> > > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > > > + "zifencei", "zihpm";
> > > > +
> > > > + cpu0_intc: interrupt-controller {
> > > > + compatible = "riscv,cpu-intc";
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <1>;
> > > > + };
> > > > };
> > > > };
> > > > };
> > >
> > > Make all soc definition include the common cpu file.
> > > Not just copy it.
> >
> > I was acting according to Krzysztof's suggestion:
> > https://lore.kernel.org/soc/d3ba0ea5-0491-42d5-a18e-64cf21df696c@kernel.org/
> >
> > Krzysztof, I can name the file cv18xx-cpu-intc.dtsi and pack CPU core + interrupt
> > controllers into it. Would it make sense?
>
>
> I don't understand the original suggestion.
This is the snippet in question:
---[ cut ]---
#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
/ {
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <65536>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
};
&soc {
interrupt-parent = <&plic>;
dma-noncoherent;
plic: interrupt-controller@70000000 {
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
---[ cut ]---
Inochi's proposal is to put it into separate cv18xx-cpu-intc.dtsi and
include the latter in 3 other SoC-specific .dtsis. In v2 I've just
duplicated the above snippet 3 times (refer to diffstat above).
What are your thoughts? In Renesas everything is duplicated, I believe.
Sophgo outsources much smaller snippets into .dtsi (refer to cv181x.dtsi).
> Inochi, please trim unnecessary context from replies.
--
Alexander Sverdlin.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files
2025-02-12 17:44 ` Alexander Sverdlin
@ 2025-02-12 19:24 ` Krzysztof Kozlowski
2025-02-12 22:32 ` Inochi Amaoto
2025-02-12 22:31 ` Inochi Amaoto
1 sibling, 1 reply; 18+ messages in thread
From: Krzysztof Kozlowski @ 2025-02-12 19:24 UTC (permalink / raw)
To: Alexander Sverdlin, Inochi Amaoto, soc
Cc: Chen Wang, Inochi Amaoto, linux-riscv, devicetree, Haylen Chu,
linux-arm-kernel, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Arnd Bergmann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jisheng Zhang, Chao Wei
On 12/02/2025 18:44, Alexander Sverdlin wrote:
> Hi
>
> On Wed, 2025-02-12 at 17:46 +0100, Krzysztof Kozlowski wrote:
>>>>> Make the peripheral device tree re-usable on ARM64 platform by moving CPU
>>>>> core and interrupt controllers' parts into the respective per-SoC .dtsi
>>>>> files.
>>>>>
>>>>> Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
>>>>> into "plic" interrupt-controller numbering.
>>>>>
>>>>> Have a nice refactoring side-effect that "plic" and "clint" "compatible"
>>>>> property is not specified outside of the corresponding device itself.
>>>>>
>>>>> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
>>>>> ---
>>>>> Changelog:
>>>>> v2:
>>>>> - instead of carving out peripherals' part, carve out ARCH-specifics (CPU
>>>>> core, interrupt controllers) and spread them among 3 SoC .dtsi files which
>>>>> included cv18xx.dtsi;
>>>>> - define a label for the "soc" node and use it in the newly introduced DTs;
>>>>>
>>>>> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 64 ++++++++++++---
>>>>> arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 64 ++++++++++++---
>>>>> arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
>>>>> arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++++
>>>>> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 ++++++----------------
>>>>> arch/riscv/boot/dts/sophgo/sg2002.dtsi | 64 ++++++++++++---
>>>>> 6 files changed, 240 insertions(+), 102 deletions(-)
>>>>> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
>>>>>
>>>>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>>>>> index aa1f5df100f0..eef2884b36f9 100644
>>>>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>>>>> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>>>>> @@ -3,6 +3,8 @@
>>>>> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
>>>>> */
>>>>>
>>>>> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
>>>>> +
>>>>> #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
>>>>> #include "cv18xx.dtsi"
>>>>>
>>>>> @@ -14,22 +16,62 @@ memory@80000000 {
>>>>> reg = <0x80000000 0x4000000>;
>>>>> };
>>>>>
>>>>
>>>>> - soc {
>>>>> - pinctrl: pinctrl@3001000 {
>>>>> - compatible = "sophgo,cv1800b-pinctrl";
>>>>> - reg = <0x03001000 0x1000>,
>>>>> - <0x05027000 0x1000>;
>>>>> - reg-names = "sys", "rtc";
>>>>
>>>>
>>>>> + cpus: cpus {
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> + timebase-frequency = <25000000>;
>>>>> +
>>>>> + cpu0: cpu@0 {
>>>>> + compatible = "thead,c906", "riscv";
>>>>> + device_type = "cpu";
>>>>> + reg = <0>;
>>>>> + d-cache-block-size = <64>;
>>>>> + d-cache-sets = <512>;
>>>>> + d-cache-size = <65536>;
>>>>> + i-cache-block-size = <64>;
>>>>> + i-cache-sets = <128>;
>>>>> + i-cache-size = <32768>;
>>>>> + mmu-type = "riscv,sv39";
>>>>> + riscv,isa = "rv64imafdc";
>>>>> + riscv,isa-base = "rv64i";
>>>>> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
>>>>> + "zifencei", "zihpm";
>>>>> +
>>>>> + cpu0_intc: interrupt-controller {
>>>>> + compatible = "riscv,cpu-intc";
>>>>> + interrupt-controller;
>>>>> + #interrupt-cells = <1>;
>>>>> + };
>>>>> };
>>>>> };
>>>>> };
>>>>
>>>> Make all soc definition include the common cpu file.
>>>> Not just copy it.
>>>
>>> I was acting according to Krzysztof's suggestion:
>>> https://lore.kernel.org/soc/d3ba0ea5-0491-42d5-a18e-64cf21df696c@kernel.org/
>>>
>>> Krzysztof, I can name the file cv18xx-cpu-intc.dtsi and pack CPU core + interrupt
>>> controllers into it. Would it make sense?
>>
>>
>> I don't understand the original suggestion.
>
> This is the snippet in question:
>
> ---[ cut ]---
> #define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
>
> / {
> cpus: cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> timebase-frequency = <25000000>;
>
> cpu0: cpu@0 {
> compatible = "thead,c906", "riscv";
> device_type = "cpu";
> reg = <0>;
> d-cache-block-size = <64>;
> d-cache-sets = <512>;
> d-cache-size = <65536>;
> i-cache-block-size = <64>;
> i-cache-sets = <128>;
> i-cache-size = <32768>;
> mmu-type = "riscv,sv39";
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> "zifencei", "zihpm";
>
> cpu0_intc: interrupt-controller {
> compatible = "riscv,cpu-intc";
> interrupt-controller;
> #interrupt-cells = <1>;
> };
> };
> };
> };
>
> &soc {
> interrupt-parent = <&plic>;
> dma-noncoherent;
>
> plic: interrupt-controller@70000000 {
> reg = <0x70000000 0x4000000>;
> interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> interrupt-controller;
> #address-cells = <0>;
> #interrupt-cells = <2>;
> riscv,ndev = <101>;
> };
>
> clint: timer@74000000 {
> reg = <0x74000000 0x10000>;
> interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> };
> };
> ---[ cut ]---
>
> Inochi's proposal is to put it into separate cv18xx-cpu-intc.dtsi and
> include the latter in 3 other SoC-specific .dtsis. In v2 I've just
> duplicated the above snippet 3 times (refer to diffstat above).
>
> What are your thoughts? In Renesas everything is duplicated, I believe.
> Sophgo outsources much smaller snippets into .dtsi (refer to cv181x.dtsi).
If it represents some shared design/part, then it feels good.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files
2025-02-12 17:44 ` Alexander Sverdlin
2025-02-12 19:24 ` Krzysztof Kozlowski
@ 2025-02-12 22:31 ` Inochi Amaoto
1 sibling, 0 replies; 18+ messages in thread
From: Inochi Amaoto @ 2025-02-12 22:31 UTC (permalink / raw)
To: Alexander Sverdlin, Krzysztof Kozlowski, Inochi Amaoto, soc
Cc: Chen Wang, Inochi Amaoto, linux-riscv, devicetree, Haylen Chu,
linux-arm-kernel, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Arnd Bergmann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jisheng Zhang, Chao Wei
On Wed, Feb 12, 2025 at 06:44:15PM +0100, Alexander Sverdlin wrote:
> Hi
>
> On Wed, 2025-02-12 at 17:46 +0100, Krzysztof Kozlowski wrote:
> > > > > Make the peripheral device tree re-usable on ARM64 platform by moving CPU
> > > > > core and interrupt controllers' parts into the respective per-SoC .dtsi
> > > > > files.
> > > > >
> > > > > Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
> > > > > into "plic" interrupt-controller numbering.
> > > > >
> > > > > Have a nice refactoring side-effect that "plic" and "clint" "compatible"
> > > > > property is not specified outside of the corresponding device itself.
> > > > >
> > > > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> > > > > ---
> > > > > Changelog:
> > > > > v2:
> > > > > - instead of carving out peripherals' part, carve out ARCH-specifics (CPU
> > > > > core, interrupt controllers) and spread them among 3 SoC .dtsi files which
> > > > > included cv18xx.dtsi;
> > > > > - define a label for the "soc" node and use it in the newly introduced DTs;
> > > > >
> > > > > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 64 ++++++++++++---
> > > > > arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 64 ++++++++++++---
> > > > > arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
> > > > > arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++++
> > > > > arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 ++++++----------------
> > > > > arch/riscv/boot/dts/sophgo/sg2002.dtsi | 64 ++++++++++++---
> > > > > 6 files changed, 240 insertions(+), 102 deletions(-)
> > > > > create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
> > > > >
> > > > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > > > > index aa1f5df100f0..eef2884b36f9 100644
> > > > > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > > > > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > > > > @@ -3,6 +3,8 @@
> > > > > * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> > > > > */
> > > > >
> > > > > +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> > > > > +
> > > > > #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
> > > > > #include "cv18xx.dtsi"
> > > > >
> > > > > @@ -14,22 +16,62 @@ memory@80000000 {
> > > > > reg = <0x80000000 0x4000000>;
> > > > > };
> > > > >
> > > >
> > > > > - soc {
> > > > > - pinctrl: pinctrl@3001000 {
> > > > > - compatible = "sophgo,cv1800b-pinctrl";
> > > > > - reg = <0x03001000 0x1000>,
> > > > > - <0x05027000 0x1000>;
> > > > > - reg-names = "sys", "rtc";
> > > >
> > > >
> > > > > + cpus: cpus {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > + timebase-frequency = <25000000>;
> > > > > +
> > > > > + cpu0: cpu@0 {
> > > > > + compatible = "thead,c906", "riscv";
> > > > > + device_type = "cpu";
> > > > > + reg = <0>;
> > > > > + d-cache-block-size = <64>;
> > > > > + d-cache-sets = <512>;
> > > > > + d-cache-size = <65536>;
> > > > > + i-cache-block-size = <64>;
> > > > > + i-cache-sets = <128>;
> > > > > + i-cache-size = <32768>;
> > > > > + mmu-type = "riscv,sv39";
> > > > > + riscv,isa = "rv64imafdc";
> > > > > + riscv,isa-base = "rv64i";
> > > > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > > > > + "zifencei", "zihpm";
> > > > > +
> > > > > + cpu0_intc: interrupt-controller {
> > > > > + compatible = "riscv,cpu-intc";
> > > > > + interrupt-controller;
> > > > > + #interrupt-cells = <1>;
> > > > > + };
> > > > > };
> > > > > };
> > > > > };
> > > >
> > > > Make all soc definition include the common cpu file.
> > > > Not just copy it.
> > >
> > > I was acting according to Krzysztof's suggestion:
> > > https://lore.kernel.org/soc/d3ba0ea5-0491-42d5-a18e-64cf21df696c@kernel.org/
> > >
> > > Krzysztof, I can name the file cv18xx-cpu-intc.dtsi and pack CPU core + interrupt
> > > controllers into it. Would it make sense?
> >
> >
> > I don't understand the original suggestion.
>
> This is the snippet in question:
>
> ---[ cut ]---
> #define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
>
> / {
> cpus: cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> timebase-frequency = <25000000>;
>
> cpu0: cpu@0 {
> compatible = "thead,c906", "riscv";
> device_type = "cpu";
> reg = <0>;
> d-cache-block-size = <64>;
> d-cache-sets = <512>;
> d-cache-size = <65536>;
> i-cache-block-size = <64>;
> i-cache-sets = <128>;
> i-cache-size = <32768>;
> mmu-type = "riscv,sv39";
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> "zifencei", "zihpm";
>
> cpu0_intc: interrupt-controller {
> compatible = "riscv,cpu-intc";
> interrupt-controller;
> #interrupt-cells = <1>;
> };
> };
> };
> };
>
> &soc {
> interrupt-parent = <&plic>;
> dma-noncoherent;
>
> plic: interrupt-controller@70000000 {
> reg = <0x70000000 0x4000000>;
> interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> interrupt-controller;
> #address-cells = <0>;
> #interrupt-cells = <2>;
> riscv,ndev = <101>;
> };
>
> clint: timer@74000000 {
> reg = <0x74000000 0x10000>;
> interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> };
> };
> ---[ cut ]---
>
> Inochi's proposal is to put it into separate cv18xx-cpu-intc.dtsi and
> include the latter in 3 other SoC-specific .dtsis.
Yes, this is what I want to say. Since I can confirm all cv18xx
series have the same riscv core (IIRC they share the same hw
design). There is no reason to duplicate them.
> In v2 I've just
> duplicated the above snippet 3 times (refer to diffstat above).
>
> What are your thoughts? In Renesas everything is duplicated, I believe.
> Sophgo outsources much smaller snippets into .dtsi (refer to cv181x.dtsi).
>
> > Inochi, please trim unnecessary context from replies.
>
> --
> Alexander Sverdlin.
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files
2025-02-12 19:24 ` Krzysztof Kozlowski
@ 2025-02-12 22:32 ` Inochi Amaoto
0 siblings, 0 replies; 18+ messages in thread
From: Inochi Amaoto @ 2025-02-12 22:32 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alexander Sverdlin, Inochi Amaoto, soc
Cc: Chen Wang, Inochi Amaoto, linux-riscv, devicetree, Haylen Chu,
linux-arm-kernel, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Arnd Bergmann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jisheng Zhang, Chao Wei
On Wed, Feb 12, 2025 at 08:24:55PM +0100, Krzysztof Kozlowski wrote:
> On 12/02/2025 18:44, Alexander Sverdlin wrote:
> > Hi
> >
> > On Wed, 2025-02-12 at 17:46 +0100, Krzysztof Kozlowski wrote:
> >>>>> Make the peripheral device tree re-usable on ARM64 platform by moving CPU
> >>>>> core and interrupt controllers' parts into the respective per-SoC .dtsi
> >>>>> files.
> >>>>>
> >>>>> Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
> >>>>> into "plic" interrupt-controller numbering.
> >>>>>
> >>>>> Have a nice refactoring side-effect that "plic" and "clint" "compatible"
> >>>>> property is not specified outside of the corresponding device itself.
> >>>>>
> >>>>> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> >>>>> ---
> >>>>> Changelog:
> >>>>> v2:
> >>>>> - instead of carving out peripherals' part, carve out ARCH-specifics (CPU
> >>>>> core, interrupt controllers) and spread them among 3 SoC .dtsi files which
> >>>>> included cv18xx.dtsi;
> >>>>> - define a label for the "soc" node and use it in the newly introduced DTs;
> >>>>>
> >>>>> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 64 ++++++++++++---
> >>>>> arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 64 ++++++++++++---
> >>>>> arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
> >>>>> arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++++
> >>>>> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 ++++++----------------
> >>>>> arch/riscv/boot/dts/sophgo/sg2002.dtsi | 64 ++++++++++++---
> >>>>> 6 files changed, 240 insertions(+), 102 deletions(-)
> >>>>> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
> >>>>>
> >>>>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> >>>>> index aa1f5df100f0..eef2884b36f9 100644
> >>>>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> >>>>> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> >>>>> @@ -3,6 +3,8 @@
> >>>>> * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> >>>>> */
> >>>>>
> >>>>> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> >>>>> +
> >>>>> #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
> >>>>> #include "cv18xx.dtsi"
> >>>>>
> >>>>> @@ -14,22 +16,62 @@ memory@80000000 {
> >>>>> reg = <0x80000000 0x4000000>;
> >>>>> };
> >>>>>
> >>>>
> >>>>> - soc {
> >>>>> - pinctrl: pinctrl@3001000 {
> >>>>> - compatible = "sophgo,cv1800b-pinctrl";
> >>>>> - reg = <0x03001000 0x1000>,
> >>>>> - <0x05027000 0x1000>;
> >>>>> - reg-names = "sys", "rtc";
> >>>>
> >>>>
> >>>>> + cpus: cpus {
> >>>>> + #address-cells = <1>;
> >>>>> + #size-cells = <0>;
> >>>>> + timebase-frequency = <25000000>;
> >>>>> +
> >>>>> + cpu0: cpu@0 {
> >>>>> + compatible = "thead,c906", "riscv";
> >>>>> + device_type = "cpu";
> >>>>> + reg = <0>;
> >>>>> + d-cache-block-size = <64>;
> >>>>> + d-cache-sets = <512>;
> >>>>> + d-cache-size = <65536>;
> >>>>> + i-cache-block-size = <64>;
> >>>>> + i-cache-sets = <128>;
> >>>>> + i-cache-size = <32768>;
> >>>>> + mmu-type = "riscv,sv39";
> >>>>> + riscv,isa = "rv64imafdc";
> >>>>> + riscv,isa-base = "rv64i";
> >>>>> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> >>>>> + "zifencei", "zihpm";
> >>>>> +
> >>>>> + cpu0_intc: interrupt-controller {
> >>>>> + compatible = "riscv,cpu-intc";
> >>>>> + interrupt-controller;
> >>>>> + #interrupt-cells = <1>;
> >>>>> + };
> >>>>> };
> >>>>> };
> >>>>> };
> >>>>
> >>>> Make all soc definition include the common cpu file.
> >>>> Not just copy it.
> >>>
> >>> I was acting according to Krzysztof's suggestion:
> >>> https://lore.kernel.org/soc/d3ba0ea5-0491-42d5-a18e-64cf21df696c@kernel.org/
> >>>
> >>> Krzysztof, I can name the file cv18xx-cpu-intc.dtsi and pack CPU core + interrupt
> >>> controllers into it. Would it make sense?
> >>
> >>
> >> I don't understand the original suggestion.
> >
> > This is the snippet in question:
> >
> > ---[ cut ]---
> > #define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> >
> > / {
> > cpus: cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > timebase-frequency = <25000000>;
> >
> > cpu0: cpu@0 {
> > compatible = "thead,c906", "riscv";
> > device_type = "cpu";
> > reg = <0>;
> > d-cache-block-size = <64>;
> > d-cache-sets = <512>;
> > d-cache-size = <65536>;
> > i-cache-block-size = <64>;
> > i-cache-sets = <128>;
> > i-cache-size = <32768>;
> > mmu-type = "riscv,sv39";
> > riscv,isa = "rv64imafdc";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > "zifencei", "zihpm";
> >
> > cpu0_intc: interrupt-controller {
> > compatible = "riscv,cpu-intc";
> > interrupt-controller;
> > #interrupt-cells = <1>;
> > };
> > };
> > };
> > };
> >
> > &soc {
> > interrupt-parent = <&plic>;
> > dma-noncoherent;
> >
> > plic: interrupt-controller@70000000 {
> > reg = <0x70000000 0x4000000>;
> > interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> > interrupt-controller;
> > #address-cells = <0>;
> > #interrupt-cells = <2>;
> > riscv,ndev = <101>;
> > };
> >
> > clint: timer@74000000 {
> > reg = <0x74000000 0x10000>;
> > interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> > };
> > };
> > ---[ cut ]---
> >
> > Inochi's proposal is to put it into separate cv18xx-cpu-intc.dtsi and
> > include the latter in 3 other SoC-specific .dtsis. In v2 I've just
> > duplicated the above snippet 3 times (refer to diffstat above).
> >
> > What are your thoughts? In Renesas everything is duplicated, I believe.
> > Sophgo outsources much smaller snippets into .dtsi (refer to cv181x.dtsi).
>
> If it represents some shared design/part, then it feels good.
> Best regards,
> Krzysztof
Yes, it does share the same design.
Regards,
Inochi
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2025-02-12 22:32 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-10 22:09 [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB Alexander Sverdlin
2025-02-10 22:09 ` [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files Alexander Sverdlin
2025-02-12 0:31 ` Inochi Amaoto
2025-02-12 9:26 ` Alexander Sverdlin
2025-02-12 16:46 ` Krzysztof Kozlowski
2025-02-12 17:44 ` Alexander Sverdlin
2025-02-12 19:24 ` Krzysztof Kozlowski
2025-02-12 22:32 ` Inochi Amaoto
2025-02-12 22:31 ` Inochi Amaoto
2025-02-10 22:09 ` [PATCH v2 2/7] dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 Alexander Sverdlin
2025-02-11 1:29 ` Chen Wang
2025-02-11 18:18 ` Conor Dooley
2025-02-10 22:09 ` [PATCH v2 3/7] arm64: dts: sophgo: Add initial SG2000 SoC device tree Alexander Sverdlin
2025-02-10 22:09 ` [PATCH v2 4/7] arm64: dts: sophgo: Add Duo Module 01 Alexander Sverdlin
2025-02-10 22:09 ` [PATCH v2 5/7] arm64: dts: sophgo: Add Duo Module 01 Evaluation Board Alexander Sverdlin
2025-02-11 10:50 ` [PATCH v2 0/7] arm64 support for Milk-V Duo Module 01 EVB Conor Dooley
2025-02-11 12:43 ` Alexander Sverdlin
2025-02-11 13:48 ` Conor Dooley
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