From: Bjorn Helgaas <helgaas@kernel.org>
To: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Cc: cros-qcom-dts-watchers@chromium.org,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konradybcio@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
quic_vbadigan@quicinc.com, quic_mrana@quicinc.com,
quic_vpernami@quicinc.com, mmareddy@quicinc.com
Subject: Re: [PATCH v4 4/4] PCI: qcom: Enable ECAM feature
Date: Mon, 10 Feb 2025 16:54:31 -0600 [thread overview]
Message-ID: <20250210225431.GA21989@bhelgaas> (raw)
In-Reply-To: <20250207-ecam_v4-v4-4-94b5d5ec5017@oss.qualcomm.com>
On Fri, Feb 07, 2025 at 04:58:59AM +0530, Krishna Chaitanya Chundru wrote:
> The ELBI registers falls after the DBI space, PARF_SLV_DBI_ELBI register
> gives us the offset from which ELBI starts. so use this offset and cfg
> win to map these regions instead of doing the ioremap again.
> + /* Set the ECAM base */
> + writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE);
> + writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI);
> +
> + /*
> + * The only device on root bus is the Root Port. Any access other than that
> + * should not go out of the link and should return all F's. Since the iATU
> + * is configured for the buses which starts after root bus, block the transactions
> + * starting from function 1 of the root bus to the end of the root bus (i.e from
> + * dbi_base + 4kb to dbi_base + 1MB) from going outside the link.
99% of this file fits in 80 columns. Wrap comments to do the same.
The text doesn't quite make sense because accesses to devices on the
root bus *never* involve a link. Only Root Ports have links and the
links all lead to buses other than the root bus.
next prev parent reply other threads:[~2025-02-10 22:54 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 23:28 [PATCH v4 0/4] PCI: dwc: Add ECAM support with iATU configuration Krishna Chaitanya Chundru
2025-02-06 23:28 ` [PATCH v4 1/4] arm64: dts: qcom: sc7280: Increase config size to 256MB for ECAM feature Krishna Chaitanya Chundru
2025-02-06 23:28 ` [PATCH v4 2/4] PCI: dwc: Add ECAM support with iATU configuration Krishna Chaitanya Chundru
2025-02-10 8:37 ` Manivannan Sadhasivam
2025-03-05 18:14 ` Manivannan Sadhasivam
2025-02-06 23:28 ` [PATCH v4 3/4] PCI: dwc: Reduce DT reads by allocating host bridge via DWC glue driver Krishna Chaitanya Chundru
2025-02-10 9:20 ` Manivannan Sadhasivam
2025-03-05 18:18 ` Manivannan Sadhasivam
2025-02-06 23:28 ` [PATCH v4 4/4] PCI: qcom: Enable ECAM feature Krishna Chaitanya Chundru
2025-02-10 9:22 ` Manivannan Sadhasivam
2025-02-10 9:34 ` Krishna Chaitanya Chundru
2025-02-10 9:47 ` Manivannan Sadhasivam
2025-02-10 9:53 ` Krishna Chaitanya Chundru
2025-02-10 10:08 ` Manivannan Sadhasivam
2025-03-05 18:26 ` Manivannan Sadhasivam
2025-03-07 1:14 ` Krishna Chaitanya Chundru
2025-03-07 17:40 ` Manivannan Sadhasivam
2025-02-10 22:54 ` Bjorn Helgaas [this message]
2025-02-17 5:07 ` Krishna Chaitanya Chundru
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