* [PATCH 0/7] Add DMAC support to the RZ/V2H(P)
@ 2025-02-06 22:03 Fabrizio Castro
2025-02-06 22:03 ` [PATCH 2/7] dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H Fabrizio Castro
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Fabrizio Castro @ 2025-02-06 22:03 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Michael Turquette, Stephen Boyd, Thomas Gleixner,
Geert Uytterhoeven
Cc: Fabrizio Castro, Magnus Damm, Wolfram Sang, Philipp Zabel,
Biju Das, Uwe Kleine-König, dmaengine, devicetree,
linux-kernel, linux-renesas-soc, linux-clk, Lad Prabhakar
Dear All,
This series adds DMAC support to the Renesas RZ/V2H(P).
Cheers,
Fab
Fabrizio Castro (7):
clk: renesas: r9a09g057: Add entries for the DMACs
dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H
dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req_ack
dmaengine: sh: rz-dmac: Allow for multiple DMACs
dmaengine: sh: rz-dmac: Add RZ/V2H(P) support
arm64: dts: renesas: r9a09g057: Add DMAC nodes
.../bindings/dma/renesas,rz-dmac.yaml | 148 +++++++++++++--
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 165 +++++++++++++++++
drivers/clk/renesas/r9a09g057-cpg.c | 24 +++
drivers/clk/renesas/rzv2h-cpg.h | 2 +
drivers/dma/sh/Kconfig | 1 +
drivers/dma/sh/rz-dmac.c | 170 ++++++++++++++++--
drivers/irqchip/irq-renesas-rzv2h.c | 61 +++++++
include/linux/irqchip/irq-renesas-rzv2h.h | 19 ++
8 files changed, 555 insertions(+), 35 deletions(-)
create mode 100644 include/linux/irqchip/irq-renesas-rzv2h.h
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/7] dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H
2025-02-06 22:03 [PATCH 0/7] Add DMAC support to the RZ/V2H(P) Fabrizio Castro
@ 2025-02-06 22:03 ` Fabrizio Castro
2025-02-06 22:03 ` [PATCH 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs Fabrizio Castro
2025-02-06 22:03 ` [PATCH 7/7] arm64: dts: renesas: r9a09g057: Add DMAC nodes Fabrizio Castro
2 siblings, 0 replies; 6+ messages in thread
From: Fabrizio Castro @ 2025-02-06 22:03 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven
Cc: Fabrizio Castro, Magnus Damm, Biju Das, Wolfram Sang, dmaengine,
devicetree, linux-kernel, linux-renesas-soc, Lad Prabhakar
Make sure we don't allow for the clocks, clock-names, resets,
reset-names. and power-domains properties for the Renesas
RZ/A1H SoC because its DMAC doesn't have clocks, resets,
and power domains.
Fixes: 209efec19c4c ("dt-bindings: dma: rz-dmac: Document RZ/A1H SoC")
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
.../devicetree/bindings/dma/renesas,rz-dmac.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
index b356251de5a8..82de3b927479 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -112,6 +112,14 @@ allOf:
- resets
- reset-names
+ else:
+ properties:
+ clocks: false
+ clock-names: false
+ power-domains: false
+ resets: false
+ reset-names: false
+
additionalProperties: false
examples:
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
2025-02-06 22:03 [PATCH 0/7] Add DMAC support to the RZ/V2H(P) Fabrizio Castro
2025-02-06 22:03 ` [PATCH 2/7] dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H Fabrizio Castro
@ 2025-02-06 22:03 ` Fabrizio Castro
2025-02-11 22:26 ` Rob Herring
2025-02-06 22:03 ` [PATCH 7/7] arm64: dts: renesas: r9a09g057: Add DMAC nodes Fabrizio Castro
2 siblings, 1 reply; 6+ messages in thread
From: Fabrizio Castro @ 2025-02-06 22:03 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven
Cc: Fabrizio Castro, Magnus Damm, Biju Das, dmaengine, devicetree,
linux-kernel, linux-renesas-soc, Lad Prabhakar
Document the Renesas RZ/V2H(P) family of SoCs DMAC block.
The Renesas RZ/V2H(P) DMAC is very similar to the one found on the
Renesas RZ/G2L family of SoCs, but there are some differences:
* It only uses one register area
* It only uses one clock
* It only uses one reset
* Instead of using MID/IRD it uses REQ NO/ACK NO
* It is connected to the Interrupt Control Unit (ICU)
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
.../bindings/dma/renesas,rz-dmac.yaml | 152 +++++++++++++++---
1 file changed, 127 insertions(+), 25 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
index 82de3b927479..d4dd22432e49 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -11,19 +11,23 @@ maintainers:
properties:
compatible:
- items:
- - enum:
- - renesas,r7s72100-dmac # RZ/A1H
- - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
- - renesas,r9a07g044-dmac # RZ/G2{L,LC}
- - renesas,r9a07g054-dmac # RZ/V2L
- - renesas,r9a08g045-dmac # RZ/G3S
- - const: renesas,rz-dmac
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r7s72100-dmac # RZ/A1H
+ - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
+ - renesas,r9a07g044-dmac # RZ/G2{L,LC}
+ - renesas,r9a07g054-dmac # RZ/V2L
+ - renesas,r9a08g045-dmac # RZ/G3S
+ - const: renesas,rz-dmac
+
+ - const: renesas,r9a09g057-dmac # RZ/V2H(P)
reg:
items:
- description: Control and channel register block
- description: DMA extended resource selector block
+ minItems: 1
interrupts:
maxItems: 17
@@ -52,6 +56,7 @@ properties:
items:
- description: DMA main clock
- description: DMA register access clock
+ minItems: 1
clock-names:
items:
@@ -61,14 +66,22 @@ properties:
'#dma-cells':
const: 1
description:
- The cell specifies the encoded MID/RID values of the DMAC port
- connected to the DMA client and the slave channel configuration
- parameters.
+ For the RZ/A1H, RZ/Five, RZ/G2{L,LC,UL}, RZ/V2L, and RZ/G3S SoCs, the cell
+ specifies the encoded MID/RID values of the DMAC port connected to the
+ DMA client and the slave channel configuration parameters.
bits[0:9] - Specifies MID/RID value
bit[10] - Specifies DMA request high enable (HIEN)
bit[11] - Specifies DMA request detection type (LVL)
bits[12:14] - Specifies DMAACK output mode (AM)
bit[15] - Specifies Transfer Mode (TM)
+ For the RZ/V2H(P) SoC the cell specifies the REQ NO, the ACK NO, and the
+ slave channel configuration parameters.
+ bits[0:9] - Specifies the REQ NO
+ bits[10:16] - Specifies the ACK NO
+ bit[17] - Specifies DMA request high enable (HIEN)
+ bit[18] - Specifies DMA request detection type (LVL)
+ bits[19:21] - Specifies DMAACK output mode (AM)
+ bit[22] - Specifies Transfer Mode (TM)
dma-channels:
const: 16
@@ -80,12 +93,29 @@ properties:
items:
- description: Reset for DMA ARESETN reset terminal
- description: Reset for DMA RST_ASYNC reset terminal
+ minItems: 1
reset-names:
items:
- const: arst
- const: rst_async
+ renesas,icu:
+ description:
+ On the RZ/V2H(P) SoC configures the ICU to which the DMAC is connected to.
+ It must contain the phandle to the ICU, and the index of the DMAC as seen
+ from the ICU (e.g. parameter k from register ICU_DMkSELy).
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to the ICU node.
+ - description: The DMAC index.
+ 4 for DMAC0
+ 0 for DMAC1
+ 1 for DMAC2
+ 2 for DMAC3
+ 3 for DMAC4
+
required:
- compatible
- reg
@@ -98,27 +128,62 @@ allOf:
- $ref: dma-controller.yaml#
- if:
- not:
- properties:
- compatible:
- contains:
- enum:
- - renesas,r7s72100-dmac
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g057-dmac
then:
+ properties:
+ reg:
+ maxItems: 1
+ clocks:
+ maxItems: 1
+ resets:
+ maxItems: 1
+
+ clock-names: false
+ reset-names: false
+
required:
- clocks
- - clock-names
- power-domains
+ - renesas,icu
- resets
- - reset-names
else:
- properties:
- clocks: false
- clock-names: false
- power-domains: false
- resets: false
- reset-names: false
+ if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r7s72100-dmac
+ then:
+ properties:
+ reg:
+ minItems: 2
+ clocks:
+ minItems: 2
+ resets:
+ minItems: 2
+
+ renesas,icu: false
+
+ required:
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - reset-names
+
+ else:
+ properties:
+ clocks: false
+ clock-names: false
+ power-domains: false
+ resets: false
+ reset-names: false
+ renesas,icu: false
additionalProperties: false
@@ -164,3 +229,40 @@ examples:
#dma-cells = <1>;
dma-channels = <16>;
};
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+ dmac0: dma-controller@11400000 {
+ compatible = "renesas,r9a09g057-dmac";
+ reg = <0x11400000 0x10000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x0>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x31>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 4>;
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 7/7] arm64: dts: renesas: r9a09g057: Add DMAC nodes
2025-02-06 22:03 [PATCH 0/7] Add DMAC support to the RZ/V2H(P) Fabrizio Castro
2025-02-06 22:03 ` [PATCH 2/7] dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H Fabrizio Castro
2025-02-06 22:03 ` [PATCH 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs Fabrizio Castro
@ 2025-02-06 22:03 ` Fabrizio Castro
2 siblings, 0 replies; 6+ messages in thread
From: Fabrizio Castro @ 2025-02-06 22:03 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven
Cc: Fabrizio Castro, Magnus Damm, linux-renesas-soc, devicetree,
linux-kernel, Biju Das, Lad Prabhakar
Add nodes for the DMAC IPs found on the Renesas RZ/V2H(P) SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 165 +++++++++++++++++++++
1 file changed, 165 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 1c550b22b164..0a7d0c801e32 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -252,6 +252,171 @@ sys: system-controller@10430000 {
status = "disabled";
};
+ dmac0: dma-controller@11400000 {
+ compatible = "renesas,r9a09g057-dmac";
+ reg = <0 0x11400000 0 0x10000>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x0>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x31>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 4>;
+ };
+
+ dmac1: dma-controller@14830000 {
+ compatible = "renesas,r9a09g057-dmac";
+ reg = <0 0x14830000 0 0x10000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x1>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x32>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 0>;
+ };
+
+ dmac2: dma-controller@14840000 {
+ compatible = "renesas,r9a09g057-dmac";
+ reg = <0 0x14840000 0 0x10000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x2>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x33>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 1>;
+ };
+
+ dmac3: dma-controller@12000000 {
+ compatible = "renesas,r9a09g057-dmac";
+ reg = <0 0x12000000 0 0x10000>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x3>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x34>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 2>;
+ };
+
+ dmac4: dma-controller@12010000 {
+ compatible = "renesas,r9a09g057-dmac";
+ reg = <0 0x12010000 0 0x10000>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 0x4>;
+ power-domains = <&cpg>;
+ resets = <&cpg 0x35>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,icu = <&icu 3>;
+ };
+
ostm0: timer@11800000 {
compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
reg = <0x0 0x11800000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
2025-02-06 22:03 ` [PATCH 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs Fabrizio Castro
@ 2025-02-11 22:26 ` Rob Herring
2025-02-12 18:27 ` Fabrizio Castro
0 siblings, 1 reply; 6+ messages in thread
From: Rob Herring @ 2025-02-11 22:26 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Vinod Koul, Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Biju Das, dmaengine, devicetree, linux-kernel,
linux-renesas-soc, Lad Prabhakar
On Thu, Feb 06, 2025 at 10:03:04PM +0000, Fabrizio Castro wrote:
> Document the Renesas RZ/V2H(P) family of SoCs DMAC block.
> The Renesas RZ/V2H(P) DMAC is very similar to the one found on the
> Renesas RZ/G2L family of SoCs, but there are some differences:
> * It only uses one register area
> * It only uses one clock
> * It only uses one reset
> * Instead of using MID/IRD it uses REQ NO/ACK NO
> * It is connected to the Interrupt Control Unit (ICU)
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
> .../bindings/dma/renesas,rz-dmac.yaml | 152 +++++++++++++++---
> 1 file changed, 127 insertions(+), 25 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> index 82de3b927479..d4dd22432e49 100644
> --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> @@ -11,19 +11,23 @@ maintainers:
>
> properties:
> compatible:
> - items:
> - - enum:
> - - renesas,r7s72100-dmac # RZ/A1H
> - - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
> - - renesas,r9a07g044-dmac # RZ/G2{L,LC}
> - - renesas,r9a07g054-dmac # RZ/V2L
> - - renesas,r9a08g045-dmac # RZ/G3S
> - - const: renesas,rz-dmac
> + oneOf:
> + - items:
> + - enum:
> + - renesas,r7s72100-dmac # RZ/A1H
> + - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
> + - renesas,r9a07g044-dmac # RZ/G2{L,LC}
> + - renesas,r9a07g054-dmac # RZ/V2L
> + - renesas,r9a08g045-dmac # RZ/G3S
> + - const: renesas,rz-dmac
> +
> + - const: renesas,r9a09g057-dmac # RZ/V2H(P)
>
> reg:
> items:
> - description: Control and channel register block
> - description: DMA extended resource selector block
> + minItems: 1
>
> interrupts:
> maxItems: 17
> @@ -52,6 +56,7 @@ properties:
> items:
> - description: DMA main clock
> - description: DMA register access clock
> + minItems: 1
>
> clock-names:
> items:
> @@ -61,14 +66,22 @@ properties:
> '#dma-cells':
> const: 1
> description:
> - The cell specifies the encoded MID/RID values of the DMAC port
> - connected to the DMA client and the slave channel configuration
> - parameters.
> + For the RZ/A1H, RZ/Five, RZ/G2{L,LC,UL}, RZ/V2L, and RZ/G3S SoCs, the cell
> + specifies the encoded MID/RID values of the DMAC port connected to the
> + DMA client and the slave channel configuration parameters.
> bits[0:9] - Specifies MID/RID value
> bit[10] - Specifies DMA request high enable (HIEN)
> bit[11] - Specifies DMA request detection type (LVL)
> bits[12:14] - Specifies DMAACK output mode (AM)
> bit[15] - Specifies Transfer Mode (TM)
> + For the RZ/V2H(P) SoC the cell specifies the REQ NO, the ACK NO, and the
> + slave channel configuration parameters.
> + bits[0:9] - Specifies the REQ NO
> + bits[10:16] - Specifies the ACK NO
> + bit[17] - Specifies DMA request high enable (HIEN)
> + bit[18] - Specifies DMA request detection type (LVL)
> + bits[19:21] - Specifies DMAACK output mode (AM)
> + bit[22] - Specifies Transfer Mode (TM)
>
> dma-channels:
> const: 16
> @@ -80,12 +93,29 @@ properties:
> items:
> - description: Reset for DMA ARESETN reset terminal
> - description: Reset for DMA RST_ASYNC reset terminal
> + minItems: 1
>
> reset-names:
> items:
> - const: arst
> - const: rst_async
>
> + renesas,icu:
> + description:
> + On the RZ/V2H(P) SoC configures the ICU to which the DMAC is connected to.
> + It must contain the phandle to the ICU, and the index of the DMAC as seen
> + from the ICU (e.g. parameter k from register ICU_DMkSELy).
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to the ICU node.
> + - description: The DMAC index.
> + 4 for DMAC0
> + 0 for DMAC1
> + 1 for DMAC2
> + 2 for DMAC3
> + 3 for DMAC4
> +
> required:
> - compatible
> - reg
> @@ -98,27 +128,62 @@ allOf:
> - $ref: dma-controller.yaml#
>
> - if:
> - not:
> - properties:
> - compatible:
> - contains:
> - enum:
> - - renesas,r7s72100-dmac
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a09g057-dmac
> then:
> + properties:
> + reg:
> + maxItems: 1
> + clocks:
> + maxItems: 1
> + resets:
> + maxItems: 1
> +
> + clock-names: false
> + reset-names: false
> +
> required:
> - clocks
> - - clock-names
> - power-domains
> + - renesas,icu
> - resets
> - - reset-names
>
> else:
> - properties:
> - clocks: false
> - clock-names: false
> - power-domains: false
> - resets: false
> - reset-names: false
> + if:
Please try to avoid nesting if/then/else. Not sure that's easy or not
here. This diff is hard to read.
> + not:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - renesas,r7s72100-dmac
> + then:
> + properties:
> + reg:
> + minItems: 2
> + clocks:
> + minItems: 2
> + resets:
> + minItems: 2
> +
> + renesas,icu: false
> +
> + required:
> + - clocks
> + - clock-names
> + - power-domains
> + - resets
> + - reset-names
> +
> + else:
> + properties:
> + clocks: false
> + clock-names: false
> + power-domains: false
> + resets: false
> + reset-names: false
> + renesas,icu: false
>
> additionalProperties: false
>
> @@ -164,3 +229,40 @@ examples:
> #dma-cells = <1>;
> dma-channels = <16>;
> };
> +
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> + dmac0: dma-controller@11400000 {
> + compatible = "renesas,r9a09g057-dmac";
Is this example really different enough from the others to need it? I
would drop it.
Rob
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
2025-02-11 22:26 ` Rob Herring
@ 2025-02-12 18:27 ` Fabrizio Castro
0 siblings, 0 replies; 6+ messages in thread
From: Fabrizio Castro @ 2025-02-12 18:27 UTC (permalink / raw)
To: Rob Herring
Cc: Vinod Koul, Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, Biju Das, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad
Hi Rob,
Thanks for your feedback!
> From: Rob Herring <robh@kernel.org>
> Sent: 11 February 2025 22:27
> Subject: Re: [PATCH 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
>
> On Thu, Feb 06, 2025 at 10:03:04PM +0000, Fabrizio Castro wrote:
> > Document the Renesas RZ/V2H(P) family of SoCs DMAC block.
> > The Renesas RZ/V2H(P) DMAC is very similar to the one found on the
> > Renesas RZ/G2L family of SoCs, but there are some differences:
> > * It only uses one register area
> > * It only uses one clock
> > * It only uses one reset
> > * Instead of using MID/IRD it uses REQ NO/ACK NO
> > * It is connected to the Interrupt Control Unit (ICU)
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > ---
> > .../bindings/dma/renesas,rz-dmac.yaml | 152 +++++++++++++++---
> > 1 file changed, 127 insertions(+), 25 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > index 82de3b927479..d4dd22432e49 100644
> > --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > @@ -11,19 +11,23 @@ maintainers:
> >
> > properties:
> > compatible:
> > - items:
> > - - enum:
> > - - renesas,r7s72100-dmac # RZ/A1H
> > - - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
> > - - renesas,r9a07g044-dmac # RZ/G2{L,LC}
> > - - renesas,r9a07g054-dmac # RZ/V2L
> > - - renesas,r9a08g045-dmac # RZ/G3S
> > - - const: renesas,rz-dmac
> > + oneOf:
> > + - items:
> > + - enum:
> > + - renesas,r7s72100-dmac # RZ/A1H
> > + - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
> > + - renesas,r9a07g044-dmac # RZ/G2{L,LC}
> > + - renesas,r9a07g054-dmac # RZ/V2L
> > + - renesas,r9a08g045-dmac # RZ/G3S
> > + - const: renesas,rz-dmac
> > +
> > + - const: renesas,r9a09g057-dmac # RZ/V2H(P)
> >
> > reg:
> > items:
> > - description: Control and channel register block
> > - description: DMA extended resource selector block
> > + minItems: 1
> >
> > interrupts:
> > maxItems: 17
> > @@ -52,6 +56,7 @@ properties:
> > items:
> > - description: DMA main clock
> > - description: DMA register access clock
> > + minItems: 1
> >
> > clock-names:
> > items:
> > @@ -61,14 +66,22 @@ properties:
> > '#dma-cells':
> > const: 1
> > description:
> > - The cell specifies the encoded MID/RID values of the DMAC port
> > - connected to the DMA client and the slave channel configuration
> > - parameters.
> > + For the RZ/A1H, RZ/Five, RZ/G2{L,LC,UL}, RZ/V2L, and RZ/G3S SoCs, the cell
> > + specifies the encoded MID/RID values of the DMAC port connected to the
> > + DMA client and the slave channel configuration parameters.
> > bits[0:9] - Specifies MID/RID value
> > bit[10] - Specifies DMA request high enable (HIEN)
> > bit[11] - Specifies DMA request detection type (LVL)
> > bits[12:14] - Specifies DMAACK output mode (AM)
> > bit[15] - Specifies Transfer Mode (TM)
> > + For the RZ/V2H(P) SoC the cell specifies the REQ NO, the ACK NO, and the
> > + slave channel configuration parameters.
> > + bits[0:9] - Specifies the REQ NO
> > + bits[10:16] - Specifies the ACK NO
> > + bit[17] - Specifies DMA request high enable (HIEN)
> > + bit[18] - Specifies DMA request detection type (LVL)
> > + bits[19:21] - Specifies DMAACK output mode (AM)
> > + bit[22] - Specifies Transfer Mode (TM)
> >
> > dma-channels:
> > const: 16
> > @@ -80,12 +93,29 @@ properties:
> > items:
> > - description: Reset for DMA ARESETN reset terminal
> > - description: Reset for DMA RST_ASYNC reset terminal
> > + minItems: 1
> >
> > reset-names:
> > items:
> > - const: arst
> > - const: rst_async
> >
> > + renesas,icu:
> > + description:
> > + On the RZ/V2H(P) SoC configures the ICU to which the DMAC is connected to.
> > + It must contain the phandle to the ICU, and the index of the DMAC as seen
> > + from the ICU (e.g. parameter k from register ICU_DMkSELy).
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + - items:
> > + - description: phandle to the ICU node.
> > + - description: The DMAC index.
> > + 4 for DMAC0
> > + 0 for DMAC1
> > + 1 for DMAC2
> > + 2 for DMAC3
> > + 3 for DMAC4
> > +
> > required:
> > - compatible
> > - reg
> > @@ -98,27 +128,62 @@ allOf:
> > - $ref: dma-controller.yaml#
> >
> > - if:
> > - not:
> > - properties:
> > - compatible:
> > - contains:
> > - enum:
> > - - renesas,r7s72100-dmac
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,r9a09g057-dmac
> > then:
> > + properties:
> > + reg:
> > + maxItems: 1
> > + clocks:
> > + maxItems: 1
> > + resets:
> > + maxItems: 1
> > +
> > + clock-names: false
> > + reset-names: false
> > +
> > required:
> > - clocks
> > - - clock-names
> > - power-domains
> > + - renesas,icu
> > - resets
> > - - reset-names
> >
> > else:
> > - properties:
> > - clocks: false
> > - clock-names: false
> > - power-domains: false
> > - resets: false
> > - reset-names: false
> > + if:
>
> Please try to avoid nesting if/then/else. Not sure that's easy or not
> here. This diff is hard to read.
I think I can use 3 if statements as opposed to nesting them, and I'll have to
explicitly list the platforms in order to cover all of the cases.
It should be a lot more readable, and hopefully simpler to maintain.
I'll send something across soon for you to look at.
>
> > + not:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - renesas,r7s72100-dmac
> > + then:
> > + properties:
> > + reg:
> > + minItems: 2
> > + clocks:
> > + minItems: 2
> > + resets:
> > + minItems: 2
> > +
> > + renesas,icu: false
> > +
> > + required:
> > + - clocks
> > + - clock-names
> > + - power-domains
> > + - resets
> > + - reset-names
> > +
> > + else:
> > + properties:
> > + clocks: false
> > + clock-names: false
> > + power-domains: false
> > + resets: false
> > + reset-names: false
> > + renesas,icu: false
> >
> > additionalProperties: false
> >
> > @@ -164,3 +229,40 @@ examples:
> > #dma-cells = <1>;
> > dma-channels = <16>;
> > };
> > +
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +
> > + dmac0: dma-controller@11400000 {
> > + compatible = "renesas,r9a09g057-dmac";
>
> Is this example really different enough from the others to need it? I
> would drop it.
I think the new example can be dropped in v2.
Thank you.
Cheers,
Fab
>
> Rob
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-02-12 18:27 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-06 22:03 [PATCH 0/7] Add DMAC support to the RZ/V2H(P) Fabrizio Castro
2025-02-06 22:03 ` [PATCH 2/7] dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H Fabrizio Castro
2025-02-06 22:03 ` [PATCH 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs Fabrizio Castro
2025-02-11 22:26 ` Rob Herring
2025-02-12 18:27 ` Fabrizio Castro
2025-02-06 22:03 ` [PATCH 7/7] arm64: dts: renesas: r9a09g057: Add DMAC nodes Fabrizio Castro
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