* [PATCH v4 01/11] dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles
2025-02-14 14:28 [PATCH v4 00/11] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Nick Chan
@ 2025-02-14 14:28 ` Nick Chan
2025-02-14 14:28 ` [PATCH v4 02/11] drivers/perf: apple_m1: Support per-implementation event tables Nick Chan
` (9 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-14 14:28 UTC (permalink / raw)
To: Will Deacon, Mark Rutland, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Catalin Marinas
Cc: Marc Zyngier, linux-arm-kernel, linux-perf-users, devicetree,
asahi, linux-kernel, Nick Chan, Krzysztof Kozlowski
Document the compatibles for Apple A7-A11 SoC CPU PMU.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
Documentation/devicetree/bindings/arm/pmu.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml
index a148ff54f2b8a92fa3fcfa78c1bcc525dba1c6dd..d2e7f19cf6a2d7d2348d163d37c2787c7a36bbd4 100644
--- a/Documentation/devicetree/bindings/arm/pmu.yaml
+++ b/Documentation/devicetree/bindings/arm/pmu.yaml
@@ -22,8 +22,14 @@ properties:
- apm,potenza-pmu
- apple,avalanche-pmu
- apple,blizzard-pmu
+ - apple,cyclone-pmu
- apple,firestorm-pmu
+ - apple,fusion-pmu
- apple,icestorm-pmu
+ - apple,monsoon-pmu
+ - apple,mistral-pmu
+ - apple,twister-pmu
+ - apple,typhoon-pmu
- arm,armv8-pmuv3 # Only for s/w models
- arm,arm1136-pmu
- arm,arm1176-pmu
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v4 02/11] drivers/perf: apple_m1: Support per-implementation event tables
2025-02-14 14:28 [PATCH v4 00/11] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Nick Chan
2025-02-14 14:28 ` [PATCH v4 01/11] dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles Nick Chan
@ 2025-02-14 14:28 ` Nick Chan
2025-02-14 14:28 ` [PATCH v4 03/11] drivers/perf: apple_m1: Support a per-implementation number of counters Nick Chan
` (8 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-14 14:28 UTC (permalink / raw)
To: Will Deacon, Mark Rutland, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Catalin Marinas
Cc: Marc Zyngier, linux-arm-kernel, linux-perf-users, devicetree,
asahi, linux-kernel, Nick Chan
Use per-implementation event tables to allow supporting implementations
with a different list of events and event affinities.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
drivers/perf/apple_m1_cpu_pmu.c | 65 +++++++++++++++++++++++++----------------
1 file changed, 40 insertions(+), 25 deletions(-)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index 06fd317529fcbab0f1485228efe8470be565407c..dfd5d72ce9f3c5bebd990b5df6a6823fb7785cce 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -42,9 +42,6 @@
* moment, we don't really need to distinguish between the two because we
* know next to nothing about the events themselves, and we already have
* per cpu-type PMU abstractions.
- *
- * If we eventually find out that the events are different across
- * implementations, we'll have to introduce per cpu-type tables.
*/
enum m1_pmu_events {
M1_PMU_PERFCTR_RETIRE_UOP = 0x1,
@@ -466,11 +463,12 @@ static void m1_pmu_write_counter(struct perf_event *event, u64 value)
isb();
}
-static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc,
- struct perf_event *event)
+static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc,
+ struct perf_event *event,
+ const u16 event_affinities[M1_PMU_CFG_EVENT])
{
unsigned long evtype = event->hw.config_base & M1_PMU_CFG_EVENT;
- unsigned long affinity = m1_pmu_event_affinity[evtype];
+ unsigned long affinity = event_affinities[evtype];
int idx;
/*
@@ -489,6 +487,12 @@ static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc,
return -EAGAIN;
}
+static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc,
+ struct perf_event *event)
+{
+ return apple_pmu_get_event_idx(cpuc, event, m1_pmu_event_affinity);
+}
+
static void m1_pmu_clear_event_idx(struct pmu_hw_events *cpuc,
struct perf_event *event)
{
@@ -516,7 +520,8 @@ static void m1_pmu_stop(struct arm_pmu *cpu_pmu)
__m1_pmu_set_mode(PMCR0_IMODE_OFF);
}
-static int m1_pmu_map_event(struct perf_event *event)
+static int apple_pmu_map_event_47(struct perf_event *event,
+ const unsigned int (*perf_map)[])
{
/*
* Although the counters are 48bit wide, bit 47 is what
@@ -524,18 +529,29 @@ static int m1_pmu_map_event(struct perf_event *event)
* being 47bit wide to mimick the behaviour of the ARM PMU.
*/
event->hw.flags |= ARMPMU_EVT_47BIT;
- return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT);
+ return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT);
}
-static int m2_pmu_map_event(struct perf_event *event)
+static int apple_pmu_map_event_63(struct perf_event *event,
+ const unsigned int (*perf_map)[])
{
/*
- * Same deal as the above, except that M2 has 64bit counters.
+ * Same deal as the above, except with 64bit counters.
* Which, as far as we're concerned, actually means 63 bits.
* Yes, this is getting awkward.
*/
event->hw.flags |= ARMPMU_EVT_63BIT;
- return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT);
+ return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT);
+}
+
+static int m1_pmu_map_event(struct perf_event *event)
+{
+ return apple_pmu_map_event_47(event, &m1_pmu_perf_map);
+}
+
+static int m2_pmu_map_event(struct perf_event *event)
+{
+ return apple_pmu_map_event_63(event, &m1_pmu_perf_map);
}
static void m1_pmu_reset(void *info)
@@ -572,25 +588,16 @@ static int m1_pmu_set_event_filter(struct hw_perf_event *event,
return 0;
}
-static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 flags)
+static int apple_pmu_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->handle_irq = m1_pmu_handle_irq;
cpu_pmu->enable = m1_pmu_enable_event;
cpu_pmu->disable = m1_pmu_disable_event;
cpu_pmu->read_counter = m1_pmu_read_counter;
cpu_pmu->write_counter = m1_pmu_write_counter;
- cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
cpu_pmu->clear_event_idx = m1_pmu_clear_event_idx;
cpu_pmu->start = m1_pmu_start;
cpu_pmu->stop = m1_pmu_stop;
-
- if (flags & ARMPMU_EVT_47BIT)
- cpu_pmu->map_event = m1_pmu_map_event;
- else if (flags & ARMPMU_EVT_63BIT)
- cpu_pmu->map_event = m2_pmu_map_event;
- else
- return WARN_ON(-EINVAL);
-
cpu_pmu->reset = m1_pmu_reset;
cpu_pmu->set_event_filter = m1_pmu_set_event_filter;
@@ -604,25 +611,33 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 flags)
static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->name = "apple_icestorm_pmu";
- return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT);
+ cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
+ cpu_pmu->map_event = m1_pmu_map_event;
+ return apple_pmu_init(cpu_pmu);
}
static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->name = "apple_firestorm_pmu";
- return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT);
+ cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
+ cpu_pmu->map_event = m1_pmu_map_event;
+ return apple_pmu_init(cpu_pmu);
}
static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->name = "apple_avalanche_pmu";
- return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT);
+ cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
+ cpu_pmu->map_event = m2_pmu_map_event;
+ return apple_pmu_init(cpu_pmu);
}
static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->name = "apple_blizzard_pmu";
- return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT);
+ cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
+ cpu_pmu->map_event = m2_pmu_map_event;
+ return apple_pmu_init(cpu_pmu);
}
static const struct of_device_id m1_pmu_of_device_ids[] = {
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v4 03/11] drivers/perf: apple_m1: Support a per-implementation number of counters
2025-02-14 14:28 [PATCH v4 00/11] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Nick Chan
2025-02-14 14:28 ` [PATCH v4 01/11] dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles Nick Chan
2025-02-14 14:28 ` [PATCH v4 02/11] drivers/perf: apple_m1: Support per-implementation event tables Nick Chan
@ 2025-02-14 14:28 ` Nick Chan
2025-02-14 14:28 ` [PATCH v4 04/11] drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 Nick Chan
` (7 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-14 14:28 UTC (permalink / raw)
To: Will Deacon, Mark Rutland, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Catalin Marinas
Cc: Marc Zyngier, linux-arm-kernel, linux-perf-users, devicetree,
asahi, linux-kernel, Nick Chan
Support a per-implementation number of counters to allow adding support
for implementations with less counters.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
drivers/perf/apple_m1_cpu_pmu.c | 31 ++++++++++++++++++++-----------
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index dfd5d72ce9f3c5bebd990b5df6a6823fb7785cce..bf397fd81230007dcf52888f148e3158dc02e29d 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -19,6 +19,7 @@
#include <asm/perf_event.h>
#define M1_PMU_NR_COUNTERS 10
+#define APPLE_PMU_MAX_NR_COUNTERS 10
#define M1_PMU_CFG_EVENT GENMASK(7, 0)
@@ -431,7 +432,7 @@ static irqreturn_t m1_pmu_handle_irq(struct arm_pmu *cpu_pmu)
regs = get_irq_regs();
- for_each_set_bit(idx, cpu_pmu->cntr_mask, M1_PMU_NR_COUNTERS) {
+ for_each_set_bit(idx, cpu_pmu->cntr_mask, APPLE_PMU_MAX_NR_COUNTERS) {
struct perf_event *event = cpuc->events[idx];
struct perf_sample_data data;
@@ -479,7 +480,7 @@ static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc,
* counting on the PMU at any given time, and by placing the
* most constraining events first.
*/
- for_each_set_bit(idx, &affinity, M1_PMU_NR_COUNTERS) {
+ for_each_set_bit(idx, &affinity, APPLE_PMU_MAX_NR_COUNTERS) {
if (!test_and_set_bit(idx, cpuc->used_mask))
return idx;
}
@@ -554,13 +555,13 @@ static int m2_pmu_map_event(struct perf_event *event)
return apple_pmu_map_event_63(event, &m1_pmu_perf_map);
}
-static void m1_pmu_reset(void *info)
+static void apple_pmu_reset(void *info, u32 counters)
{
int i;
__m1_pmu_set_mode(PMCR0_IMODE_OFF);
- for (i = 0; i < M1_PMU_NR_COUNTERS; i++) {
+ for (i = 0; i < counters; i++) {
m1_pmu_disable_counter(i);
m1_pmu_disable_counter_interrupt(i);
m1_pmu_write_hw_counter(0, i);
@@ -569,6 +570,11 @@ static void m1_pmu_reset(void *info)
isb();
}
+static void m1_pmu_reset(void *info)
+{
+ apple_pmu_reset(info, M1_PMU_NR_COUNTERS);
+}
+
static int m1_pmu_set_event_filter(struct hw_perf_event *event,
struct perf_event_attr *attr)
{
@@ -588,7 +594,7 @@ static int m1_pmu_set_event_filter(struct hw_perf_event *event,
return 0;
}
-static int apple_pmu_init(struct arm_pmu *cpu_pmu)
+static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters)
{
cpu_pmu->handle_irq = m1_pmu_handle_irq;
cpu_pmu->enable = m1_pmu_enable_event;
@@ -598,10 +604,9 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu)
cpu_pmu->clear_event_idx = m1_pmu_clear_event_idx;
cpu_pmu->start = m1_pmu_start;
cpu_pmu->stop = m1_pmu_stop;
- cpu_pmu->reset = m1_pmu_reset;
cpu_pmu->set_event_filter = m1_pmu_set_event_filter;
- bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS);
+ bitmap_set(cpu_pmu->cntr_mask, 0, counters);
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &m1_pmu_format_attr_group;
return 0;
@@ -613,7 +618,8 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
cpu_pmu->name = "apple_icestorm_pmu";
cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
cpu_pmu->map_event = m1_pmu_map_event;
- return apple_pmu_init(cpu_pmu);
+ cpu_pmu->reset = m1_pmu_reset;
+ return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
}
static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu)
@@ -621,7 +627,8 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu)
cpu_pmu->name = "apple_firestorm_pmu";
cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
cpu_pmu->map_event = m1_pmu_map_event;
- return apple_pmu_init(cpu_pmu);
+ cpu_pmu->reset = m1_pmu_reset;
+ return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
}
static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu)
@@ -629,7 +636,8 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu)
cpu_pmu->name = "apple_avalanche_pmu";
cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
cpu_pmu->map_event = m2_pmu_map_event;
- return apple_pmu_init(cpu_pmu);
+ cpu_pmu->reset = m1_pmu_reset;
+ return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
}
static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu)
@@ -637,7 +645,8 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu)
cpu_pmu->name = "apple_blizzard_pmu";
cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
cpu_pmu->map_event = m2_pmu_map_event;
- return apple_pmu_init(cpu_pmu);
+ cpu_pmu->reset = m1_pmu_reset;
+ return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
}
static const struct of_device_id m1_pmu_of_device_ids[] = {
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v4 04/11] drivers/perf: apple_m1: Support configuring counters for 32-bit EL0
2025-02-14 14:28 [PATCH v4 00/11] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Nick Chan
` (2 preceding siblings ...)
2025-02-14 14:28 ` [PATCH v4 03/11] drivers/perf: apple_m1: Support a per-implementation number of counters Nick Chan
@ 2025-02-14 14:28 ` Nick Chan
2025-02-14 14:28 ` [PATCH v4 05/11] drivers/perf: apple_m1: Support per-implementation PMU startup Nick Chan
` (6 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-14 14:28 UTC (permalink / raw)
To: Will Deacon, Mark Rutland, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Catalin Marinas
Cc: Marc Zyngier, linux-arm-kernel, linux-perf-users, devicetree,
asahi, linux-kernel, Nick Chan
Add support for configuring counters for 32-bit EL0 to allow adding support
for implementations with 32-bit EL0.
For documentation purposes, also add the bitmask for configuring counters
for 64-bit EL3.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
arch/arm64/include/asm/apple_m1_pmu.h | 3 +++
drivers/perf/apple_m1_cpu_pmu.c | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm/apple_m1_pmu.h
index 99483b19b99fca38483faad443ad4bcf4b85ef63..75be4b4c71f167a6874e22b38dc7c0bf30d25a47 100644
--- a/arch/arm64/include/asm/apple_m1_pmu.h
+++ b/arch/arm64/include/asm/apple_m1_pmu.h
@@ -37,8 +37,11 @@
#define PMCR0_PMI_ENABLE_8_9 GENMASK(45, 44)
#define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0)
+#define PMCR1_COUNT_A32_EL0_0_7 GENMASK(7, 0)
#define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8)
#define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16)
+#define PMCR1_COUNT_A64_EL3_0_7 GENMASK(31, 24)
+#define PMCR1_COUNT_A32_EL0_8_9 GENMASK(33, 32)
#define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40)
#define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index bf397fd81230007dcf52888f148e3158dc02e29d..73ba9861a15ff931b5e388b6d809dedb140e2292 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -335,10 +335,16 @@ static void m1_pmu_configure_counter(unsigned int index, u8 event,
case 0 ... 7:
user_bit = BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL0_0_7));
kernel_bit = BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL1_0_7));
+
+ if (system_supports_32bit_el0())
+ user_bit |= BIT(get_bit_offset(index, PMCR1_COUNT_A32_EL0_0_7));
break;
case 8 ... 9:
user_bit = BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL0_8_9));
kernel_bit = BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL1_8_9));
+
+ if (system_supports_32bit_el0())
+ user_bit |= BIT(get_bit_offset(index - 8, PMCR1_COUNT_A32_EL0_8_9));
break;
default:
BUG();
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v4 05/11] drivers/perf: apple_m1: Support per-implementation PMU startup
2025-02-14 14:28 [PATCH v4 00/11] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Nick Chan
` (3 preceding siblings ...)
2025-02-14 14:28 ` [PATCH v4 04/11] drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 Nick Chan
@ 2025-02-14 14:28 ` Nick Chan
2025-02-14 14:28 ` [PATCH v4 06/11] drivers/perf: apple_m1: Support per-implementation event attr group Nick Chan
` (5 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-14 14:28 UTC (permalink / raw)
To: Will Deacon, Mark Rutland, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Catalin Marinas
Cc: Marc Zyngier, linux-arm-kernel, linux-perf-users, devicetree,
asahi, linux-kernel, Nick Chan
Support for implementations that deliver its interrupts in ways other than
FIQ will be added, which requires a per-implementation startup function.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
drivers/perf/apple_m1_cpu_pmu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index 73ba9861a15ff931b5e388b6d809dedb140e2292..b601d585d204f9e59ad7f5216679b97852a46a04 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -608,7 +608,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters)
cpu_pmu->read_counter = m1_pmu_read_counter;
cpu_pmu->write_counter = m1_pmu_write_counter;
cpu_pmu->clear_event_idx = m1_pmu_clear_event_idx;
- cpu_pmu->start = m1_pmu_start;
cpu_pmu->stop = m1_pmu_stop;
cpu_pmu->set_event_filter = m1_pmu_set_event_filter;
@@ -625,6 +624,7 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
cpu_pmu->map_event = m1_pmu_map_event;
cpu_pmu->reset = m1_pmu_reset;
+ cpu_pmu->start = m1_pmu_start;
return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
}
@@ -634,6 +634,7 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu)
cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
cpu_pmu->map_event = m1_pmu_map_event;
cpu_pmu->reset = m1_pmu_reset;
+ cpu_pmu->start = m1_pmu_start;
return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
}
@@ -643,6 +644,7 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu)
cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
cpu_pmu->map_event = m2_pmu_map_event;
cpu_pmu->reset = m1_pmu_reset;
+ cpu_pmu->start = m1_pmu_start;
return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
}
@@ -652,6 +654,7 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu)
cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
cpu_pmu->map_event = m2_pmu_map_event;
cpu_pmu->reset = m1_pmu_reset;
+ cpu_pmu->start = m1_pmu_start;
return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
}
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v4 06/11] drivers/perf: apple_m1: Support per-implementation event attr group
2025-02-14 14:28 [PATCH v4 00/11] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Nick Chan
` (4 preceding siblings ...)
2025-02-14 14:28 ` [PATCH v4 05/11] drivers/perf: apple_m1: Support per-implementation PMU startup Nick Chan
@ 2025-02-14 14:28 ` Nick Chan
2025-02-14 14:28 ` [PATCH v4 07/11] drivers/perf: apple_m1: Add Apple A7 support Nick Chan
` (4 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-14 14:28 UTC (permalink / raw)
To: Will Deacon, Mark Rutland, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Catalin Marinas
Cc: Marc Zyngier, linux-arm-kernel, linux-perf-users, devicetree,
asahi, linux-kernel, Nick Chan
To support implementations with different event numbers for cycles or
instruction events, event attr groups needs to be per-implementation.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
drivers/perf/apple_m1_cpu_pmu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index b601d585d204f9e59ad7f5216679b97852a46a04..f98f3e95bfdbb5e9d0fe66357f6037f056fbf25c 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -612,7 +612,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters)
cpu_pmu->set_event_filter = m1_pmu_set_event_filter;
bitmap_set(cpu_pmu->cntr_mask, 0, counters);
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &m1_pmu_format_attr_group;
return 0;
}
@@ -625,6 +624,7 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
cpu_pmu->map_event = m1_pmu_map_event;
cpu_pmu->reset = m1_pmu_reset;
cpu_pmu->start = m1_pmu_start;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
}
@@ -635,6 +635,7 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu)
cpu_pmu->map_event = m1_pmu_map_event;
cpu_pmu->reset = m1_pmu_reset;
cpu_pmu->start = m1_pmu_start;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
}
@@ -645,6 +646,7 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu)
cpu_pmu->map_event = m2_pmu_map_event;
cpu_pmu->reset = m1_pmu_reset;
cpu_pmu->start = m1_pmu_start;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
}
@@ -655,6 +657,7 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu)
cpu_pmu->map_event = m2_pmu_map_event;
cpu_pmu->reset = m1_pmu_reset;
cpu_pmu->start = m1_pmu_start;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
}
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v4 07/11] drivers/perf: apple_m1: Add Apple A7 support
2025-02-14 14:28 [PATCH v4 00/11] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Nick Chan
` (5 preceding siblings ...)
2025-02-14 14:28 ` [PATCH v4 06/11] drivers/perf: apple_m1: Support per-implementation event attr group Nick Chan
@ 2025-02-14 14:28 ` Nick Chan
2025-02-14 14:28 ` [PATCH v4 08/11] drivers/perf: apple_m1: Add Apple A8/A8X support Nick Chan
` (3 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-14 14:28 UTC (permalink / raw)
To: Will Deacon, Mark Rutland, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Catalin Marinas
Cc: Marc Zyngier, linux-arm-kernel, linux-perf-users, devicetree,
asahi, linux-kernel, Nick Chan
Add support for the CPU PMU found in the Apple A7 SoC. The PMU has 8
counters and a very different event layout compared to the M1 PMU.
Interrupts are delivered as IRQs instead of FIQs like on the M1.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
drivers/perf/apple_m1_cpu_pmu.c | 190 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 190 insertions(+)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index f98f3e95bfdbb5e9d0fe66357f6037f056fbf25c..93b49f08e5c740c5bba2eede191e279ed4965181 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -18,6 +18,7 @@
#include <asm/irq_regs.h>
#include <asm/perf_event.h>
+#define A7_PMU_NR_COUNTERS 8
#define M1_PMU_NR_COUNTERS 10
#define APPLE_PMU_MAX_NR_COUNTERS 10
@@ -44,6 +45,143 @@
* know next to nothing about the events themselves, and we already have
* per cpu-type PMU abstractions.
*/
+
+enum a7_pmu_events {
+ A7_PMU_PERFCTR_INST_ALL = 0x0,
+ A7_PMU_PERFCTR_UNKNOWN_1 = 0x1,
+ A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
+ A7_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0x10,
+ A7_PMU_PERFCTR_L2_TLB_MISS_DATA = 0x11,
+ A7_PMU_PERFCTR_BIU_UPSTREAM_CYCLE = 0x19,
+ A7_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE = 0x20,
+ A7_PMU_PERFCTR_L2C_AGENT_LD = 0x22,
+ A7_PMU_PERFCTR_L2C_AGENT_LD_MISS = 0x23,
+ A7_PMU_PERFCTR_L2C_AGENT_ST = 0x24,
+ A7_PMU_PERFCTR_L2C_AGENT_ST_MISS = 0x25,
+ A7_PMU_PERFCTR_SCHEDULE_UOP = 0x58,
+ A7_PMU_PERFCTR_MAP_REWIND = 0x61,
+ A7_PMU_PERFCTR_MAP_STALL = 0x62,
+ A7_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x6e,
+ A7_PMU_PERFCTR_INST_A32 = 0x78,
+ A7_PMU_PERFCTR_INST_T32 = 0x79,
+ A7_PMU_PERFCTR_INST_A64 = 0x7a,
+ A7_PMU_PERFCTR_INST_BRANCH = 0x7b,
+ A7_PMU_PERFCTR_INST_BRANCH_CALL = 0x7c,
+ A7_PMU_PERFCTR_INST_BRANCH_RET = 0x7d,
+ A7_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x7e,
+ A7_PMU_PERFCTR_INST_BRANCH_INDIR = 0x81,
+ A7_PMU_PERFCTR_INST_BRANCH_COND = 0x82,
+ A7_PMU_PERFCTR_INST_INT_LD = 0x83,
+ A7_PMU_PERFCTR_INST_INT_ST = 0x84,
+ A7_PMU_PERFCTR_INST_INT_ALU = 0x85,
+ A7_PMU_PERFCTR_INST_SIMD_LD = 0x86,
+ A7_PMU_PERFCTR_INST_SIMD_ST = 0x87,
+ A7_PMU_PERFCTR_INST_SIMD_ALU = 0x88,
+ A7_PMU_PERFCTR_INST_LDST = 0x89,
+ A7_PMU_PERFCTR_UNKNOWN_8d = 0x8d,
+ A7_PMU_PERFCTR_UNKNOWN_8e = 0x8e,
+ A7_PMU_PERFCTR_UNKNOWN_8f = 0x8f,
+ A7_PMU_PERFCTR_UNKNOWN_90 = 0x90,
+ A7_PMU_PERFCTR_UNKNOWN_93 = 0x93,
+ A7_PMU_PERFCTR_UNKNOWN_94 = 0x94,
+ A7_PMU_PERFCTR_UNKNOWN_95 = 0x95,
+ A7_PMU_PERFCTR_L1D_TLB_ACCESS = 0x96,
+ A7_PMU_PERFCTR_L1D_TLB_MISS = 0x97,
+ A7_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0x98,
+ A7_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0x99,
+ A7_PMU_PERFCTR_UNKNOWN_9b = 0x9b,
+ A7_PMU_PERFCTR_LD_UNIT_UOP = 0x9c,
+ A7_PMU_PERFCTR_ST_UNIT_UOP = 0x9d,
+ A7_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0x9e,
+ A7_PMU_PERFCTR_UNKNOWN_9f = 0x9f,
+ A7_PMU_PERFCTR_LDST_X64_UOP = 0xa7,
+ A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xb4,
+ A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xb5,
+ A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xb6,
+ A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xb9,
+ A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xba,
+ A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xbb,
+ A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xbd,
+ A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xbf,
+ A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xc0,
+ A7_PMU_PERFCTR_UNKNOWN_c1 = 0xc1,
+ A7_PMU_PERFCTR_UNKNOWN_c4 = 0xc4,
+ A7_PMU_PERFCTR_UNKNOWN_c5 = 0xc5,
+ A7_PMU_PERFCTR_UNKNOWN_c6 = 0xc6,
+ A7_PMU_PERFCTR_UNKNOWN_c8 = 0xc8,
+ A7_PMU_PERFCTR_UNKNOWN_ca = 0xca,
+ A7_PMU_PERFCTR_UNKNOWN_cb = 0xcb,
+ A7_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xce,
+ A7_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xcf,
+ A7_PMU_PERFCTR_UNKNOWN_f5 = 0xf5,
+ A7_PMU_PERFCTR_UNKNOWN_f6 = 0xf6,
+ A7_PMU_PERFCTR_UNKNOWN_f7 = 0xf7,
+ A7_PMU_PERFCTR_UNKNOWN_f8 = 0xf8,
+ A7_PMU_PERFCTR_UNKNOWN_fd = 0xfd,
+ A7_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT,
+ /*
+ * From this point onwards, these are not actual HW events,
+ * but attributes that get stored in hw->config_base.
+ */
+ A7_PMU_CFG_COUNT_USER = BIT(8),
+ A7_PMU_CFG_COUNT_KERNEL = BIT(9),
+};
+
+static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR_LAST + 1] = {
+ [0 ... A7_PMU_PERFCTR_LAST] = ANY_BUT_0_1,
+ [A7_PMU_PERFCTR_INST_ALL] = ANY_BUT_0_1 | BIT(1),
+ [A7_PMU_PERFCTR_UNKNOWN_1] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0),
+ [A7_PMU_PERFCTR_INST_A32] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_T32] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_A64] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_INT_ALU] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_SIMD_ALU] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_8d] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_8e] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_8f] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_90] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_93] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_94] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_95] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_9b] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_LD_UNIT_UOP] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_9f] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_c1] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_c4] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_c5] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_c6] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_c8] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_ca] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_cb] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6,
+ [A7_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6,
+ [A7_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6,
+ [A7_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
+};
+
enum m1_pmu_events {
M1_PMU_PERFCTR_RETIRE_UOP = 0x1,
M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
@@ -162,6 +300,14 @@ static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_LAST + 1] = {
[M1_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
};
+static const unsigned int a7_pmu_perf_map[PERF_COUNT_HW_MAX] = {
+ PERF_MAP_ALL_UNSUPPORTED,
+ [PERF_COUNT_HW_CPU_CYCLES] = A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE,
+ [PERF_COUNT_HW_INSTRUCTIONS] = A7_PMU_PERFCTR_INST_ALL,
+ [PERF_COUNT_HW_BRANCH_MISSES] = A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = A7_PMU_PERFCTR_INST_BRANCH
+};
+
static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] = {
PERF_MAP_ALL_UNSUPPORTED,
[PERF_COUNT_HW_CPU_CYCLES] = M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE,
@@ -185,6 +331,17 @@ static ssize_t m1_pmu_events_sysfs_show(struct device *dev,
#define M1_PMU_EVENT_ATTR(name, config) \
PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config)
+static struct attribute *a7_pmu_event_attrs[] = {
+ M1_PMU_EVENT_ATTR(cycles, A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE),
+ M1_PMU_EVENT_ATTR(instructions, A7_PMU_PERFCTR_INST_ALL),
+ NULL,
+};
+
+static const struct attribute_group a7_pmu_events_attr_group = {
+ .name = "events",
+ .attrs = a7_pmu_event_attrs,
+};
+
static struct attribute *m1_pmu_event_attrs[] = {
M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE),
M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INST_ALL),
@@ -494,6 +651,12 @@ static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc,
return -EAGAIN;
}
+static int a7_pmu_get_event_idx(struct pmu_hw_events *cpuc,
+ struct perf_event *event)
+{
+ return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity);
+}
+
static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc,
struct perf_event *event)
{
@@ -517,6 +680,11 @@ static void __m1_pmu_set_mode(u8 mode)
isb();
}
+static void a7_pmu_start(struct arm_pmu *cpu_pmu)
+{
+ __m1_pmu_set_mode(PMCR0_IMODE_AIC);
+}
+
static void m1_pmu_start(struct arm_pmu *cpu_pmu)
{
__m1_pmu_set_mode(PMCR0_IMODE_FIQ);
@@ -551,6 +719,11 @@ static int apple_pmu_map_event_63(struct perf_event *event,
return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT);
}
+static int a7_pmu_map_event(struct perf_event *event)
+{
+ return apple_pmu_map_event_47(event, &a7_pmu_perf_map);
+}
+
static int m1_pmu_map_event(struct perf_event *event)
{
return apple_pmu_map_event_47(event, &m1_pmu_perf_map);
@@ -576,6 +749,11 @@ static void apple_pmu_reset(void *info, u32 counters)
isb();
}
+static void a7_pmu_reset(void *info)
+{
+ apple_pmu_reset(info, A7_PMU_NR_COUNTERS);
+}
+
static void m1_pmu_reset(void *info)
{
apple_pmu_reset(info, M1_PMU_NR_COUNTERS);
@@ -617,6 +795,17 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters)
}
/* Device driver gunk */
+static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu)
+{
+ cpu_pmu->name = "apple_cyclone_pmu";
+ cpu_pmu->get_event_idx = a7_pmu_get_event_idx;
+ cpu_pmu->map_event = a7_pmu_map_event;
+ cpu_pmu->reset = a7_pmu_reset;
+ cpu_pmu->start = a7_pmu_start;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &a7_pmu_events_attr_group;
+ return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS);
+}
+
static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->name = "apple_icestorm_pmu";
@@ -666,6 +855,7 @@ static const struct of_device_id m1_pmu_of_device_ids[] = {
{ .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, },
{ .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, },
{ .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, },
+ { .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, },
{ },
};
MODULE_DEVICE_TABLE(of, m1_pmu_of_device_ids);
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v4 08/11] drivers/perf: apple_m1: Add Apple A8/A8X support
2025-02-14 14:28 [PATCH v4 00/11] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Nick Chan
` (6 preceding siblings ...)
2025-02-14 14:28 ` [PATCH v4 07/11] drivers/perf: apple_m1: Add Apple A7 support Nick Chan
@ 2025-02-14 14:28 ` Nick Chan
2025-02-14 14:28 ` [PATCH v4 09/11] drivers/perf: apple_m1: Add A9/A9X support Nick Chan
` (2 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-14 14:28 UTC (permalink / raw)
To: Will Deacon, Mark Rutland, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Catalin Marinas
Cc: Marc Zyngier, linux-arm-kernel, linux-perf-users, devicetree,
asahi, linux-kernel, Nick Chan
Add support for the CPU PMU found on the Apple A8, A8X SoCs.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
drivers/perf/apple_m1_cpu_pmu.c | 124 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 124 insertions(+)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index 93b49f08e5c740c5bba2eede191e279ed4965181..04825a1991ab1c670563e3ce91b43fa5d8c85920 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -27,6 +27,7 @@
#define ANY_BUT_0_1 GENMASK(9, 2)
#define ONLY_2_TO_7 GENMASK(7, 2)
#define ONLY_2_4_6 (BIT(2) | BIT(4) | BIT(6))
+#define ONLY_3_5_7 (BIT(3) | BIT(5) | BIT(7))
#define ONLY_5_6_7 (BIT(5) | BIT(6) | BIT(7))
/*
@@ -182,6 +183,111 @@ static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR_LAST + 1] = {
[A7_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
};
+enum a8_pmu_events {
+ A8_PMU_PERFCTR_UNKNOWN_1 = 0x1,
+ A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
+ A8_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa,
+ A8_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb,
+ A8_PMU_PERFCTR_BIU_UPSTREAM_CYCLE = 0x13,
+ A8_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE = 0x14,
+ A8_PMU_PERFCTR_L2C_AGENT_LD = 0x1a,
+ A8_PMU_PERFCTR_L2C_AGENT_LD_MISS = 0x1b,
+ A8_PMU_PERFCTR_L2C_AGENT_ST = 0x1c,
+ A8_PMU_PERFCTR_L2C_AGENT_ST_MISS = 0x1d,
+ A8_PMU_PERFCTR_SCHEDULE_UOP = 0x52,
+ A8_PMU_PERFCTR_MAP_REWIND = 0x75,
+ A8_PMU_PERFCTR_MAP_STALL = 0x76,
+ A8_PMU_PERFCTR_MAP_INT_UOP = 0x7b,
+ A8_PMU_PERFCTR_MAP_LDST_UOP = 0x7c,
+ A8_PMU_PERFCTR_MAP_SIMD_UOP = 0x7d,
+ A8_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84,
+ A8_PMU_PERFCTR_INST_A32 = 0x8a,
+ A8_PMU_PERFCTR_INST_T32 = 0x8b,
+ A8_PMU_PERFCTR_INST_ALL = 0x8c,
+ A8_PMU_PERFCTR_INST_BRANCH = 0x8d,
+ A8_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e,
+ A8_PMU_PERFCTR_INST_BRANCH_RET = 0x8f,
+ A8_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90,
+ A8_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93,
+ A8_PMU_PERFCTR_INST_BRANCH_COND = 0x94,
+ A8_PMU_PERFCTR_INST_INT_LD = 0x95,
+ A8_PMU_PERFCTR_INST_INT_ST = 0x96,
+ A8_PMU_PERFCTR_INST_INT_ALU = 0x97,
+ A8_PMU_PERFCTR_INST_SIMD_LD = 0x98,
+ A8_PMU_PERFCTR_INST_SIMD_ST = 0x99,
+ A8_PMU_PERFCTR_INST_SIMD_ALU = 0x9a,
+ A8_PMU_PERFCTR_INST_LDST = 0x9b,
+ A8_PMU_PERFCTR_UNKNOWN_9c = 0x9c,
+ A8_PMU_PERFCTR_UNKNOWN_9f = 0x9f,
+ A8_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0,
+ A8_PMU_PERFCTR_L1D_TLB_MISS = 0xa1,
+ A8_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2,
+ A8_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3,
+ A8_PMU_PERFCTR_LD_UNIT_UOP = 0xa6,
+ A8_PMU_PERFCTR_ST_UNIT_UOP = 0xa7,
+ A8_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8,
+ A8_PMU_PERFCTR_LDST_X64_UOP = 0xb1,
+ A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf,
+ A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0,
+ A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1,
+ A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4,
+ A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5,
+ A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6,
+ A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8,
+ A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca,
+ A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb,
+ A8_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xd3,
+ A8_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4,
+ A8_PMU_PERFCTR_FETCH_RESTART = 0xde,
+ A8_PMU_PERFCTR_UNKNOWN_f5 = 0xf5,
+ A8_PMU_PERFCTR_UNKNOWN_f6 = 0xf6,
+ A8_PMU_PERFCTR_UNKNOWN_f7 = 0xf7,
+ A8_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT,
+
+ /*
+ * From this point onwards, these are not actual HW events,
+ * but attributes that get stored in hw->config_base.
+ */
+ A8_PMU_CFG_COUNT_USER = BIT(8),
+ A8_PMU_CFG_COUNT_KERNEL = BIT(9),
+};
+
+static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR_LAST + 1] = {
+ [0 ... A8_PMU_PERFCTR_LAST] = ANY_BUT_0_1,
+ [A8_PMU_PERFCTR_UNKNOWN_1] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0),
+ [A8_PMU_PERFCTR_INST_A32] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_T32] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1),
+ [A8_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_INT_ALU] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_SIMD_ALU] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_UNKNOWN_9c] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_UNKNOWN_9f] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A8_PMU_PERFCTR_UNKNOWN_f5] = ANY_BUT_0_1,
+ [A8_PMU_PERFCTR_UNKNOWN_f6] = ONLY_3_5_7,
+ [A8_PMU_PERFCTR_UNKNOWN_f7] = ONLY_3_5_7,
+};
+
enum m1_pmu_events {
M1_PMU_PERFCTR_RETIRE_UOP = 0x1,
M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
@@ -657,6 +763,12 @@ static int a7_pmu_get_event_idx(struct pmu_hw_events *cpuc,
return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity);
}
+static int a8_pmu_get_event_idx(struct pmu_hw_events *cpuc,
+ struct perf_event *event)
+{
+ return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity);
+}
+
static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc,
struct perf_event *event)
{
@@ -806,6 +918,17 @@ static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu)
return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS);
}
+static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pmu)
+{
+ cpu_pmu->name = "apple_typhoon_pmu";
+ cpu_pmu->get_event_idx = a8_pmu_get_event_idx;
+ cpu_pmu->map_event = m1_pmu_map_event;
+ cpu_pmu->reset = a7_pmu_reset;
+ cpu_pmu->start = a7_pmu_start;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
+ return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS);
+}
+
static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->name = "apple_icestorm_pmu";
@@ -855,6 +978,7 @@ static const struct of_device_id m1_pmu_of_device_ids[] = {
{ .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, },
{ .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, },
{ .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, },
+ { .compatible = "apple,typhoon-pmu", .data = a8_pmu_typhoon_init, },
{ .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, },
{ },
};
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v4 09/11] drivers/perf: apple_m1: Add A9/A9X support
2025-02-14 14:28 [PATCH v4 00/11] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Nick Chan
` (7 preceding siblings ...)
2025-02-14 14:28 ` [PATCH v4 08/11] drivers/perf: apple_m1: Add Apple A8/A8X support Nick Chan
@ 2025-02-14 14:28 ` Nick Chan
2025-02-14 14:28 ` [PATCH v4 10/11] drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support Nick Chan
2025-02-14 14:28 ` [PATCH v4 11/11] drivers/perf: apple_m1: Add Apple A11 Support Nick Chan
10 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-14 14:28 UTC (permalink / raw)
To: Will Deacon, Mark Rutland, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Catalin Marinas
Cc: Marc Zyngier, linux-arm-kernel, linux-perf-users, devicetree,
asahi, linux-kernel, Nick Chan
Add support for CPU PMU found in the Apple A9 and A9X SoCs.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
drivers/perf/apple_m1_cpu_pmu.c | 121 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index 04825a1991ab1c670563e3ce91b43fa5d8c85920..f7ae5cd56980b75d8f2073368479d0af77ab351c 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -288,6 +288,109 @@ static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR_LAST + 1] = {
[A8_PMU_PERFCTR_UNKNOWN_f7] = ONLY_3_5_7,
};
+
+enum a9_pmu_events {
+ A9_PMU_PERFCTR_UNKNOWN_1 = 0x1,
+ A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
+ A9_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa,
+ A9_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb,
+ A9_PMU_PERFCTR_L2C_AGENT_LD = 0x1a,
+ A9_PMU_PERFCTR_L2C_AGENT_LD_MISS = 0x1b,
+ A9_PMU_PERFCTR_L2C_AGENT_ST = 0x1c,
+ A9_PMU_PERFCTR_L2C_AGENT_ST_MISS = 0x1d,
+ A9_PMU_PERFCTR_SCHEDULE_UOP = 0x52,
+ A9_PMU_PERFCTR_MAP_REWIND = 0x75,
+ A9_PMU_PERFCTR_MAP_STALL = 0x76,
+ A9_PMU_PERFCTR_MAP_INT_UOP = 0x7c,
+ A9_PMU_PERFCTR_MAP_LDST_UOP = 0x7d,
+ A9_PMU_PERFCTR_MAP_SIMD_UOP = 0x7e,
+ A9_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84,
+ A9_PMU_PERFCTR_INST_ALL = 0x8c,
+ A9_PMU_PERFCTR_INST_BRANCH = 0x8d,
+ A9_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e,
+ A9_PMU_PERFCTR_INST_BRANCH_RET = 0x8f,
+ A9_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90,
+ A9_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93,
+ A9_PMU_PERFCTR_INST_BRANCH_COND = 0x94,
+ A9_PMU_PERFCTR_INST_INT_LD = 0x95,
+ A9_PMU_PERFCTR_INST_INT_ST = 0x96,
+ A9_PMU_PERFCTR_INST_INT_ALU = 0x97,
+ A9_PMU_PERFCTR_INST_SIMD_LD = 0x98,
+ A9_PMU_PERFCTR_INST_SIMD_ST = 0x99,
+ A9_PMU_PERFCTR_INST_SIMD_ALU = 0x9a,
+ A9_PMU_PERFCTR_INST_LDST = 0x9b,
+ A9_PMU_PERFCTR_INST_BARRIER = 0x9c,
+ A9_PMU_PERFCTR_UNKNOWN_9f = 0x9f,
+ A9_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0,
+ A9_PMU_PERFCTR_L1D_TLB_MISS = 0xa1,
+ A9_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2,
+ A9_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3,
+ A9_PMU_PERFCTR_LD_UNIT_UOP = 0xa6,
+ A9_PMU_PERFCTR_ST_UNIT_UOP = 0xa7,
+ A9_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8,
+ A9_PMU_PERFCTR_LDST_X64_UOP = 0xb1,
+ A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC = 0xb3,
+ A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL = 0xb4,
+ A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf,
+ A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0,
+ A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1,
+ A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4,
+ A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5,
+ A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6,
+ A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8,
+ A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca,
+ A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb,
+ A9_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xd3,
+ A9_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4,
+ A9_PMU_PERFCTR_MAP_DISPATCH_BUBBLE = 0xd6,
+ A9_PMU_PERFCTR_FETCH_RESTART = 0xde,
+ A9_PMU_PERFCTR_ST_NT_UOP = 0xe5,
+ A9_PMU_PERFCTR_LD_NT_UOP = 0xe6,
+ A9_PMU_PERFCTR_UNKNOWN_f6 = 0xf6,
+ A9_PMU_PERFCTR_UNKNOWN_f7 = 0xf7,
+ A9_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT,
+
+ /*
+ * From this point onwards, these are not actual HW events,
+ * but attributes that get stored in hw->config_base.
+ */
+ A9_PMU_CFG_COUNT_USER = BIT(8),
+ A9_PMU_CFG_COUNT_KERNEL = BIT(9),
+};
+
+static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR_LAST + 1] = {
+ [0 ... A9_PMU_PERFCTR_LAST] = ANY_BUT_0_1,
+ [A9_PMU_PERFCTR_UNKNOWN_1] = BIT(7),
+ [A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0),
+ [A9_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1),
+ [A9_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_INST_INT_ALU] = BIT(7),
+ [A9_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_INST_SIMD_ALU] = BIT(7),
+ [A9_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_INST_BARRIER] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_UNKNOWN_9f] = BIT(7),
+ [A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A9_PMU_PERFCTR_UNKNOWN_f6] = ONLY_3_5_7,
+ [A9_PMU_PERFCTR_UNKNOWN_f7] = ONLY_3_5_7,
+};
+
enum m1_pmu_events {
M1_PMU_PERFCTR_RETIRE_UOP = 0x1,
M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
@@ -769,6 +872,12 @@ static int a8_pmu_get_event_idx(struct pmu_hw_events *cpuc,
return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity);
}
+static int a9_pmu_get_event_idx(struct pmu_hw_events *cpuc,
+ struct perf_event *event)
+{
+ return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity);
+}
+
static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc,
struct perf_event *event)
{
@@ -929,6 +1038,17 @@ static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pmu)
return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS);
}
+static int a9_pmu_twister_init(struct arm_pmu *cpu_pmu)
+{
+ cpu_pmu->name = "apple_twister_pmu";
+ cpu_pmu->get_event_idx = a9_pmu_get_event_idx;
+ cpu_pmu->map_event = m1_pmu_map_event;
+ cpu_pmu->reset = a7_pmu_reset;
+ cpu_pmu->start = a7_pmu_start;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
+ return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS);
+}
+
static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->name = "apple_icestorm_pmu";
@@ -978,6 +1098,7 @@ static const struct of_device_id m1_pmu_of_device_ids[] = {
{ .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, },
{ .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, },
{ .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, },
+ { .compatible = "apple,twister-pmu", .data = a9_pmu_twister_init, },
{ .compatible = "apple,typhoon-pmu", .data = a8_pmu_typhoon_init, },
{ .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, },
{ },
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v4 10/11] drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support
2025-02-14 14:28 [PATCH v4 00/11] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Nick Chan
` (8 preceding siblings ...)
2025-02-14 14:28 ` [PATCH v4 09/11] drivers/perf: apple_m1: Add A9/A9X support Nick Chan
@ 2025-02-14 14:28 ` Nick Chan
2025-02-14 14:28 ` [PATCH v4 11/11] drivers/perf: apple_m1: Add Apple A11 Support Nick Chan
10 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-14 14:28 UTC (permalink / raw)
To: Will Deacon, Mark Rutland, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Catalin Marinas
Cc: Marc Zyngier, linux-arm-kernel, linux-perf-users, devicetree,
asahi, linux-kernel, Nick Chan
Add support for the CPU PMU found in the Apple A10, A10X, T2 SoCs.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
drivers/perf/apple_m1_cpu_pmu.c | 127 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 127 insertions(+)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index f7ae5cd56980b75d8f2073368479d0af77ab351c..e66ec1426f5d9d48ef52abd539acff7648958785 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -391,6 +391,115 @@ static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR_LAST + 1] = {
[A9_PMU_PERFCTR_UNKNOWN_f7] = ONLY_3_5_7,
};
+enum a10_pmu_events {
+ A10_PMU_PERFCTR_RETIRE_UOP = 0x1,
+ A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
+ A10_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa,
+ A10_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb,
+ A10_PMU_PERFCTR_L2C_AGENT_LD = 0x1a,
+ A10_PMU_PERFCTR_L2C_AGENT_LD_MISS = 0x1b,
+ A10_PMU_PERFCTR_L2C_AGENT_ST = 0x1c,
+ A10_PMU_PERFCTR_L2C_AGENT_ST_MISS = 0x1d,
+ A10_PMU_PERFCTR_SCHEDULE_UOP = 0x52,
+ A10_PMU_PERFCTR_MAP_REWIND = 0x75,
+ A10_PMU_PERFCTR_MAP_STALL = 0x76,
+ A10_PMU_PERFCTR_MAP_INT_UOP = 0x7c,
+ A10_PMU_PERFCTR_MAP_LDST_UOP = 0x7d,
+ A10_PMU_PERFCTR_MAP_SIMD_UOP = 0x7e,
+ A10_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84,
+ A10_PMU_PERFCTR_INST_ALL = 0x8c,
+ A10_PMU_PERFCTR_INST_BRANCH = 0x8d,
+ A10_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e,
+ A10_PMU_PERFCTR_INST_BRANCH_RET = 0x8f,
+ A10_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90,
+ A10_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93,
+ A10_PMU_PERFCTR_INST_BRANCH_COND = 0x94,
+ A10_PMU_PERFCTR_INST_INT_LD = 0x95,
+ A10_PMU_PERFCTR_INST_INT_ST = 0x96,
+ A10_PMU_PERFCTR_INST_INT_ALU = 0x97,
+ A10_PMU_PERFCTR_INST_SIMD_LD = 0x98,
+ A10_PMU_PERFCTR_INST_SIMD_ST = 0x99,
+ A10_PMU_PERFCTR_INST_SIMD_ALU = 0x9a,
+ A10_PMU_PERFCTR_INST_LDST = 0x9b,
+ A10_PMU_PERFCTR_INST_BARRIER = 0x9c,
+ A10_PMU_PERFCTR_UNKNOWN_9f = 0x9f,
+ A10_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0,
+ A10_PMU_PERFCTR_L1D_TLB_MISS = 0xa1,
+ A10_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2,
+ A10_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3,
+ A10_PMU_PERFCTR_LD_UNIT_UOP = 0xa6,
+ A10_PMU_PERFCTR_ST_UNIT_UOP = 0xa7,
+ A10_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8,
+ A10_PMU_PERFCTR_LDST_X64_UOP = 0xb1,
+ A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC = 0xb3,
+ A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL = 0xb4,
+ A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf,
+ A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0,
+ A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1,
+ A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4,
+ A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5,
+ A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6,
+ A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8,
+ A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca,
+ A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb,
+ A10_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xd3,
+ A10_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4,
+ A10_PMU_PERFCTR_MAP_DISPATCH_BUBBLE = 0xd6,
+ A10_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND = 0xdb,
+ A10_PMU_PERFCTR_FETCH_RESTART = 0xde,
+ A10_PMU_PERFCTR_ST_NT_UOP = 0xe5,
+ A10_PMU_PERFCTR_LD_NT_UOP = 0xe6,
+ A10_PMU_PERFCTR_UNKNOWN_f5 = 0xf5,
+ A10_PMU_PERFCTR_UNKNOWN_f6 = 0xf6,
+ A10_PMU_PERFCTR_UNKNOWN_f7 = 0xf7,
+ A10_PMU_PERFCTR_UNKNOWN_f8 = 0xf8,
+ A10_PMU_PERFCTR_UNKNOWN_fd = 0xfd,
+ A10_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT,
+
+ /*
+ * From this point onwards, these are not actual HW events,
+ * but attributes that get stored in hw->config_base.
+ */
+ A10_PMU_CFG_COUNT_USER = BIT(8),
+ A10_PMU_CFG_COUNT_KERNEL = BIT(9),
+};
+
+static const u16 a10_pmu_event_affinity[A10_PMU_PERFCTR_LAST + 1] = {
+ [0 ... A10_PMU_PERFCTR_LAST] = ANY_BUT_0_1,
+ [A10_PMU_PERFCTR_RETIRE_UOP] = BIT(7),
+ [A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0),
+ [A10_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1),
+ [A10_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_INT_ALU] = BIT(7),
+ [A10_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_SIMD_ALU] = BIT(7),
+ [A10_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_INST_BARRIER] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_UNKNOWN_9f] = BIT(7),
+ [A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A10_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6,
+ [A10_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6,
+ [A10_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6,
+ [A10_PMU_PERFCTR_UNKNOWN_f8] = ONLY_2_TO_7,
+ [A10_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
+};
+
enum m1_pmu_events {
M1_PMU_PERFCTR_RETIRE_UOP = 0x1,
M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
@@ -878,6 +987,12 @@ static int a9_pmu_get_event_idx(struct pmu_hw_events *cpuc,
return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity);
}
+static int a10_pmu_get_event_idx(struct pmu_hw_events *cpuc,
+ struct perf_event *event)
+{
+ return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity);
+}
+
static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc,
struct perf_event *event)
{
@@ -1049,6 +1164,17 @@ static int a9_pmu_twister_init(struct arm_pmu *cpu_pmu)
return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS);
}
+static int a10_pmu_fusion_init(struct arm_pmu *cpu_pmu)
+{
+ cpu_pmu->name = "apple_fusion_pmu";
+ cpu_pmu->get_event_idx = a10_pmu_get_event_idx;
+ cpu_pmu->map_event = m1_pmu_map_event;
+ cpu_pmu->reset = m1_pmu_reset;
+ cpu_pmu->start = a7_pmu_start;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
+ return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
+}
+
static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->name = "apple_icestorm_pmu";
@@ -1098,6 +1224,7 @@ static const struct of_device_id m1_pmu_of_device_ids[] = {
{ .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, },
{ .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, },
{ .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, },
+ { .compatible = "apple,fusion-pmu", .data = a10_pmu_fusion_init, },
{ .compatible = "apple,twister-pmu", .data = a9_pmu_twister_init, },
{ .compatible = "apple,typhoon-pmu", .data = a8_pmu_typhoon_init, },
{ .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, },
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v4 11/11] drivers/perf: apple_m1: Add Apple A11 Support
2025-02-14 14:28 [PATCH v4 00/11] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Nick Chan
` (9 preceding siblings ...)
2025-02-14 14:28 ` [PATCH v4 10/11] drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support Nick Chan
@ 2025-02-14 14:28 ` Nick Chan
10 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-14 14:28 UTC (permalink / raw)
To: Will Deacon, Mark Rutland, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Catalin Marinas
Cc: Marc Zyngier, linux-arm-kernel, linux-perf-users, devicetree,
asahi, linux-kernel, Nick Chan
Add support for the CPU PMU found attached to the performance and
efficiency cores of the Apple A11 SoCs. This PMU can deliver its
interrupt via IRQ or FIQ. Use FIQ as that is faster.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
drivers/perf/apple_m1_cpu_pmu.c | 137 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 137 insertions(+)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index e66ec1426f5d9d48ef52abd539acff7648958785..612ec0dfacaa9c3fc43a3c122d836193494967ad 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -500,6 +500,113 @@ static const u16 a10_pmu_event_affinity[A10_PMU_PERFCTR_LAST + 1] = {
[A10_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
};
+enum a11_pmu_events {
+ A11_PMU_PERFCTR_RETIRE_UOP = 0x1,
+ A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
+ A11_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa,
+ A11_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb,
+ A11_PMU_PERFCTR_SCHEDULE_UOP = 0x52,
+ A11_PMU_PERFCTR_MAP_REWIND = 0x75,
+ A11_PMU_PERFCTR_MAP_STALL = 0x76,
+ A11_PMU_PERFCTR_MAP_INT_UOP = 0x7c,
+ A11_PMU_PERFCTR_MAP_LDST_UOP = 0x7d,
+ A11_PMU_PERFCTR_MAP_SIMD_UOP = 0x7e,
+ A11_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84,
+ A11_PMU_PERFCTR_INST_A32 = 0x8a,
+ A11_PMU_PERFCTR_INST_T32 = 0x8b,
+ A11_PMU_PERFCTR_INST_ALL = 0x8c,
+ A11_PMU_PERFCTR_INST_BRANCH = 0x8d,
+ A11_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e,
+ A11_PMU_PERFCTR_INST_BRANCH_RET = 0x8f,
+ A11_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90,
+ A11_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93,
+ A11_PMU_PERFCTR_INST_BRANCH_COND = 0x94,
+ A11_PMU_PERFCTR_INST_INT_LD = 0x95,
+ A11_PMU_PERFCTR_INST_INT_ST = 0x96,
+ A11_PMU_PERFCTR_INST_INT_ALU = 0x97,
+ A11_PMU_PERFCTR_INST_SIMD_LD = 0x98,
+ A11_PMU_PERFCTR_INST_SIMD_ST = 0x99,
+ A11_PMU_PERFCTR_INST_SIMD_ALU = 0x9a,
+ A11_PMU_PERFCTR_INST_LDST = 0x9b,
+ A11_PMU_PERFCTR_INST_BARRIER = 0x9c,
+ A11_PMU_PERFCTR_UNKNOWN_9f = 0x9f,
+ A11_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0,
+ A11_PMU_PERFCTR_L1D_TLB_MISS = 0xa1,
+ A11_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2,
+ A11_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3,
+ A11_PMU_PERFCTR_LD_UNIT_UOP = 0xa6,
+ A11_PMU_PERFCTR_ST_UNIT_UOP = 0xa7,
+ A11_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8,
+ A11_PMU_PERFCTR_LDST_X64_UOP = 0xb1,
+ A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC = 0xb3,
+ A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL = 0xb4,
+ A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf,
+ A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0,
+ A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1,
+ A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4,
+ A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5,
+ A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6,
+ A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8,
+ A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca,
+ A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb,
+ A11_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xd3,
+ A11_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4,
+ A11_PMU_PERFCTR_MAP_DISPATCH_BUBBLE = 0xd6,
+ A11_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND = 0xdb,
+ A11_PMU_PERFCTR_FETCH_RESTART = 0xde,
+ A11_PMU_PERFCTR_ST_NT_UOP = 0xe5,
+ A11_PMU_PERFCTR_LD_NT_UOP = 0xe6,
+ A11_PMU_PERFCTR_UNKNOWN_f5 = 0xf5,
+ A11_PMU_PERFCTR_UNKNOWN_f6 = 0xf6,
+ A11_PMU_PERFCTR_UNKNOWN_f7 = 0xf7,
+ A11_PMU_PERFCTR_UNKNOWN_f8 = 0xf8,
+ A11_PMU_PERFCTR_UNKNOWN_fd = 0xfd,
+ A11_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT,
+
+ /*
+ * From this point onwards, these are not actual HW events,
+ * but attributes that get stored in hw->config_base.
+ */
+ A11_PMU_CFG_COUNT_USER = BIT(8),
+ A11_PMU_CFG_COUNT_KERNEL = BIT(9),
+};
+
+static const u16 a11_pmu_event_affinity[A11_PMU_PERFCTR_LAST + 1] = {
+ [0 ... A11_PMU_PERFCTR_LAST] = ANY_BUT_0_1,
+ [A11_PMU_PERFCTR_RETIRE_UOP] = BIT(7),
+ [A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0),
+ [A11_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1),
+ [A11_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_INT_ALU] = BIT(7),
+ [A11_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_SIMD_ALU] = BIT(7),
+ [A11_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_INST_BARRIER] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_UNKNOWN_9f] = BIT(7),
+ [A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A11_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6,
+ [A11_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6,
+ [A11_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6,
+ [A11_PMU_PERFCTR_UNKNOWN_f8] = ONLY_2_TO_7,
+ [A11_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
+};
+
enum m1_pmu_events {
M1_PMU_PERFCTR_RETIRE_UOP = 0x1,
M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
@@ -993,6 +1100,12 @@ static int a10_pmu_get_event_idx(struct pmu_hw_events *cpuc,
return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity);
}
+static int a11_pmu_get_event_idx(struct pmu_hw_events *cpuc,
+ struct perf_event *event)
+{
+ return apple_pmu_get_event_idx(cpuc, event, a11_pmu_event_affinity);
+}
+
static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc,
struct perf_event *event)
{
@@ -1175,6 +1288,28 @@ static int a10_pmu_fusion_init(struct arm_pmu *cpu_pmu)
return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
}
+static int a11_pmu_monsoon_init(struct arm_pmu *cpu_pmu)
+{
+ cpu_pmu->name = "apple_monsoon_pmu";
+ cpu_pmu->get_event_idx = a11_pmu_get_event_idx;
+ cpu_pmu->map_event = m1_pmu_map_event;
+ cpu_pmu->reset = m1_pmu_reset;
+ cpu_pmu->start = m1_pmu_start;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
+ return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
+}
+
+static int a11_pmu_mistral_init(struct arm_pmu *cpu_pmu)
+{
+ cpu_pmu->name = "apple_mistral_pmu";
+ cpu_pmu->get_event_idx = a11_pmu_get_event_idx;
+ cpu_pmu->map_event = m1_pmu_map_event;
+ cpu_pmu->reset = m1_pmu_reset;
+ cpu_pmu->start = m1_pmu_start;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
+ return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS);
+}
+
static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->name = "apple_icestorm_pmu";
@@ -1225,6 +1360,8 @@ static const struct of_device_id m1_pmu_of_device_ids[] = {
{ .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, },
{ .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, },
{ .compatible = "apple,fusion-pmu", .data = a10_pmu_fusion_init, },
+ { .compatible = "apple,monsoon-pmu", .data = a11_pmu_monsoon_init, },
+ { .compatible = "apple,mistral-pmu", .data = a11_pmu_mistral_init, },
{ .compatible = "apple,twister-pmu", .data = a9_pmu_twister_init, },
{ .compatible = "apple,typhoon-pmu", .data = a8_pmu_typhoon_init, },
{ .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, },
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread