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b=RDWoyVWfPkTI6hWbn9tcBiYgdqyOC+z4fW6AC72LZdNWHWe4TPU7G48gaWoyZU2Ar bB4lDbJSUfYzT7vPiMNX0ip5QrJeodVJP5wj9WCAS7J/rIvL/M4RS5HPMOIypn2Lzh oinUo7VUDuoekFT/TK1yN0vjKDqc3Xi3KdiIh5qA= Date: Tue, 18 Feb 2025 14:35:03 +0200 From: Laurent Pinchart To: Tommaso Merciai Cc: Tommaso Merciai , linux-renesas-soc@vger.kernel.org, linux-media@vger.kernel.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/8] media: dt-bindings: renesas,rzg2l-csi2: Document Renesas RZ/V2H(P) SoC Message-ID: <20250218123503.GC20695@pendragon.ideasonboard.com> References: <20250210114540.524790-1-tommaso.merciai.xr@bp.renesas.com> <20250210114540.524790-3-tommaso.merciai.xr@bp.renesas.com> <20250214002951.GB8393@pendragon.ideasonboard.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: On Tue, Feb 18, 2025 at 12:55:22PM +0100, Tommaso Merciai wrote: > On Fri, Feb 14, 2025 at 02:29:51AM +0200, Laurent Pinchart wrote: > > On Mon, Feb 10, 2025 at 12:45:34PM +0100, Tommaso Merciai wrote: > > > From: Lad Prabhakar > > > > > > The MIPI CSI-2 block on the Renesas RZ/V2H(P) SoC is similar to the one > > > found on the Renesas RZ/G2L SoC, with the following differences: > > > - A different D-PHY > > > - Additional registers for the MIPI CSI-2 link > > > - Only two clocks > > > > > > Add a new compatible string, `renesas,r9a09g057-csi2`, for the RZ/V2H(P) > > > SoC. > > > > > > Signed-off-by: Lad Prabhakar > > > Signed-off-by: Tommaso Merciai > > > --- > > > .../bindings/media/renesas,rzg2l-csi2.yaml | 63 ++++++++++++++----- > > > 1 file changed, 48 insertions(+), 15 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml > > > index 7faa12fecd5b..0d07c55a3f35 100644 > > > --- a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml > > > +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml > > > @@ -17,12 +17,15 @@ description: > > > > > > properties: > > > compatible: > > > - items: > > > - - enum: > > > - - renesas,r9a07g043-csi2 # RZ/G2UL > > > - - renesas,r9a07g044-csi2 # RZ/G2{L,LC} > > > - - renesas,r9a07g054-csi2 # RZ/V2L > > > - - const: renesas,rzg2l-csi2 > > > + oneOf: > > > + - items: > > > + - enum: > > > + - renesas,r9a07g043-csi2 # RZ/G2UL > > > + - renesas,r9a07g044-csi2 # RZ/G2{L,LC} > > > + - renesas,r9a07g054-csi2 # RZ/V2L > > > + - const: renesas,rzg2l-csi2 > > > + > > > > I'd drop the empty line. > > I'll drop this line in v2, thanks. > > > > + - const: renesas,r9a09g057-csi2 # RZ/V2H(P) > > > > > > reg: > > > maxItems: 1 > > > @@ -31,16 +34,24 @@ properties: > > > maxItems: 1 > > > > > > clocks: > > > - items: > > > - - description: Internal clock for connecting CRU and MIPI > > > - - description: CRU Main clock > > > - - description: CRU Register access clock > > > + oneOf: > > > + - items: > > > + - description: Internal clock for connecting CRU and MIPI > > > + - description: CRU Main clock > > > + - description: CRU Register access clock > > > + - items: > > > + - description: CRU Main clock > > > + - description: CRU Register access clock > > > > > > clock-names: > > > - items: > > > - - const: system > > > - - const: video > > > - - const: apb > > > + oneOf: > > > + - items: > > > + - const: system > > > + - const: video > > > + - const: apb > > > + - items: > > > + - const: video > > > + - const: apb > > > > I would move the clocks and clock-names definitions to the conditional > > below. Otherwise I think a device tree that has two clocks only but > > incorrectly uses "system" and "video" instead of "video" and "apb" will > > validate. > > Agreed. Taking as reference your work done on renesas,fcp.yaml. > What about the following? > > clocks: true > clock-names: true > > Then move the clocks and clock-names below as you suggested > into the conditional block: > > allOf: > - if: > properties: > compatible: > contains: > const: renesas,r9a09g057-csi2 > then: > properties: > clocks: > items: > - description: CRU Main clock > - description: CRU Register access clock > clock-names: > items: > - const: video > - const: apb > > else: > properties: > clocks: > items: > - description: Internal clock for connecting CRU and MIPI > - description: CRU Main clock > - description: CRU Register access clock > clock-names: > items: > - const: system > - const: video > - const: apb > > Thanks in advance. I do like that, but I think Krzysztof wasn't entirely happy with it (it could be a separate but similar issue though, I don't recall the details). I'd recommend checking with him (he's on CC, so he will probably reply unless the mail gets buried in a mailbox that I am sure fills up quite quickly). > > > > > > power-domains: > > > maxItems: 1 > > > @@ -48,7 +59,7 @@ properties: > > > resets: > > > items: > > > - description: CRU_PRESETN reset terminal > > > - - description: CRU_CMN_RSTB reset terminal > > > + - description: CRU_CMN_RSTB reset terminal or D-PHY reset > > > > > > reset-names: > > > items: > > > @@ -101,6 +112,28 @@ required: > > > - reset-names > > > - ports > > > > > > +allOf: > > > + - if: > > > + properties: > > > + compatible: > > > + contains: > > > + const: renesas,r9a09g057-csi2 > > > + then: > > > + properties: > > > + clocks: > > > + maxItems: 2 > > > + > > > + clock-names: > > > + maxItems: 2 > > > + > > > + else: > > > + properties: > > > + clocks: > > > + maxItems: 3 > > > + > > > + clock-names: > > > + maxItems: 3 > > > + > > > additionalProperties: false > > > > > > examples: -- Regards, Laurent Pinchart