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From: Bjorn Helgaas <helgaas@kernel.org>
To: Chen Wang <unicorn_wang@outlook.com>
Cc: Chen Wang <unicornxw@gmail.com>,
	kw@linux.com, u.kleine-koenig@baylibre.com,
	aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com,
	conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com,
	krzk+dt@kernel.org, lee@kernel.org, lpieralisi@kernel.org,
	manivannan.sadhasivam@linaro.org, palmer@dabbelt.com,
	paul.walmsley@sifive.com, pbrobinson@gmail.com, robh@kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org,
	chao.wei@sophgo.com, xiaoguang.xing@sophgo.com,
	fengchun.li@sophgo.com
Subject: Re: [PATCH v3 1/5] dt-bindings: pci: Add Sophgo SG2042 PCIe host
Date: Wed, 19 Feb 2025 12:22:47 -0600	[thread overview]
Message-ID: <20250219182247.GA225989@bhelgaas> (raw)
In-Reply-To: <BMXPR01MB24403F8CD6BF5D4D2DDC57A4FEFC2@BMXPR01MB2440.INDPRD01.PROD.OUTLOOK.COM>

On Wed, Feb 12, 2025 at 01:54:11PM +0800, Chen Wang wrote:
> On 2025/2/12 12:25, Bjorn Helgaas wrote:
> [......]
> > > pcie_rc1 and pcie_rc2 share registers in cdns_pcie1_ctrl. By using
> > > different "sophgo,core-id" values, they can distinguish and access
> > > the registers they need in cdns_pcie1_ctrl.
> > Where does cdns_pcie1_ctrl fit in this example?  Does that enclose
> > both pcie_rc1 and pcie_rc2?
> 
> cdns_pcie1_ctrl is defined as a syscon node,  which contains registers
> shared by pcie_rc1 and pcie_rc2. In the binding yaml file, I drew a diagram
> to describe the relationship between them, copy here for your quick
> reference:
> 
> +                     +-- Core (Link0) <---> pcie_rc1  +-----------------+
> +                     |                                |                 |
> +      Cadence IP 2 --+                                | cdns_pcie1_ctrl |
> +                     |                                |                 |
> +                     +-- Core (Link1) <---> pcie_rc2  +-----------------+
> 
> The following is an example with cdns_pcie1_ctrl added. For simplicity, I
> deleted pcie_rc0.

Looks good.  It would be nice if there were some naming similarity or
comment or other hint to connect sophgo,core-id with the syscon node.

> pcie_rc1: pcie@7062000000 {
>     compatible = "sophgo,sg2042-pcie-host";
>     ...... // host bride level properties
>     linux,pci-domain = <1>;
>     sophgo,core-id = <0>;
>     sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
>     port {
>         // port level properties
>         vendor-id = <0x1f1c>;
>         device-id = <0x2042>;
>         num-lanes = <2>;
>     };
> };
> 
> pcie_rc2: pcie@7062800000 {
>     compatible = "sophgo,sg2042-pcie-host";
>     ...... // host bride level properties
>     linux,pci-domain = <2>;
>     sophgo,core-id = <1>;
>     sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
>     port {
>         // port level properties
>         vendor-id = <0x1f1c>;
>         device-id = <0x2042>;
>         num-lanes = <2>;
>     }
> 
> };
> 
> cdns_pcie1_ctrl: syscon@7063800000 {
>     compatible = "sophgo,sg2042-pcie-ctrl", "syscon";
>     reg = <0x70 0x63800000 0x0 0x800000>;
> };
> 

  parent reply	other threads:[~2025-02-19 18:22 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-15  7:05 [PATCH v3 0/5] Add PCIe support to Sophgo SG2042 SoC Chen Wang
2025-01-15  7:06 ` [PATCH v3 1/5] dt-bindings: pci: Add Sophgo SG2042 PCIe host Chen Wang
2025-01-19 11:44   ` Manivannan Sadhasivam
2025-01-22 12:52     ` Chen Wang
2025-01-22 17:21       ` Manivannan Sadhasivam
2025-01-26  0:29         ` Chen Wang
2025-01-22 22:21   ` Bjorn Helgaas
2025-01-26  2:27     ` Chen Wang
2025-02-03  2:35       ` Chen Wang
2025-02-11 23:34       ` Bjorn Helgaas
2025-02-12  1:50         ` Chen Wang
2025-02-12  4:25           ` Bjorn Helgaas
2025-02-12  5:54             ` Chen Wang
2025-02-17  8:40               ` Chen Wang
2025-02-19 18:22               ` Bjorn Helgaas [this message]
2025-02-21  3:29                 ` Chen Wang
2025-02-21 22:13                   ` Bjorn Helgaas
2025-02-24  6:27                     ` Manivannan Sadhasivam
2025-01-15  7:06 ` [PATCH v3 2/5] PCI: sg2042: Add Sophgo SG2042 PCIe driver Chen Wang
2025-01-19 12:23   ` Manivannan Sadhasivam
2025-01-22 13:28     ` Chen Wang
2025-01-22 17:34       ` Manivannan Sadhasivam
2025-01-23 12:12         ` Marc Zyngier
2025-02-07 17:49           ` Manivannan Sadhasivam
2025-02-17  8:22         ` Chen Wang
2025-02-19 17:57           ` Manivannan Sadhasivam
2025-01-22 21:33   ` Bjorn Helgaas
2025-02-17  8:36     ` Chen Wang
2025-01-15  7:07 ` [PATCH v3 3/5] dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible Chen Wang
2025-02-11 14:33   ` (subset) " Lee Jones
2025-02-12  0:48     ` Chen Wang
2025-02-20 16:00       ` Lee Jones
2025-01-15  7:07 ` [PATCH v3 4/5] riscv: sophgo: dts: add pcie controllers for SG2042 Chen Wang
2025-01-15  7:07 ` [PATCH v3 5/5] riscv: sophgo: dts: enable pcie for PioneerBox Chen Wang

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