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b=fNrL9+qrRiXYpe+ui1lESh8ksitjT5ZXPSjc2ZH28uxRs5mlYbtTMspy4alOCXPI9 NEjoIo18eu8dP+D6Wx+GMogJAq8Ul6/uhN6djY7fiFSB0qIIhqseaXjx6WvEIJvq/O exFRNjaElgZ3Q52qA7ZE64wGWbu/gD4qFY/FutqA= Date: Wed, 19 Feb 2025 23:17:38 +0200 From: Laurent Pinchart To: Rob Herring Cc: Tommaso Merciai , linux-renesas-soc@vger.kernel.org, linux-media@vger.kernel.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, Tommaso Merciai , Mauro Carvalho Chehab , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/8] media: dt-bindings: renesas,rzg2l-csi2: Document Renesas RZ/V2H(P) SoC Message-ID: <20250219211738.GE31825@pendragon.ideasonboard.com> References: <20250210114540.524790-1-tommaso.merciai.xr@bp.renesas.com> <20250210114540.524790-3-tommaso.merciai.xr@bp.renesas.com> <20250214002951.GB8393@pendragon.ideasonboard.com> <20250219145139.GA2551711-robh@kernel.org> <20250219151237.GB31825@pendragon.ideasonboard.com> <20250219205620.GA2912221-robh@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20250219205620.GA2912221-robh@kernel.org> On Wed, Feb 19, 2025 at 02:56:20PM -0600, Rob Herring wrote: > On Wed, Feb 19, 2025 at 05:12:37PM +0200, Laurent Pinchart wrote: > > On Wed, Feb 19, 2025 at 08:51:39AM -0600, Rob Herring wrote: > > > On Fri, Feb 14, 2025 at 02:29:51AM +0200, Laurent Pinchart wrote: > > > > Hi Tommaso, Prabhakar, > > > > > > > > Thank you for the patch. > > > > > > > > On Mon, Feb 10, 2025 at 12:45:34PM +0100, Tommaso Merciai wrote: > > > > > From: Lad Prabhakar > > > > > > > > > > The MIPI CSI-2 block on the Renesas RZ/V2H(P) SoC is similar to the one > > > > > found on the Renesas RZ/G2L SoC, with the following differences: > > > > > - A different D-PHY > > > > > - Additional registers for the MIPI CSI-2 link > > > > > - Only two clocks > > > > > > > > > > Add a new compatible string, `renesas,r9a09g057-csi2`, for the RZ/V2H(P) > > > > > SoC. > > > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > Signed-off-by: Tommaso Merciai > > > > > --- > > > > > .../bindings/media/renesas,rzg2l-csi2.yaml | 63 ++++++++++++++----- > > > > > 1 file changed, 48 insertions(+), 15 deletions(-) > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml > > > > > index 7faa12fecd5b..0d07c55a3f35 100644 > > > > > --- a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml > > > > > +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml > > > > > @@ -17,12 +17,15 @@ description: > > > > > > > > > > properties: > > > > > compatible: > > > > > - items: > > > > > - - enum: > > > > > - - renesas,r9a07g043-csi2 # RZ/G2UL > > > > > - - renesas,r9a07g044-csi2 # RZ/G2{L,LC} > > > > > - - renesas,r9a07g054-csi2 # RZ/V2L > > > > > - - const: renesas,rzg2l-csi2 > > > > > + oneOf: > > > > > + - items: > > > > > + - enum: > > > > > + - renesas,r9a07g043-csi2 # RZ/G2UL > > > > > + - renesas,r9a07g044-csi2 # RZ/G2{L,LC} > > > > > + - renesas,r9a07g054-csi2 # RZ/V2L > > > > > + - const: renesas,rzg2l-csi2 > > > > > + > > > > > > > > I'd drop the empty line. > > > > > > > > > + - const: renesas,r9a09g057-csi2 # RZ/V2H(P) > > > > > > > > > > reg: > > > > > maxItems: 1 > > > > > @@ -31,16 +34,24 @@ properties: > > > > > maxItems: 1 > > > > > > > > > > clocks: > > > > > - items: > > > > > - - description: Internal clock for connecting CRU and MIPI > > > > > - - description: CRU Main clock > > > > > - - description: CRU Register access clock > > > > > + oneOf: > > > > > + - items: > > > > > + - description: Internal clock for connecting CRU and MIPI > > > > > + - description: CRU Main clock > > > > > + - description: CRU Register access clock > > > > > + - items: > > > > > + - description: CRU Main clock > > > > > + - description: CRU Register access clock > > > > > > > > > > clock-names: > > > > > - items: > > > > > - - const: system > > > > > - - const: video > > > > > - - const: apb > > > > > + oneOf: > > > > > + - items: > > > > > + - const: system > > > > > + - const: video > > > > > + - const: apb > > > > > + - items: > > > > > + - const: video > > > > > + - const: apb > > > > > > > > I would move the clocks and clock-names definitions to the conditional > > > > below. Otherwise I think a device tree that has two clocks only but > > > > incorrectly uses "system" and "video" instead of "video" and "apb" will > > > > validate. > > > > > > No, that wouldn't be allowed. The preference is to have it like this > > > because it discourages creating more variations. If the names are all > > > defined in if/then schema, then you can just add a new one with any > > > names you want. Though if the variations become such a mess, then > > > defining them in the if/then schemas would probably be better. > > > > > > It would be better if 'clocks' could be reworked to avoid the 'oneOf' > > > though (oneOf == poor error messages). It just needs a 'minItems: 2' > > > added and the descriptions reworded for both cases. > > > > Don't the items in clocks need to match the items in clock-names ? We > > can't reorder clock-names items as that would be an ABI breakage, so we > > can't reorder clocks items either. > > Validation wise, the only thing we check is is it 2 or 3 entries. No way > to enforce it's the right clock. The description is just for humans. So > you could just put "(optional)" on the first entry though there is no > way in json-schema to really do that. If you prefer as-is with the > oneOf, that's fine too. Adding "(optional)" would work for me in this case I think, even if I think it could be a bit confusing. I'm OK either way. -- Regards, Laurent Pinchart