Re: [PATCH 2/2] PCI: sophgo-dwc: Add Sophgo SG2044 PCIe driver

Inochi Amaoto
2025-02-22T00:44:04Z

On Fri, Feb 21, 2025 at 05:49:58PM -0600, Bjorn Helgaas wrote:
> On Fri, Feb 21, 2025 at 09:37:56AM +0800, Inochi Amaoto wrote:
> > Add support for DesignWare-based PCIe controller in SG2044 SoC.
>
> > @@ -341,6 +341,16 @@ config PCIE_ROCKCHIP_DW_EP
> > Enables support for the DesignWare PCIe controller in the
> > Rockchip SoC (except RK3399) to work in endpoint mode.
> >
> > +config PCIE_SOPHGO_DW
> > + bool "SOPHGO DesignWare PCIe controller"
>
> What's the canonical styling of "SOPHGO"? I see "Sophgo" in the
> subject line and in Chen Wang's SG2042 series. Pick the official
> styling and use it consistently.
>

This is my mistake. It should be "Sophgo", I will change it.

> Reorder this so the menuconfig menu items remain alphabetically
> sorted.
>

I think this order is applied to the entry title in menuconfig,
and is not the config key? If so, I will change it.

> > + depends on ARCH_SOPHGO || COMPILE_TEST
> > + depends on PCI_MSI
> > + depends on OF
> > + select PCIE_DW_HOST
> > + help
> > + Enables support for the DesignWare PCIe controller in the
> > + SOPHGO SoC.
> > +
> > config PCI_EXYNOS
> > tristate "Samsung Exynos PCIe controller"
> > depends on ARCH_EXYNOS || COMPILE_TEST
>
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * PCIe host controller driver for Sophgo SoCs.
>
> Looks too generic, since Chen Wang's series says Sophgo SG2042 SoC is
> Cadence-based, so this driver apparently doesn't cover all Sophgo
> SoCs.
>

OK, I will change the description to point it only cover
the controller based on the DesignWare core.

> > + *
>
> Spurious blank line.
>
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/gpio/consumer.h>
> > +#include <linux/irqchip/chained_irq.h>
> > +#include <linux/irqdomain.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/property.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +#include <linux/reset.h>
> > +
> > +#include "pcie-designware.h"
> > +
> > +#define to_sophgo_pcie(x) dev_get_drvdata((x)->dev)
> > +
> > +#define PCIE_INT_SIGNAL 0xc48
> > +#define PCIE_INT_EN 0xca0
> > +
> > +#define PCIE_SIGNAL_INTX_SHIFT 5
> > +#define PCIE_INT_EN_INTX_SHIFT 1
>
> Define masks with GENMASK() and get rid of the _SHIFT #defines.
>
> > +#define PCIE_INT_EN_INT_SII BIT(0)
> > +#define PCIE_INT_EN_INT_INTA BIT(1)
> > +#define PCIE_INT_EN_INT_INTB BIT(2)
> > +#define PCIE_INT_EN_INT_INTC BIT(3)
> > +#define PCIE_INT_EN_INT_INTD BIT(4)
>
> These are unused, drop them.
>
> > +#define PCIE_INT_EN_INT_MSI BIT(5)
> > +
> > +struct sophgo_pcie {
> > + struct dw_pcie pci;
> > + void __iomem *app_base;
> > + struct clk_bulk_data *clks;
> > + unsigned int clk_cnt;
> > + struct reset_control *rst;
> > + struct irq_domain *irq_domain;
>
> Indent the member names to align vertically as most other drivers do.
>
> > +};
> > +
> > +static int sophgo_pcie_readl_app(struct sophgo_pcie *sophgo, u32 reg)
> > +{
> > + return readl_relaxed(sophgo->app_base + reg);
> > +}
> > +
> > +static void sophgo_pcie_writel_app(struct sophgo_pcie *sophgo, u32 val, u32 reg)
> > +{
> > + writel_relaxed(val, sophgo->app_base + reg);
> > +}
> > +
> > +static void sophgo_pcie_intx_handler(struct irq_desc *desc)
> > +{
> > + struct dw_pcie_rp *pp = irq_desc_get_handler_data(desc);
> > + struct irq_chip *chip = irq_desc_get_chip(desc);
> > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > + struct sophgo_pcie *sophgo = to_sophgo_pcie(pci);
> > + unsigned long hwirq = PCIE_SIGNAL_INTX_SHIFT;
> > + unsigned long reg;
> > +
> > + chained_irq_enter(chip, desc);
> > +
> > + reg = sophgo_pcie_readl_app(sophgo, PCIE_INT_SIGNAL);
> > +
> > + for_each_set_bit_from(hwirq, &reg, PCI_NUM_INTX + PCIE_SIGNAL_INTX_SHIFT)
>
> Use FIELD_GET() here and iterate through PCI_NUM_INTX. Then you don't
> need for_each_set_bit_from() and shouldn't need PCIE_SIGNAL_INTX_SHIFT
> here and below.
>

OK, I will change it

> > + generic_handle_domain_irq(sophgo->irq_domain,
> > + hwirq - PCIE_SIGNAL_INTX_SHIFT);
> > +
> > + chained_irq_exit(chip, desc);
> > +}
> > +
> > +static void sophgo_intx_mask(struct irq_data *d)
> > +{
> > + struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
> > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > + struct sophgo_pcie *sophgo = to_sophgo_pcie(pci);
> > + unsigned long flags;
> > + u32 val;
> > +
> > + raw_spin_lock_irqsave(&pp->lock, flags);
> > +
> > + val = sophgo_pcie_readl_app(sophgo, PCIE_INT_EN);
> > + val &= ~BIT(d->hwirq + PCIE_INT_EN_INTX_SHIFT);
>
> FIELD_PREP().
>
> > + sophgo_pcie_writel_app(sophgo, val, PCIE_INT_EN);
> > +
> > + raw_spin_unlock_irqrestore(&pp->lock, flags);
> > +};
> > +
> > +static void sophgo_intx_unmask(struct irq_data *d)
> > +{
> > + struct dw_pcie_rp *pp = irq_data_get_irq_chip_data(d);
> > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > + struct sophgo_pcie *sophgo = to_sophgo_pcie(pci);
> > + unsigned long flags;
> > + u32 val;
> > +
> > + raw_spin_lock_irqsave(&pp->lock, flags);
> > +
> > + val = sophgo_pcie_readl_app(sophgo, PCIE_INT_EN);
> > + val |= BIT(d->hwirq + PCIE_INT_EN_INTX_SHIFT);
>
> Ditto.
>
> > + sophgo_pcie_writel_app(sophgo, val, PCIE_INT_EN);
> > +
> > + raw_spin_unlock_irqrestore(&pp->lock, flags);
> > +};
> > +
> > +static void sophgo_intx_eoi(struct irq_data *d)
> > +{
> > +}
> > +
> > +static struct irq_chip sophgo_intx_irq_chip = {
> > + .name = "INTx",
> > + .irq_mask = sophgo_intx_mask,
> > + .irq_unmask = sophgo_intx_unmask,
> > + .irq_eoi = sophgo_intx_eoi,
>
> Name these ending with the irq_chip field names, e.g.,
> sophgo_intx_irq_mask(), to make them easier to find with grep.
>
> Bjorn

Thanks, I will take all the comments and improve the driver.

Regards,
Inochi