Re: [PATCH 1/2] dt-bindings: pci: Add Sophgo SG2044 PCIe host

Inochi Amaoto
2025-02-22T00:34:28Z

On Fri, Feb 21, 2025 at 05:01:41PM +0000, Conor Dooley wrote:
> On Fri, Feb 21, 2025 at 09:37:55AM +0800, Inochi Amaoto wrote:
> > The pcie controller on the SG2044 is designware based with
> > custom app registers.
> >
> > Add binding document for SG2044 PCIe host controller.
> >
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > ---
> > .../bindings/pci/sophgo,sg2044-pcie.yaml | 125 ++++++++++++++++++
> > 1 file changed, 125 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml
> > new file mode 100644
> > index 000000000000..040dabe905e0
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml
> > @@ -0,0 +1,125 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/sophgo,sg2044-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: DesignWare based PCIe Root Complex controller on Sophgo SoCs
> > +
> > +maintainers:
> > + - Inochi Amaoto <inochiama@gmail.com>
> > +
> > +description: |+
> > + SG2044 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
> > + PCIe IP and thus inherits all the common properties defined in
> > + snps,dw-pcie.yaml.
> > +
> > +allOf:
> > + - $ref: /schemas/pci/pci-host-bridge.yaml#
> > + - $ref: /schemas/pci/snps,dw-pcie.yaml#
> > +
> > +properties:
> > + compatible:
> > + const: sophgo,sg2044-pcie
> > +
> > + reg:
> > + items:
> > + - description: Data Bus Interface (DBI) registers
> > + - description: iATU registers
> > + - description: Config registers
> > + - description: Sophgo designed configuration registers
> > +
> > + reg-names:
> > + items:
> > + - const: dbi
> > + - const: atu
> > + - const: config
> > + - const: app
> > +
> > + clocks:
> > + items:
> > + - description: core clk
> > +
> > + clock-names:
> > + items:
> > + - const: core
> > +
> > + dma-coherent: true
>
> Why's this here? RISC-V is dma-coherent by default, with dma-noncoherent
> used to indicate systems/devices that are not.
>
> Cheers,
> Conor.
>

The PCIe is dma coherent, but the SoC itself is marked as
dma-noncoherent. So I add dma-coherent to the binding. I
wonder whether dma-coherent is necessary even in this case?

Regards,
Inochi