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[209.17.68.221]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-220d556e169sm139087635ad.192.2025.02.21.08.23.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 08:23:22 -0800 (PST) Date: Sat, 22 Feb 2025 01:23:21 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Florian Fainelli Cc: Thomas Gleixner , Stanimir Varbanov , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jim Quinlan , Nicolas Saenz Julienne , Lorenzo Pieralisi , Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Dave Stevenson Subject: Re: [PATCH v5 -next 03/11] irqchip: Add Broadcom bcm2712 MSI-X interrupt controller Message-ID: <20250221162321.GC3753638@rocinante> References: <20250120130119.671119-1-svarbanov@suse.de> <20250120130119.671119-4-svarbanov@suse.de> <87bjvs86w8.ffs@tglx> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hello, [...] > > As this is a new controller and required for the actual PCI muck, I > > think the best way is to take it through the PCI tree, unless someone > > wants me to pick the whole lot up. > > Agreed, the PCI maintainers should take patches 1 through 9 inclusive, and I > will take patches 10-11 through the Broadcom ARM SoC tree, Bjorn, KW, does > that work? No problem. As such, when applying, I took all the patches from #1 through #8 and dropped #9 as it has been superseded. Krzysztof