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Sun, 23 Feb 2025 22:33:31 -0800 (PST) Date: Mon, 24 Feb 2025 12:03:26 +0530 From: Manivannan Sadhasivam To: Matthew Gerlach Cc: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, joyce.ooi@intel.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, matthew.gerlach@altera.com, peter.colberg@altera.com Subject: Re: [PATCH v8 1/2] dt-bindings: PCI: altera: Add binding for Agilex Message-ID: <20250224063326.kbuknwwhx5kyhgad@thinkpad> References: <20250221170452.875419-1-matthew.gerlach@linux.intel.com> <20250221170452.875419-2-matthew.gerlach@linux.intel.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250221170452.875419-2-matthew.gerlach@linux.intel.com> On Fri, Feb 21, 2025 at 11:04:51AM -0600, Matthew Gerlach wrote: > Add the compatible bindings for the three variants of Agilex > PCIe Hard IP. > > Signed-off-by: Matthew Gerlach Acked-by: Manivannan Sadhasivam - Mani > Reviewed-by: Rob Herring (Arm) > --- > v8: > - Removed patches unrelated to Agilex PCIe root port support from set. > - Removed patches related to a specific FPGA configuration from set. > --- > .../devicetree/bindings/pci/altr,pcie-root-port.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml > index 52533fccc134..1f93120d8eef 100644 > --- a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml > +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml > @@ -12,9 +12,19 @@ maintainers: > > properties: > compatible: > + description: Each family of socfpga has its own implementation > + of the pci controller. altr,pcie-root-port-1.0 is used for the Cyclone5 > + family of chips. The Stratix10 family of chips is supported > + by altr,pcie-root-port-2.0. The Agilex family of chips has > + three, non-register compatible, variants of PCIe Hard IP referred to as > + the f-tile, p-tile, and r-tile, depending on the specific chip instance. > + > enum: > - altr,pcie-root-port-1.0 > - altr,pcie-root-port-2.0 > + - altr,pcie-root-port-3.0-f-tile > + - altr,pcie-root-port-3.0-p-tile > + - altr,pcie-root-port-3.0-r-tile > > reg: > items: > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்