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Thu, 27 Feb 2025 12:06:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG1PEPF000082E4.mail.protection.outlook.com (10.167.240.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8489.16 via Frontend Transport; Thu, 27 Feb 2025 12:06:20 +0000 Received: from localhost.localdomain (unknown [172.16.64.25]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 8F1F941604E4; Thu, 27 Feb 2025 20:06:19 +0800 (CST) From: Peter Chen To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, marcin@juszkiewicz.com.pl, Peter Chen Subject: [PATCH v3 0/6] arm64: Introduce CIX P1 (SKY1) SoC Date: Thu, 27 Feb 2025 20:06:13 +0800 Message-Id: <20250227120619.1741431-1-peter.chen@cixtech.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E4:EE_|SEZPR06MB6744:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 5c289c89-46e3-48c0-4161-08dd572725b4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Feb 2025 12:06:20.2670 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c289c89-46e3-48c0-4161-08dd572725b4 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E4.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEZPR06MB6744 Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC. Orion O6 is the world's first open source Arm V9 Motherboard built by Radxa. You could find brief introduction for SoC and related boards at: https://radxa.com/products/orion/o6#overview In this series, we add initial SoC and board support for Kernel building. Patch 1-2: Add dt-binding doc for CIX and its sky1 SoC Patch 3: add related maintainter entry Patch 4-5: add Arm64 build support Patch 6: add initial dts support for SoC and Orion O6 board To run upstream kernel at Orion O6 board, you need to use BIOS released by Radxa: https://docs.radxa.com/en/orion/o6/bios/install-bios Changes for v3: - Patch 1: Add Krzysztof Kozlowski's Acked-by Tag - Patch 2: Add Krzysztof Kozlowski's Reviewed-by Tag - Patch 6: Fix two dts coding sytle issues Changes for v2: - Pass dts build check with below commands: make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=vendor-prefixes.yaml make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=arm/cix.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb - Re-order the patch set, and move vendor-perfixes to the 1st patch. - Patch 4: Ordered Kconfig config entry by alpha-numerically - Patch 5: Corrects the Ack tag's name - Patch 6: see below. 1) Corrects the SoF tag's name 2) Fix several coding sytle issues 3) move linux,cma node to dts file 4) delete memory node, memory size is passed by firmware 5) delete uart2 node which will be added in future patches 6) Improve for pmu and cpu node to stands for more specific cpu model 7) Improve the timer node and add hypervisor virtual timer irq Fugang Duan (1): arm64: Kconfig: add ARCH_CIX for cix silicons Peter Chen (5): dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd. dt-bindings: arm: add CIX P1 (SKY1) SoC MAINTAINERS: Add CIX SoC maintainer entry arm64: defconfig: Enable CIX SoC arm64: dts: cix: add initial CIX P1(SKY1) dts support .../devicetree/bindings/arm/cix.yaml | 26 +++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + MAINTAINERS | 8 + arch/arm64/Kconfig.platforms | 6 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/cix/Makefile | 2 + arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 26 +++ arch/arm64/boot/dts/cix/sky1.dtsi | 216 ++++++++++++++++++ arch/arm64/configs/defconfig | 1 + 9 files changed, 288 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cix.yaml create mode 100644 arch/arm64/boot/dts/cix/Makefile create mode 100644 arch/arm64/boot/dts/cix/sky1-orion-o6.dts create mode 100644 arch/arm64/boot/dts/cix/sky1.dtsi -- 2.25.1