[PATCH v3 01/13] dt-bindings: soc: Add Renesas RZ/T2H (R9A09G077) SoC

[PATCH v3 01/13] dt-bindings: soc: Add Renesas RZ/T2H (R9A09G077) SoC

[Thierry Bultel]

Add RZ/T2H (R9A09G077), its variants, and the rt2h-evk evaluation board in
documentation.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
---
 .../devicetree/bindings/soc/renesas/renesas.yaml       | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index 225c0f07ae94..98563a31b5e1 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -554,6 +554,16 @@ properties:
               - renesas,r9a09g057h44 # RZ/V2HP with Mali-G31 + Mali-C55 support
           - const: renesas,r9a09g057
 
+      - description: RZ/T2H (R9A09G077)
+        items:
+          - enum:
+              - renesas,rzt2h-evk # RZ/T2H Evaluation Board
+          - enum:
+              - renesas,r9a09g077m04 # RZ/T2H with Single Cortex-A55 + Dual Cortex-R52 - no security
+              - renesas,r9a09g077m24 # RZ/T2H with Dual Cortex-A55 + Dual Cortex-R52 - no security
+              - renesas,r9a09g077m44 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - no security
+          - const: renesas,r9a09g077
+
 additionalProperties: true
 
 ...
-- 
2.43.0

Re: [PATCH v3 01/13] dt-bindings: soc: Add Renesas RZ/T2H (R9A09G077) SoC

[Krzysztof Kozlowski]

On 26/02/2025 14:09, Thierry Bultel wrote:
> Add RZ/T2H (R9A09G077), its variants, and the rt2h-evk evaluation board in
> documentation.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>

Where? That's a v3, previous version did not have it and there was no
tag given on the lists. In the same time this changed from v2, so more
questions - tag which was not given appears on patch which changed
significantly.



Best regards,
Krzysztof

[PATCH v3 02/13] dt-bindings: clock: Add cpg for the Renesas RZ/T2H SoC

[Thierry Bultel]

Document RZ/T2H (a.k.a r9a09g077) cpg-mssr (Clock Pulse Generator) binding.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
---
 .../bindings/clock/renesas,cpg-mssr.yaml      |  4 +-
 .../clock/renesas,r9a09g077-cpg-mssr.h        | 49 +++++++++++++++++++
 2 files changed, 52 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
index 77ce3615c65a..be9a0576e1db 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
@@ -52,9 +52,10 @@ properties:
       - renesas,r8a779f0-cpg-mssr # R-Car S4-8
       - renesas,r8a779g0-cpg-mssr # R-Car V4H
       - renesas,r8a779h0-cpg-mssr # R-Car V4M
+      - renesas,r9a09g077-cpg-mssr # RZ/T2H
 
   reg:
-    maxItems: 1
+    maxItems: 2
 
   clocks:
     minItems: 1
@@ -68,6 +69,7 @@ properties:
         - extal     # All
         - extalr    # Most R-Car Gen3 and RZ/G2
         - usb_extal # Most R-Car Gen2 and RZ/G1
+        - loco      # RZ/T2H
 
   '#clock-cells':
     description: |
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
new file mode 100644
index 000000000000..27c9cdcdf7c8
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A09G077 CPG Core Clocks */
+#define R9A09G077_CA55C0		0
+#define R9A09G077_CA55C1		1
+#define R9A09G077_CA55C2		2
+#define R9A09G077_CA55C3		3
+#define R9A09G077_SDHIHS		4
+#define R9A09G077_CLK_PLL1_ETH_PHY	5
+#define R9A09G077_CLK_OSC_ETH_PHY	6
+#define R9A09G077_CLK_ETHPHY		7
+#define R9A09G077_PCLKAH		8
+#define R9A09G077_PCLKAM		9
+#define R9A09G077_PCLKAL		10
+#define R9A09G077_CLK_SEL_ETH_PHY	11
+#define R9A09G077_DFI			12
+#define R9A09G077_PCLKH			13
+#define R9A09G077_PCLKM			14
+#define R9A09G077_PCLKL			15
+#define R9A09G077_PCLKGPTL		16
+#define R9A09G077_PCLKSHOST		17
+#define R9A09G077_PCLKRTC		18
+#define R9A09G077_USB			19
+#define R9A09G077_SPI0			20
+#define R9A09G077_SPI1			21
+#define R9A09G077_SPI2			22
+#define R9A09G077_SPI3			23
+#define R9A09G077_ETCLKA		24
+#define R9A09G077_ETCLKB		25
+#define R9A09G077_ETCLKC		26
+#define R9A09G077_ETCLKD		27
+#define R9A09G077_ETCLKE		28
+#define R9A09G077_ETHCLKE		29
+#define R9A09G077_ETHCLK_EXTAL		30
+#define R9A09G077_ETH_REFCLK		31
+#define R9A09G077_LCDC_CLKA		32
+#define R9A09G077_LCDC_CLKP		33
+#define R9A09G077_CA55			34
+#define R9A09G077_LCDC_CLKD		35
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
-- 
2.43.0

Re: [PATCH v3 02/13] dt-bindings: clock: Add cpg for the Renesas RZ/T2H SoC

[Rob Herring (Arm)]

On Wed, 26 Feb 2025 14:09:21 +0100, Thierry Bultel wrote:
> Document RZ/T2H (a.k.a r9a09g077) cpg-mssr (Clock Pulse Generator) binding.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
> ---
>  .../bindings/clock/renesas,cpg-mssr.yaml      |  4 +-
>  .../clock/renesas,r9a09g077-cpg-mssr.h        | 49 +++++++++++++++++++
>  2 files changed, 52 insertions(+), 1 deletion(-)
>  create mode 100644 include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.example.dtb: clock-controller@e6150000: reg: [[3860135936, 4096]] is too short
	from schema $id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250226130935.3029927-3-thierry.bultel.yh@bp.renesas.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[PATCH v3 03/13] dt-bindings: serial: Add compatible for Renesas RZ/T2H SoC in sci

[Thierry Bultel]

Document RZ/T2H (a.k.a r9a09g077) in SCI binding.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
---
 .../bindings/serial/renesas,sci.yaml          | 64 ++++++++++++-------
 1 file changed, 40 insertions(+), 24 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/renesas,sci.yaml b/Documentation/devicetree/bindings/serial/renesas,sci.yaml
index 64d3db6e54e5..2c4080283963 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,sci.yaml
@@ -9,9 +9,6 @@ title: Renesas Serial Communication Interface
 maintainers:
   - Geert Uytterhoeven <geert+renesas@glider.be>
 
-allOf:
-  - $ref: serial.yaml#
-
 properties:
   compatible:
     oneOf:
@@ -22,6 +19,8 @@ properties:
               - renesas,r9a07g054-sci     # RZ/V2L
           - const: renesas,sci            # generic SCI compatible UART
 
+      - const: renesas,r9a09g077-sci      # RZ/T2H
+
       - items:
           - const: renesas,sci            # generic SCI compatible UART
 
@@ -54,8 +53,6 @@ properties:
         - fck # UART functional clock
         - sck # optional external clock input
 
-  uart-has-rtscts: false
-
 required:
   - compatible
   - reg
@@ -63,25 +60,44 @@ required:
   - clocks
   - clock-names
 
-if:
-  properties:
-    compatible:
-      contains:
-        enum:
-          - renesas,r9a07g043-sci
-          - renesas,r9a07g044-sci
-          - renesas,r9a07g054-sci
-then:
-  properties:
-    resets:
-      maxItems: 1
-
-    power-domains:
-      maxItems: 1
-
-  required:
-    - resets
-    - power-domains
+allOf:
+  - $ref: serial.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g077-sci
+    then:
+      properties:
+        uart-has-rtscts: true
+        power-domains:
+          maxItems: 1
+      required:
+        - power-domains
+
+    else:
+      properties:
+        uart-has-rtscts: false
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a07g043-sci
+              - renesas,r9a07g044-sci
+              - renesas,r9a07g054-sci
+    then:
+      properties:
+        resets:
+          maxItems: 1
+
+        power-domains:
+          maxItems: 1
+
+      required:
+        - resets
+        - power-domains
 
 unevaluatedProperties: false
 
-- 
2.43.0

Re: [PATCH v3 03/13] dt-bindings: serial: Add compatible for Renesas RZ/T2H SoC in sci

[Rob Herring]

On Wed, Feb 26, 2025 at 02:09:22PM +0100, Thierry Bultel wrote:
> Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
> ---
>  .../bindings/serial/renesas,sci.yaml          | 64 ++++++++++++-------
>  1 file changed, 40 insertions(+), 24 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/renesas,sci.yaml b/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> index 64d3db6e54e5..2c4080283963 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> @@ -9,9 +9,6 @@ title: Renesas Serial Communication Interface
>  maintainers:
>    - Geert Uytterhoeven <geert+renesas@glider.be>
>  
> -allOf:
> -  - $ref: serial.yaml#
> -
>  properties:
>    compatible:
>      oneOf:
> @@ -22,6 +19,8 @@ properties:
>                - renesas,r9a07g054-sci     # RZ/V2L
>            - const: renesas,sci            # generic SCI compatible UART
>  
> +      - const: renesas,r9a09g077-sci      # RZ/T2H
> +

Perhaps explain in the commit msg why the 'renesas,sci' is not 
applicable for this chip.

>        - items:
>            - const: renesas,sci            # generic SCI compatible UART
>  
> @@ -54,8 +53,6 @@ properties:
>          - fck # UART functional clock
>          - sck # optional external clock input
>  
> -  uart-has-rtscts: false
> -
>  required:
>    - compatible
>    - reg
> @@ -63,25 +60,44 @@ required:
>    - clocks
>    - clock-names
>  
> -if:
> -  properties:
> -    compatible:
> -      contains:
> -        enum:
> -          - renesas,r9a07g043-sci
> -          - renesas,r9a07g044-sci
> -          - renesas,r9a07g054-sci
> -then:
> -  properties:
> -    resets:
> -      maxItems: 1
> -
> -    power-domains:
> -      maxItems: 1
> -
> -  required:
> -    - resets
> -    - power-domains
> +allOf:
> +  - $ref: serial.yaml#
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a09g077-sci
> +    then:
> +      properties:
> +        uart-has-rtscts: true

Drop. It is already allowed.

> +        power-domains:
> +          maxItems: 1
> +      required:
> +        - power-domains
> +
> +    else:
> +      properties:
> +        uart-has-rtscts: false
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - renesas,r9a07g043-sci
> +              - renesas,r9a07g044-sci
> +              - renesas,r9a07g054-sci
> +    then:
> +      properties:
> +        resets:
> +          maxItems: 1
> +
> +        power-domains:
> +          maxItems: 1
> +
> +      required:
> +        - resets
> +        - power-domains
>  
>  unevaluatedProperties: false
>  
> -- 
> 2.43.0
> 

RE: [PATCH v3 03/13] dt-bindings: serial: Add compatible for Renesas RZ/T2H SoC in sci

[Thierry Bultel]

Hi Rob,
thanks for you review

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: lundi 3 mars 2025 14:36
> To: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> Cc: thierry.bultel@linatsea.fr; linux-renesas-soc@vger.kernel.org;
> geert@linux-m68k.org; Paul Barker <paul.barker.ct@bp.renesas.com>; Geert
> Uytterhoeven <geert+renesas@glider.be>; linux-kernel@vger.kernel.org;
> linux-serial@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v3 03/13] dt-bindings: serial: Add compatible for
> Renesas RZ/T2H SoC in sci
> 
> On Wed, Feb 26, 2025 at 02:09:22PM +0100, Thierry Bultel wrote:
> > Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
> >
> > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> > Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
> > ---
> >  .../bindings/serial/renesas,sci.yaml          | 64 ++++++++++++-------
> >  1 file changed, 40 insertions(+), 24 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> > b/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> > index 64d3db6e54e5..2c4080283963 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> > @@ -9,9 +9,6 @@ title: Renesas Serial Communication Interface
> >  maintainers:
> >    - Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > -allOf:
> > -  - $ref: serial.yaml#
> > -
> >  properties:
> >    compatible:
> >      oneOf:
> > @@ -22,6 +19,8 @@ properties:
> >                - renesas,r9a07g054-sci     # RZ/V2L
> >            - const: renesas,sci            # generic SCI compatible UART
> >
> > +      - const: renesas,r9a09g077-sci      # RZ/T2H
> > +
> 
> Perhaps explain in the commit msg why the 'renesas,sci' is not applicable
> for this chip.


Would something like that be explicit enough ? 

"The SCI of RZ/T2H SoC (a.k.a r9a09g077), as a lot
of similarities with other Renesas SoCs like G2L, G3S and V2L,
but a different set of registers, that moreover are 32 bits instead
of 16 bits. 
This is why the 'renesas,sci' fallback does not apply for it".

Thanks !
Thierry

Re: [PATCH v3 03/13] dt-bindings: serial: Add compatible for Renesas RZ/T2H SoC in sci

[Geert Uytterhoeven]

Hi Thierry,

On Mon, 3 Mar 2025 at 16:10, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> > -----Original Message-----
> > From: Rob Herring <robh@kernel.org>
> > Sent: lundi 3 mars 2025 14:36
> > To: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> > Cc: thierry.bultel@linatsea.fr; linux-renesas-soc@vger.kernel.org;
> > geert@linux-m68k.org; Paul Barker <paul.barker.ct@bp.renesas.com>; Geert
> > Uytterhoeven <geert+renesas@glider.be>; linux-kernel@vger.kernel.org;
> > linux-serial@vger.kernel.org; devicetree@vger.kernel.org
> > Subject: Re: [PATCH v3 03/13] dt-bindings: serial: Add compatible for
> > Renesas RZ/T2H SoC in sci
> >
> > On Wed, Feb 26, 2025 at 02:09:22PM +0100, Thierry Bultel wrote:
> > > Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
> > >
> > > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> > > Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
> > > ---
> > >  .../bindings/serial/renesas,sci.yaml          | 64 ++++++++++++-------
> > >  1 file changed, 40 insertions(+), 24 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> > > b/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> > > index 64d3db6e54e5..2c4080283963 100644
> > > --- a/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> > > +++ b/Documentation/devicetree/bindings/serial/renesas,sci.yaml
> > > @@ -9,9 +9,6 @@ title: Renesas Serial Communication Interface
> > >  maintainers:
> > >    - Geert Uytterhoeven <geert+renesas@glider.be>
> > >
> > > -allOf:
> > > -  - $ref: serial.yaml#
> > > -
> > >  properties:
> > >    compatible:
> > >      oneOf:
> > > @@ -22,6 +19,8 @@ properties:
> > >                - renesas,r9a07g054-sci     # RZ/V2L
> > >            - const: renesas,sci            # generic SCI compatible UART
> > >
> > > +      - const: renesas,r9a09g077-sci      # RZ/T2H
> > > +
> >
> > Perhaps explain in the commit msg why the 'renesas,sci' is not applicable
> > for this chip.
>
> Would something like that be explicit enough ?
>
> "The SCI of RZ/T2H SoC (a.k.a r9a09g077), as a lot
> of similarities with other Renesas SoCs like G2L, G3S and V2L,
> but a different set of registers, that moreover are 32 bits instead
> of 16 bits.
> This is why the 'renesas,sci' fallback does not apply for it".

FTR, the registers being 32-bit instead of 8/16-bit wide is the least of
your problems... If it was just a SCI with 32-bit registers, you could
use "reg-io-width = <4>;" and "reg-shift = <2>;", and add support for
the latter to the driver (it already uses regshift on non-DT SuperH).

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 11/13] arm64: dts: renesas: Add initial support for renesas RZ/T2H SoC

[Thierry Bultel]

Add the initial dtsi for the RZ/T2H Soc:

- gic
- armv8-timer
- cpg clock
- sci0 uart

also add arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi, that keeps
all 4 CPUs enabled, for consistency with later support of -m24
and -m04 SoC revisions, that only have 2 and 1 Cortex-A55, respectively,
and that will use /delete-node/ to disable the missing CPUs.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g077.dtsi    | 129 ++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi |  13 ++
 2 files changed, 142 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
new file mode 100644
index 000000000000..80e7805f2561
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/T2H SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a09g077";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		l3_ca55: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-size = <0x100000>;
+			cache-level = <3>;
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a55";
+			reg = <0>;
+			device_type = "cpu";
+			next-level-cache = <&l3_ca55>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			device_type = "cpu";
+			next-level-cache = <&l3_ca55>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@200 {
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			device_type = "cpu";
+			next-level-cache = <&l3_ca55>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@300 {
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			device_type = "cpu";
+			next-level-cache = <&l3_ca55>;
+			enable-method = "psci";
+		};
+	};
+
+	loco_clk: loco {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		sci0: serial@80005000 {
+			compatible = "renesas,r9a09g077-sci";
+			reg = <0 0x80005000 0 0x400>;
+			interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 108>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		cpg: clock-controller@80280000 {
+			compatible = "renesas,r9a09g077-cpg-mssr";
+			reg = <0 0x80280000 0 0x1000>,
+			      <0 0x81280000 0 0x9000>;
+			clocks = <&extal_clk>, <&loco_clk>;
+			clock-names = "extal", "loco";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		gic: interrupt-controller@83000000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x83000000 0 0x40000>,
+			      <0x0 0x83040000 0 0x160000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
new file mode 100644
index 000000000000..6f4a11b39d12
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/T2H 4-core SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g077.dtsi"
+
+/ {
+	compatible = "renesas,r9a09g077m44", "renesas,r9a09g077";
+};
-- 
2.43.0

[PATCH v3 12/13] arm64: dts: renesas: Add initial support for renesas RZ/T2H eval board

[Thierry Bultel]

Add the initial device tree for the RZ/T2H evaluation board.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile          |  1 +
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    | 35 +++++++++++++++++++
 2 files changed, 36 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 928635f2e76b..ee1af560f5e6 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -148,6 +148,7 @@ dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb
 
+dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb
 dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb
 
 dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
new file mode 100644
index 000000000000..0fe3a08ca9c3
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/T2H Development EVK board
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+#include "r9a09g077m44.dtsi"
+
+/ {
+	model = "Renesas Development EVK based on r9a09g077m44";
+	compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077";
+
+	aliases {
+		serial0 = &sci0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&extal_clk {
+	clock-frequency = <25000000>;
+};
+
+&loco_clk {
+	clock-frequency = <1000000>;
+};
+
+&sci0 {
+	status = "okay";
+};
-- 
2.43.0

Re: [PATCH v3 12/13] arm64: dts: renesas: Add initial support for renesas RZ/T2H eval board

[Krzysztof Kozlowski]

On 26/02/2025 14:09, Thierry Bultel wrote:
> Add the initial device tree for the RZ/T2H evaluation board.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>

Where did this happen? I see tags only to few patches, not all of them.

Same questions for all other places.

Best regards,
Krzysztof

Re: [PATCH v3 12/13] arm64: dts: renesas: Add initial support for renesas RZ/T2H eval board

[Paul Barker]

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On 26/02/2025 14:23, Krzysztof Kozlowski wrote:
> On 26/02/2025 14:09, Thierry Bultel wrote:
>> Add the initial device tree for the RZ/T2H evaluation board.
>>
>> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
>> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
> 
> Where did this happen? I see tags only to few patches, not all of them.
> 
> Same questions for all other places.
> 
> Best regards,
> Krzysztof

Hi Krzysztof,

We've recently switched to a patchwork instance and internal mailing
list for review within our team before sending things to the mailing
list. We did a round of internal review and the Reviewed-by tags from
this have accidentally been included here. It can easily be fixed.

Thierry, could you re-send a v4 series keeping my Reviewed-by tag only
on patch 7/13, as that was added on the public mailing list.

Thanks,

-- 
Paul Barker

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Re: [PATCH v3 12/13] arm64: dts: renesas: Add initial support for renesas RZ/T2H eval board

[Krzysztof Kozlowski]

On 26/02/2025 15:46, Paul Barker wrote:
> On 26/02/2025 14:23, Krzysztof Kozlowski wrote:
>> On 26/02/2025 14:09, Thierry Bultel wrote:
>>> Add the initial device tree for the RZ/T2H evaluation board.
>>>
>>> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
>>> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
>>
>> Where did this happen? I see tags only to few patches, not all of them.
>>
>> Same questions for all other places.
>>
>> Best regards,
>> Krzysztof
> 
> Hi Krzysztof,
> 
> We've recently switched to a patchwork instance and internal mailing
> list for review within our team before sending things to the mailing
> list. We did a round of internal review and the Reviewed-by tags from
> this have accidentally been included here. It can easily be fixed.
> 
> Thierry, could you re-send a v4 series keeping my Reviewed-by tag only
> on patch 7/13, as that was added on the public mailing list.


Thanks for clarification. It is unusual to see internal review resulting
in tags between already publicly discussed versions. Why it cannot be
done in public where everything is both archived and visible to entire
community?

BTW, sometimes b4 makes mistakes and we already have at least two cases
tag from one patch was applied for entire set, so your case is
indistinguishable from such b4 issue.

Best regards,
Krzysztof