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Wed, 05 Mar 2025 20:02:38 -0800 (PST) Date: Thu, 6 Mar 2025 09:32:32 +0530 From: Manivannan Sadhasivam To: Krishna Chaitanya Chundru Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com Subject: Re: [PATCH v7 4/4] PCI: dwc: Add support for configuring lane equalization presets Message-ID: <20250306040232.rkvxirmeropy44mu@thinkpad> References: <20250225-preset_v6-v7-0-a593f3ef3951@oss.qualcomm.com> <20250225-preset_v6-v7-4-a593f3ef3951@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250225-preset_v6-v7-4-a593f3ef3951@oss.qualcomm.com> On Tue, Feb 25, 2025 at 05:15:07PM +0530, Krishna Chaitanya Chundru wrote: > PCIe equalization presets are predefined settings used to optimize > signal integrity by compensating for signal loss and distortion in > high-speed data transmission. > > Based upon the number of lanes and the data rate supported, write > the preset data read from the device tree in to the lane equalization > control registers. > > Signed-off-by: Krishna Chaitanya Chundru > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 66 +++++++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.h | 3 ++ > include/uapi/linux/pci_regs.h | 3 ++ > 3 files changed, 72 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index dd56cc02f4ef..ea596119de92 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -507,6 +507,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > if (pci->num_lanes < 1) > pci->num_lanes = dw_pcie_link_get_max_link_width(pci); > > + ret = of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes); > + if (ret) > + goto err_free_msi; > + > /* > * Allocate the resource for MSG TLP before programming the iATU > * outbound window in dw_pcie_setup_rc(). Since the allocation depends > @@ -808,6 +812,67 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > return 0; > } > > +static void dw_pcie_program_presets(struct dw_pcie_rp *pp, enum pci_bus_speed speed) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + u8 lane_eq_offset, lane_reg_size, cap_id; > + u8 *presets; > + u32 cap; > + int i; > + > + if (speed == PCIE_SPEED_8_0GT) { > + presets = (u8 *)pp->presets.eq_presets_8gts; > + lane_eq_offset = PCI_SECPCI_LE_CTRL; > + cap_id = PCI_EXT_CAP_ID_SECPCI; > + /* For data rate of 8 GT/S each lane equalization control is 16bits wide*/ > + lane_reg_size = 0x2; > + } else if (speed == PCIE_SPEED_16_0GT) { > + presets = pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS]; > + lane_eq_offset = PCI_PL_16GT_LE_CTRL; > + cap_id = PCI_EXT_CAP_ID_PL_16GT; > + lane_reg_size = 0x1; > + } else { > + dev_WARN_ONCE(pci->dev, 1, "Not supported data rate %s\n", > + pci_speed_string(speed)); No, this is not what I asked for. You should warn only when there is atleast one of the preset properties are specified in DT. But I think that would complicate the code. So let's just trust DT here and add the warning later if needed. > + return; > + } > + > + if (presets[0] == PCI_EQ_RESV) { > + dev_WARN_ONCE(pci->dev, 1, > + "Lane equalization preset properties are missing for %s\n", > + pci_speed_string(speed)); Same here. This is going to trigger warning on all DWC platforms. Please remove it. - Mani -- மணிவண்ணன் சதாசிவம்