From: Guangjie Song <guangjie.song@mediatek.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Richard Cochran <richardcochran@gmail.com>
Cc: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <netdev@vger.kernel.org>,
Guangjie Song <guangjie.song@mediatek.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: [PATCH 05/26] clk: mediatek: Add gate ops without disable
Date: Fri, 7 Mar 2025 11:27:01 +0800 [thread overview]
Message-ID: <20250307032942.10447-6-guangjie.song@mediatek.com> (raw)
In-Reply-To: <20250307032942.10447-1-guangjie.song@mediatek.com>
Add gate ops without .disable and the ops is used for gate which is not
allowed to disable but cannot affect its parent clock to disable.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
---
drivers/clk/mediatek/clk-gate.c | 6 ++++++
drivers/clk/mediatek/clk-gate.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index be6cf4a6d246..a36136c61252 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -273,6 +273,12 @@ const struct clk_ops mtk_clk_gate_ops_setclr = {
};
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr);
+const struct clk_ops mtk_clk_gate_ops_setclr_enable = {
+ .is_enabled = mtk_cg_bit_is_cleared,
+ .enable = mtk_cg_enable,
+};
+EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_setclr_enable);
+
const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
.is_enabled = mtk_cg_bit_is_set,
.enable = mtk_cg_enable_inv,
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index 7d93fc84ad51..d992e3edd457 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -16,6 +16,7 @@ struct device;
struct device_node;
extern const struct clk_ops mtk_clk_gate_ops_setclr;
+extern const struct clk_ops mtk_clk_gate_ops_setclr_enable;
extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
--
2.45.2
next prev parent reply other threads:[~2025-03-07 3:32 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-07 3:26 [PATCH 00/26] clk: mediatek: Add MT8196 clock support Guangjie Song
2025-03-07 3:26 ` [PATCH 01/26] clk: mediatek: Add defines for vote Guangjie Song
2025-03-07 3:26 ` [PATCH 02/26] clk: mediatek: Support voting for pll Guangjie Song
2025-03-07 3:26 ` [PATCH 03/26] clk: mediatek: Support voting for mux Guangjie Song
2025-03-10 14:12 ` AngeloGioacchino Del Regno
2025-03-07 3:27 ` [PATCH 04/26] clk: mediatek: Support voting for gate Guangjie Song
2025-03-07 3:27 ` Guangjie Song [this message]
2025-03-07 3:27 ` [PATCH 06/26] dt-bindings: clock: mediatek: Add new MT8196 clock Guangjie Song
2025-03-07 4:16 ` Rob Herring (Arm)
2025-03-07 7:29 ` Krzysztof Kozlowski
2025-04-16 9:20 ` Chen-Yu Tsai
2025-03-07 3:27 ` [PATCH 07/26] clk: mediatek: Add MT8196 apmixedsys clock support Guangjie Song
2025-03-11 17:05 ` Jeff Johnson
2025-03-07 3:27 ` [PATCH 08/26] clk: mediatek: Add MT8196 apmixedsys_gp2 " Guangjie Song
2025-03-07 3:27 ` [PATCH 09/26] clk: mediatek: Add MT8196 topckgen " Guangjie Song
2025-04-16 9:04 ` Chen-Yu Tsai
2025-03-07 3:27 ` [PATCH 10/26] clk: mediatek: Add MT8196 topckgen2 " Guangjie Song
2025-03-07 3:27 ` [PATCH 11/26] clk: mediatek: Add MT8196 vlpckgen " Guangjie Song
2025-03-07 3:27 ` [PATCH 12/26] clk: mediatek: Add MT8196 peripheral " Guangjie Song
2025-03-07 3:27 ` [PATCH 13/26] clk: mediatek: Add MT8196 adsp " Guangjie Song
2025-03-07 3:27 ` [PATCH 14/26] clk: mediatek: Add MT8196 i2c " Guangjie Song
2025-03-07 3:27 ` [PATCH 15/26] clk: mediatek: Add MT8196 mcu " Guangjie Song
2025-03-07 3:27 ` [PATCH 16/26] clk: mediatek: Add MT8196 mdpsys " Guangjie Song
2025-03-07 3:27 ` [PATCH 17/26] clk: mediatek: Add MT8196 mfg " Guangjie Song
2025-03-07 3:27 ` [PATCH 18/26] clk: mediatek: Add MT8196 disp0 " Guangjie Song
2025-03-07 3:27 ` [PATCH 19/26] clk: mediatek: Add MT8196 disp1 " Guangjie Song
2025-03-07 3:27 ` [PATCH 20/26] clk: mediatek: Add MT8196 disp-ao " Guangjie Song
2025-03-07 3:27 ` [PATCH 21/26] clk: mediatek: Add MT8196 ovl0 " Guangjie Song
2025-03-07 7:29 ` Krzysztof Kozlowski
2025-03-07 3:27 ` [PATCH 22/26] clk: mediatek: Add MT8196 ovl1 " Guangjie Song
2025-03-07 3:27 ` [PATCH 23/26] clk: mediatek: Add MT8196 pextpsys " Guangjie Song
2025-03-07 3:27 ` [PATCH 24/26] clk: mediatek: Add MT8196 ufssys " Guangjie Song
2025-03-07 3:27 ` [PATCH 25/26] clk: mediatek: Add MT8196 vdecsys " Guangjie Song
2025-03-07 3:27 ` [PATCH 26/26] clk: mediatek: Add MT8196 vencsys " Guangjie Song
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