* [PATCH v2 0/3] ARM: tegra: complete Tegra 4 and Tegra K1 device trees
@ 2025-03-07 8:10 Svyatoslav Ryhel
2025-03-07 8:10 ` [PATCH v2 1/3] dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114 and Tegra124 Svyatoslav Ryhel
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Svyatoslav Ryhel @ 2025-03-07 8:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
Jonathan Hunter, Svyatoslav Ryhel
Cc: devicetree, linux-tegra, linux-kernel
Complete T114 and T124 device trees.
---
Changes in v2:
- dropped accepted commits
- added EPP, MPE and ISP compatibility for T114 and T124
- added TSEC schema
---
Svyatoslav Ryhel (3):
dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for
Tegra114 and Tegra124
ARM: tegra114: complete HOST1X devices binding
ARM: tegra124: complete HOST1X devices binding
.../display/tegra/nvidia,tegra114-tsec.yaml | 70 +++++++++++++++++++
.../display/tegra/nvidia,tegra20-epp.yaml | 12 ++--
.../display/tegra/nvidia,tegra20-isp.yaml | 16 +++--
.../display/tegra/nvidia,tegra20-mpe.yaml | 30 ++++++--
arch/arm/boot/dts/nvidia/tegra114.dtsi | 65 +++++++++++++++++
arch/arm/boot/dts/nvidia/tegra124.dtsi | 65 +++++++++++++++++
6 files changed, 244 insertions(+), 14 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 1/3] dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114 and Tegra124
2025-03-07 8:10 [PATCH v2 0/3] ARM: tegra: complete Tegra 4 and Tegra K1 device trees Svyatoslav Ryhel
@ 2025-03-07 8:10 ` Svyatoslav Ryhel
2025-03-07 14:06 ` Krzysztof Kozlowski
2025-03-07 8:10 ` [PATCH v2 2/3] ARM: tegra114: complete HOST1X devices binding Svyatoslav Ryhel
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Svyatoslav Ryhel @ 2025-03-07 8:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
Jonathan Hunter, Svyatoslav Ryhel
Cc: devicetree, linux-tegra, linux-kernel
The current EPP, ISP and MPE schemas are largely compatible with Tegra114 and Tegra124,
requiring only minor adjustments. Additionally, the TSEC schema for the Security engine,
which is available from Tegra114 onwards, is included.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
.../display/tegra/nvidia,tegra114-tsec.yaml | 70 +++++++++++++++++++
.../display/tegra/nvidia,tegra20-epp.yaml | 12 ++--
.../display/tegra/nvidia,tegra20-isp.yaml | 16 +++--
.../display/tegra/nvidia,tegra20-mpe.yaml | 30 ++++++--
4 files changed, 114 insertions(+), 14 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml
new file mode 100644
index 000000000000..84d9ab9394d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Security co-processor
+
+maintainers:
+ - Svyatoslav Ryhel <clamor95@gmail.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: nvidia,tegra114-tsec
+ - const: nvidia,tegra124-tsec
+ - items:
+ - const: nvidia,tegra132-tsec
+ - const: nvidia,tegra124-tsec
+ - const: nvidia,tegra210-tsec
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: module clock
+
+ resets:
+ items:
+ - description: module reset
+
+ reset-names:
+ items:
+ - const: tsec
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 6
+
+ interconnect-names:
+ maxItems: 6
+
+ operating-points-v2: true
+
+ power-domains:
+ items:
+ - description: phandle to the core power domain
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra114-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ tsec@54500000 {
+ compatible = "nvidia,tegra114-tsec";
+ reg = <0x54500000 0x00040000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_TSEC>;
+ resets = <&tegra_car TEGRA114_CLK_TSEC>;
+ reset-names = "tsec";
+ };
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
index 3c095a5491fe..a50e3261a191 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
@@ -15,10 +15,14 @@ properties:
pattern: "^epp@[0-9a-f]+$"
compatible:
- enum:
- - nvidia,tegra20-epp
- - nvidia,tegra30-epp
- - nvidia,tegra114-epp
+ oneOf:
+ - const: nvidia,tegra20-epp
+ - const: nvidia,tegra30-epp
+ - const: nvidia,tegra114-epp
+ - const: nvidia,tegra124-epp
+ - items:
+ - const: nvidia,tegra132-epp
+ - const: nvidia,tegra124-epp
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
index 3bc3b22e98e1..bfef4f26a3d7 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
@@ -11,11 +11,19 @@ maintainers:
- Jon Hunter <jonathanh@nvidia.com>
properties:
+ $nodename:
+ pattern: "^isp@[0-9a-f]+$"
+
compatible:
- enum:
- - nvidia,tegra20-isp
- - nvidia,tegra30-isp
- - nvidia,tegra210-isp
+ oneOf:
+ - const: nvidia,tegra20-isp
+ - const: nvidia,tegra30-isp
+ - const: nvidia,tegra114-isp
+ - const: nvidia,tegra124-isp
+ - items:
+ - const: nvidia,tegra132-isp
+ - const: nvidia,tegra124-isp
+ - const: nvidia,tegra210-isp
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
index 2cd3e60cd0a8..35e3991f1135 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
@@ -12,13 +12,19 @@ maintainers:
properties:
$nodename:
- pattern: "^mpe@[0-9a-f]+$"
+ oneOf:
+ - pattern: "^mpe@[0-9a-f]+$"
+ - pattern: "^msenc@[0-9a-f]+$"
compatible:
- enum:
- - nvidia,tegra20-mpe
- - nvidia,tegra30-mpe
- - nvidia,tegra114-mpe
+ oneOf:
+ - const: nvidia,tegra20-mpe
+ - const: nvidia,tegra30-mpe
+ - const: nvidia,tegra114-msenc
+ - const: nvidia,tegra124-msenc
+ - items:
+ - const: nvidia,tegra132-msenc
+ - const: nvidia,tegra124-msenc
reg:
maxItems: 1
@@ -36,7 +42,9 @@ properties:
reset-names:
items:
- - const: mpe
+ - enum:
+ - mpe
+ - msenc
iommus:
maxItems: 1
@@ -58,6 +66,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
+ #include <dt-bindings/clock/tegra114-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mpe@54040000 {
@@ -68,3 +77,12 @@ examples:
resets = <&tegra_car 60>;
reset-names = "mpe";
};
+
+ msenc@544c0000 {
+ compatible = "nvidia,tegra114-msenc";
+ reg = <0x544c0000 0x00040000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_MSENC>;
+ resets = <&tegra_car TEGRA114_CLK_MSENC>;
+ reset-names = "msenc";
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 2/3] ARM: tegra114: complete HOST1X devices binding
2025-03-07 8:10 [PATCH v2 0/3] ARM: tegra: complete Tegra 4 and Tegra K1 device trees Svyatoslav Ryhel
2025-03-07 8:10 ` [PATCH v2 1/3] dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114 and Tegra124 Svyatoslav Ryhel
@ 2025-03-07 8:10 ` Svyatoslav Ryhel
2025-03-07 8:10 ` [PATCH v2 3/3] ARM: tegra124: " Svyatoslav Ryhel
2025-03-07 13:25 ` [PATCH v2 0/3] ARM: tegra: complete Tegra 4 and Tegra K1 device trees Rob Herring (Arm)
3 siblings, 0 replies; 7+ messages in thread
From: Svyatoslav Ryhel @ 2025-03-07 8:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
Jonathan Hunter, Svyatoslav Ryhel
Cc: devicetree, linux-tegra, linux-kernel
Add nodes for devices on the HOST1X bus: VI, EPP, ISP, MSENC and TSEC.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
arch/arm/boot/dts/nvidia/tegra114.dtsi | 65 ++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
index 4caf2073c556..e2623a0629d2 100644
--- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
@@ -47,6 +47,45 @@ host1x@50000000 {
ranges = <0x54000000 0x54000000 0x01000000>;
+ vi@54080000 {
+ compatible = "nvidia,tegra114-vi";
+ reg = <0x54080000 0x00040000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_VI>;
+ resets = <&tegra_car 20>;
+ reset-names = "vi";
+
+ iommus = <&mc TEGRA_SWGROUP_VI>;
+
+ status = "disabled";
+ };
+
+ epp@540c0000 {
+ compatible = "nvidia,tegra114-epp";
+ reg = <0x540c0000 0x00040000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_EPP>;
+ resets = <&tegra_car TEGRA114_CLK_EPP>;
+ reset-names = "epp";
+
+ iommus = <&mc TEGRA_SWGROUP_EPP>;
+
+ status = "disabled";
+ };
+
+ isp@54100000 {
+ compatible = "nvidia,tegra114-isp";
+ reg = <0x54100000 0x00040000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_ISP>;
+ resets = <&tegra_car TEGRA114_CLK_ISP>;
+ reset-names = "isp";
+
+ iommus = <&mc TEGRA_SWGROUP_ISP>;
+
+ status = "disabled";
+ };
+
gr2d@54140000 {
compatible = "nvidia,tegra114-gr2d";
reg = <0x54140000 0x00040000>;
@@ -149,6 +188,32 @@ dsib: dsi@54400000 {
#address-cells = <1>;
#size-cells = <0>;
};
+
+ msenc@544c0000 {
+ compatible = "nvidia,tegra114-msenc";
+ reg = <0x544c0000 0x00040000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_MSENC>;
+ resets = <&tegra_car TEGRA114_CLK_MSENC>;
+ reset-names = "msenc";
+
+ iommus = <&mc TEGRA_SWGROUP_MSENC>;
+
+ status = "disabled";
+ };
+
+ tsec@54500000 {
+ compatible = "nvidia,tegra114-tsec";
+ reg = <0x54500000 0x00040000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_TSEC>;
+ resets = <&tegra_car TEGRA114_CLK_TSEC>;
+ reset-names = "tsec";
+
+ iommus = <&mc TEGRA_SWGROUP_TSEC>;
+
+ status = "disabled";
+ };
};
gic: interrupt-controller@50041000 {
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 3/3] ARM: tegra124: complete HOST1X devices binding
2025-03-07 8:10 [PATCH v2 0/3] ARM: tegra: complete Tegra 4 and Tegra K1 device trees Svyatoslav Ryhel
2025-03-07 8:10 ` [PATCH v2 1/3] dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114 and Tegra124 Svyatoslav Ryhel
2025-03-07 8:10 ` [PATCH v2 2/3] ARM: tegra114: complete HOST1X devices binding Svyatoslav Ryhel
@ 2025-03-07 8:10 ` Svyatoslav Ryhel
2025-03-07 14:05 ` Svyatoslav Ryhel
2025-03-07 13:25 ` [PATCH v2 0/3] ARM: tegra: complete Tegra 4 and Tegra K1 device trees Rob Herring (Arm)
3 siblings, 1 reply; 7+ messages in thread
From: Svyatoslav Ryhel @ 2025-03-07 8:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
Jonathan Hunter, Svyatoslav Ryhel
Cc: devicetree, linux-tegra, linux-kernel
Add nodes for devices on the HOST1X bus: VI, ISP, ISPB, MSENC and TSEC.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
arch/arm/boot/dts/nvidia/tegra124.dtsi | 65 ++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi
index ec4f0e346b2b..8181e5d88654 100644
--- a/arch/arm/boot/dts/nvidia/tegra124.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi
@@ -103,6 +103,45 @@ host1x@50000000 {
ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
+ vi@54080000 {
+ compatible = "nvidia,tegra124-vi";
+ reg = <0x0 0x54080000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_VI>;
+ resets = <&tegra_car 20>;
+ reset-names = "vi";
+
+ iommus = <&mc TEGRA_SWGROUP_VI>;
+
+ status = "disabled";
+ };
+
+ isp@54600000 {
+ compatible = "nvidia,tegra124-isp";
+ reg = <0x0 0x54600000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_ISP>;
+ resets = <&tegra_car TEGRA124_CLK_ISP>;
+ reset-names = "isp";
+
+ iommus = <&mc TEGRA_SWGROUP_ISP2>;
+
+ status = "disabled";
+ };
+
+ isp@54680000 {
+ compatible = "nvidia,tegra124-isp";
+ reg = <0x0 0x54680000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_ISPB>;
+ resets = <&tegra_car TEGRA124_CLK_ISPB>;
+ reset-names = "ispb";
+
+ iommus = <&mc TEGRA_SWGROUP_ISP2B>;
+
+ status = "disabled";
+ };
+
dc@54200000 {
compatible = "nvidia,tegra124-dc";
reg = <0x0 0x54200000 0x0 0x00040000>;
@@ -209,6 +248,32 @@ dsib: dsi@54400000 {
#size-cells = <0>;
};
+ msenc@544c0000 {
+ compatible = "nvidia,tegra124-msenc";
+ reg = <0x0 0x544c0000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_MSENC>;
+ resets = <&tegra_car TEGRA124_CLK_MSENC>;
+ reset-names = "msenc";
+
+ iommus = <&mc TEGRA_SWGROUP_MSENC>;
+
+ status = "disabled";
+ };
+
+ tsec@54500000 {
+ compatible = "nvidia,tegra124-tsec";
+ reg = <0x0 0x54500000 0x0 0x00040000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_TSEC>;
+ resets = <&tegra_car TEGRA124_CLK_TSEC>;
+ reset-names = "tsec";
+
+ iommus = <&mc TEGRA_SWGROUP_TSEC>;
+
+ status = "disabled";
+ };
+
sor@54540000 {
compatible = "nvidia,tegra124-sor";
reg = <0x0 0x54540000 0x0 0x00040000>;
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 0/3] ARM: tegra: complete Tegra 4 and Tegra K1 device trees
2025-03-07 8:10 [PATCH v2 0/3] ARM: tegra: complete Tegra 4 and Tegra K1 device trees Svyatoslav Ryhel
` (2 preceding siblings ...)
2025-03-07 8:10 ` [PATCH v2 3/3] ARM: tegra124: " Svyatoslav Ryhel
@ 2025-03-07 13:25 ` Rob Herring (Arm)
3 siblings, 0 replies; 7+ messages in thread
From: Rob Herring (Arm) @ 2025-03-07 13:25 UTC (permalink / raw)
To: Svyatoslav Ryhel
Cc: Conor Dooley, Krzysztof Kozlowski, devicetree, Thierry Reding,
Jonathan Hunter, linux-kernel, linux-tegra
On Fri, 07 Mar 2025 10:10:44 +0200, Svyatoslav Ryhel wrote:
> Complete T114 and T124 device trees.
>
> ---
> Changes in v2:
> - dropped accepted commits
> - added EPP, MPE and ISP compatibility for T114 and T124
> - added TSEC schema
> ---
>
> Svyatoslav Ryhel (3):
> dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for
> Tegra114 and Tegra124
> ARM: tegra114: complete HOST1X devices binding
> ARM: tegra124: complete HOST1X devices binding
>
> .../display/tegra/nvidia,tegra114-tsec.yaml | 70 +++++++++++++++++++
> .../display/tegra/nvidia,tegra20-epp.yaml | 12 ++--
> .../display/tegra/nvidia,tegra20-isp.yaml | 16 +++--
> .../display/tegra/nvidia,tegra20-mpe.yaml | 30 ++++++--
> arch/arm/boot/dts/nvidia/tegra114.dtsi | 65 +++++++++++++++++
> arch/arm/boot/dts/nvidia/tegra124.dtsi | 65 +++++++++++++++++
> 6 files changed, 244 insertions(+), 14 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml
>
> --
> 2.43.0
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/nvidia/' for 20250307081047.13724-1-clamor95@gmail.com:
arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dtb: isp@54680000: reset-names:0: 'isp' was expected
from schema $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
arch/arm/boot/dts/nvidia/tegra124-nyan-blaze.dtb: isp@54680000: reset-names:0: 'isp' was expected
from schema $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dtb: isp@54680000: reset-names:0: 'isp' was expected
from schema $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
arch/arm/boot/dts/nvidia/tegra124-nyan-big.dtb: isp@54680000: reset-names:0: 'isp' was expected
from schema $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
arch/arm/boot/dts/nvidia/tegra124-venice2.dtb: isp@54680000: reset-names:0: 'isp' was expected
from schema $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
arch/arm/boot/dts/nvidia/tegra124-nyan-big-fhd.dtb: isp@54680000: reset-names:0: 'isp' was expected
from schema $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
arch/arm/boot/dts/nvidia/tegra124-jetson-tk1.dtb: isp@54680000: reset-names:0: 'isp' was expected
from schema $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 3/3] ARM: tegra124: complete HOST1X devices binding
2025-03-07 8:10 ` [PATCH v2 3/3] ARM: tegra124: " Svyatoslav Ryhel
@ 2025-03-07 14:05 ` Svyatoslav Ryhel
0 siblings, 0 replies; 7+ messages in thread
From: Svyatoslav Ryhel @ 2025-03-07 14:05 UTC (permalink / raw)
To: Thierry Reding
Cc: devicetree, Svyatoslav Ryhel, Jonathan Hunter, linux-tegra,
linux-kernel, Conor Dooley, Krzysztof Kozlowski, Rob Herring
пт, 7 бер. 2025 р. о 10:11 Svyatoslav Ryhel <clamor95@gmail.com> пише:
>
> Add nodes for devices on the HOST1X bus: VI, ISP, ISPB, MSENC and TSEC.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> arch/arm/boot/dts/nvidia/tegra124.dtsi | 65 ++++++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
>
> diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi
> index ec4f0e346b2b..8181e5d88654 100644
> --- a/arch/arm/boot/dts/nvidia/tegra124.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi
> @@ -103,6 +103,45 @@ host1x@50000000 {
>
> ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
>
> + vi@54080000 {
> + compatible = "nvidia,tegra124-vi";
> + reg = <0x0 0x54080000 0x0 0x00040000>;
> + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&tegra_car TEGRA124_CLK_VI>;
> + resets = <&tegra_car 20>;
> + reset-names = "vi";
> +
> + iommus = <&mc TEGRA_SWGROUP_VI>;
> +
> + status = "disabled";
> + };
> +
> + isp@54600000 {
> + compatible = "nvidia,tegra124-isp";
> + reg = <0x0 0x54600000 0x0 0x00040000>;
> + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&tegra_car TEGRA124_CLK_ISP>;
> + resets = <&tegra_car TEGRA124_CLK_ISP>;
> + reset-names = "isp";
> +
> + iommus = <&mc TEGRA_SWGROUP_ISP2>;
> +
> + status = "disabled";
> + };
> +
> + isp@54680000 {
> + compatible = "nvidia,tegra124-isp";
> + reg = <0x0 0x54680000 0x0 0x00040000>;
> + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&tegra_car TEGRA124_CLK_ISPB>;
> + resets = <&tegra_car TEGRA124_CLK_ISPB>;
> + reset-names = "ispb";
Thierry, here ispb is typo and should be just isp, obviously. I can
re-upload patchset or you may adjust it when applying. Let me know
what you would prefer.
> +
> + iommus = <&mc TEGRA_SWGROUP_ISP2B>;
> +
> + status = "disabled";
> + };
> +
> dc@54200000 {
> compatible = "nvidia,tegra124-dc";
> reg = <0x0 0x54200000 0x0 0x00040000>;
> @@ -209,6 +248,32 @@ dsib: dsi@54400000 {
> #size-cells = <0>;
> };
>
> + msenc@544c0000 {
> + compatible = "nvidia,tegra124-msenc";
> + reg = <0x0 0x544c0000 0x0 0x00040000>;
> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&tegra_car TEGRA124_CLK_MSENC>;
> + resets = <&tegra_car TEGRA124_CLK_MSENC>;
> + reset-names = "msenc";
> +
> + iommus = <&mc TEGRA_SWGROUP_MSENC>;
> +
> + status = "disabled";
> + };
> +
> + tsec@54500000 {
> + compatible = "nvidia,tegra124-tsec";
> + reg = <0x0 0x54500000 0x0 0x00040000>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&tegra_car TEGRA124_CLK_TSEC>;
> + resets = <&tegra_car TEGRA124_CLK_TSEC>;
> + reset-names = "tsec";
> +
> + iommus = <&mc TEGRA_SWGROUP_TSEC>;
> +
> + status = "disabled";
> + };
> +
> sor@54540000 {
> compatible = "nvidia,tegra124-sor";
> reg = <0x0 0x54540000 0x0 0x00040000>;
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114 and Tegra124
2025-03-07 8:10 ` [PATCH v2 1/3] dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114 and Tegra124 Svyatoslav Ryhel
@ 2025-03-07 14:06 ` Krzysztof Kozlowski
0 siblings, 0 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2025-03-07 14:06 UTC (permalink / raw)
To: Svyatoslav Ryhel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Thierry Reding, Jonathan Hunter
Cc: devicetree, linux-tegra, linux-kernel
On 07/03/2025 09:10, Svyatoslav Ryhel wrote:
> The current EPP, ISP and MPE schemas are largely compatible with Tegra114 and Tegra124,
> requiring only minor adjustments. Additionally, the TSEC schema for the Security engine,
> which is available from Tegra114 onwards, is included.
Please wrap commit message according to Linux coding style / submission
process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> .../display/tegra/nvidia,tegra114-tsec.yaml | 70 +++++++++++++++++++
> .../display/tegra/nvidia,tegra20-epp.yaml | 12 ++--
> .../display/tegra/nvidia,tegra20-isp.yaml | 16 +++--
> .../display/tegra/nvidia,tegra20-mpe.yaml | 30 ++++++--
> 4 files changed, 114 insertions(+), 14 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml
> new file mode 100644
> index 000000000000..84d9ab9394d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra Security co-processor
How security processor is related to display?
> +
> +maintainers:
> + - Svyatoslav Ryhel <clamor95@gmail.com>
> + - Thierry Reding <thierry.reding@gmail.com>
Please provide description of the hardware here.
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: nvidia,tegra114-tsec
> + - const: nvidia,tegra124-tsec
That's just enum
> + - items:
> + - const: nvidia,tegra132-tsec
> + - const: nvidia,tegra124-tsec
> + - const: nvidia,tegra210-tsec
And this goes to enum.
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: module clock
Instead: maxItems: 1
> +
> + resets:
> + items:
> + - description: module reset
Instead: maxItems: 1
> +
> + reset-names:
> + items:
> + - const: tsec
Drop reset-names, redundant.
> +
> + iommus:
> + maxItems: 1
> +
> + interconnects:
> + maxItems: 6
You need to list the items.
> +
> + interconnect-names:
> + maxItems: 6
You need to list the items.
> +
> + operating-points-v2: true
No opp-table?
> +
> + power-domains:
> + items:
> + - description: phandle to the core power domain
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/tegra114-car.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + tsec@54500000 {
> + compatible = "nvidia,tegra114-tsec";
> + reg = <0x54500000 0x00040000>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&tegra_car TEGRA114_CLK_TSEC>;
> + resets = <&tegra_car TEGRA114_CLK_TSEC>;
> + reset-names = "tsec";
> + };
> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
> index 3c095a5491fe..a50e3261a191 100644
> --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
> @@ -15,10 +15,14 @@ properties:
> pattern: "^epp@[0-9a-f]+$"
>
> compatible:
> - enum:
> - - nvidia,tegra20-epp
> - - nvidia,tegra30-epp
> - - nvidia,tegra114-epp
> + oneOf:
> + - const: nvidia,tegra20-epp
> + - const: nvidia,tegra30-epp
> + - const: nvidia,tegra114-epp
> + - const: nvidia,tegra124-epp
No, that was an enum.
> + - items:
> + - const: nvidia,tegra132-epp
> + - const: nvidia,tegra124-epp
>
> reg:
> maxItems: 1
> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
> index 3bc3b22e98e1..bfef4f26a3d7 100644
> --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
> @@ -11,11 +11,19 @@ maintainers:
> - Jon Hunter <jonathanh@nvidia.com>
>
> properties:
> + $nodename:
> + pattern: "^isp@[0-9a-f]+$"
Why?
Nothing in commit msg explains this.
> +
> compatible:
> - enum:
> - - nvidia,tegra20-isp
> - - nvidia,tegra30-isp
> - - nvidia,tegra210-isp
> + oneOf:
> + - const: nvidia,tegra20-isp
> + - const: nvidia,tegra30-isp
> + - const: nvidia,tegra114-isp
> + - const: nvidia,tegra124-isp
> + - items:
> + - const: nvidia,tegra132-isp
> + - const: nvidia,tegra124-isp
> + - const: nvidia,tegra210-isp
>
> reg:
> maxItems: 1
> diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
> index 2cd3e60cd0a8..35e3991f1135 100644
> --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
> +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
> @@ -12,13 +12,19 @@ maintainers:
>
> properties:
> $nodename:
> - pattern: "^mpe@[0-9a-f]+$"
> + oneOf:
> + - pattern: "^mpe@[0-9a-f]+$"
> + - pattern: "^msenc@[0-9a-f]+$"
>
> compatible:
> - enum:
> - - nvidia,tegra20-mpe
> - - nvidia,tegra30-mpe
> - - nvidia,tegra114-mpe
> + oneOf:
> + - const: nvidia,tegra20-mpe
> + - const: nvidia,tegra30-mpe
> + - const: nvidia,tegra114-msenc
> + - const: nvidia,tegra124-msenc
> + - items:
> + - const: nvidia,tegra132-msenc
> + - const: nvidia,tegra124-msenc
>
> reg:
> maxItems: 1
> @@ -36,7 +42,9 @@ properties:
>
> reset-names:
> items:
> - - const: mpe
> + - enum:
> + - mpe
> + - msenc
No, why? That's redundant. Having names equal to module name brings zero
benefits. This change even shows that it is counter productive.
>
> iommus:
> maxItems: 1
> @@ -58,6 +66,7 @@ additionalProperties: false
> examples:
> - |
> #include <dt-bindings/clock/tegra20-car.h>
> + #include <dt-bindings/clock/tegra114-car.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> mpe@54040000 {
> @@ -68,3 +77,12 @@ examples:
> resets = <&tegra_car 60>;
> reset-names = "mpe";
> };
> +
> + msenc@544c0000 {
> + compatible = "nvidia,tegra114-msenc";
Difference in compatible does not mean you need new example.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-03-07 14:07 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2025-03-07 8:10 [PATCH v2 0/3] ARM: tegra: complete Tegra 4 and Tegra K1 device trees Svyatoslav Ryhel
2025-03-07 8:10 ` [PATCH v2 1/3] dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114 and Tegra124 Svyatoslav Ryhel
2025-03-07 14:06 ` Krzysztof Kozlowski
2025-03-07 8:10 ` [PATCH v2 2/3] ARM: tegra114: complete HOST1X devices binding Svyatoslav Ryhel
2025-03-07 8:10 ` [PATCH v2 3/3] ARM: tegra124: " Svyatoslav Ryhel
2025-03-07 14:05 ` Svyatoslav Ryhel
2025-03-07 13:25 ` [PATCH v2 0/3] ARM: tegra: complete Tegra 4 and Tegra K1 device trees Rob Herring (Arm)
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