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([188.163.112.51]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498b0bd148sm409886e87.139.2025.03.07.00.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 00:11:23 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] ARM: tegra124: complete HOST1X devices binding Date: Fri, 7 Mar 2025 10:10:47 +0200 Message-ID: <20250307081047.13724-4-clamor95@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307081047.13724-1-clamor95@gmail.com> References: <20250307081047.13724-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add nodes for devices on the HOST1X bus: VI, ISP, ISPB, MSENC and TSEC. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra124.dtsi | 65 ++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi index ec4f0e346b2b..8181e5d88654 100644 --- a/arch/arm/boot/dts/nvidia/tegra124.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi @@ -103,6 +103,45 @@ host1x@50000000 { ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; + vi@54080000 { + compatible = "nvidia,tegra124-vi"; + reg = <0x0 0x54080000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_VI>; + resets = <&tegra_car 20>; + reset-names = "vi"; + + iommus = <&mc TEGRA_SWGROUP_VI>; + + status = "disabled"; + }; + + isp@54600000 { + compatible = "nvidia,tegra124-isp"; + reg = <0x0 0x54600000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_ISP>; + resets = <&tegra_car TEGRA124_CLK_ISP>; + reset-names = "isp"; + + iommus = <&mc TEGRA_SWGROUP_ISP2>; + + status = "disabled"; + }; + + isp@54680000 { + compatible = "nvidia,tegra124-isp"; + reg = <0x0 0x54680000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_ISPB>; + resets = <&tegra_car TEGRA124_CLK_ISPB>; + reset-names = "ispb"; + + iommus = <&mc TEGRA_SWGROUP_ISP2B>; + + status = "disabled"; + }; + dc@54200000 { compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54200000 0x0 0x00040000>; @@ -209,6 +248,32 @@ dsib: dsi@54400000 { #size-cells = <0>; }; + msenc@544c0000 { + compatible = "nvidia,tegra124-msenc"; + reg = <0x0 0x544c0000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_MSENC>; + resets = <&tegra_car TEGRA124_CLK_MSENC>; + reset-names = "msenc"; + + iommus = <&mc TEGRA_SWGROUP_MSENC>; + + status = "disabled"; + }; + + tsec@54500000 { + compatible = "nvidia,tegra124-tsec"; + reg = <0x0 0x54500000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_TSEC>; + resets = <&tegra_car TEGRA124_CLK_TSEC>; + reset-names = "tsec"; + + iommus = <&mc TEGRA_SWGROUP_TSEC>; + + status = "disabled"; + }; + sor@54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; -- 2.43.0