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Sat, 08 Mar 2025 21:46:17 -0800 (PST) X-Google-Smtp-Source: AGHT+IHpXqA038rP5Ggw9FlFgm2R1a8pt/wT19XpVDrbhWVSi8/6/02dn0OjIxmQlm1MEEX4hHMNXg== X-Received: by 2002:a17:90b:38c8:b0:2f4:434d:c7f0 with SMTP id 98e67ed59e1d1-2ff7ce6f953mr18165010a91.12.1741499177081; Sat, 08 Mar 2025 21:46:17 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-224109ddbe7sm54887145ad.32.2025.03.08.21.46.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 21:46:16 -0800 (PST) From: Krishna Chaitanya Chundru Date: Sun, 09 Mar 2025 11:15:24 +0530 Subject: [PATCH v5 2/7] dt-bindings: PCI: qcom,pcie-sc7280: Make elbi register as an optional Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250309-ecam_v4-v5-2-8eff4b59790d@oss.qualcomm.com> References: <20250309-ecam_v4-v5-0-8eff4b59790d@oss.qualcomm.com> In-Reply-To: <20250309-ecam_v4-v5-0-8eff4b59790d@oss.qualcomm.com> To: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Jingoo Han Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_vpernami@quicinc.com, mmareddy@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1741499159; l=2186; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=6JdyMzO3Asj5w7yUT2KkJzLVL1A/xKSGY1cxjeq4fyQ=; b=wz1RB9CXvA8FGeEILDGOtYlFi4p2TQya48Fiatx6S46kOpMoDY1ohGf+sdniCzvoZ2ws8OA/k hSP+7NLXgblDQqH1P4Qrrnfs+nYUCwlZ/IZcFXRdsO5ve/HfIVR5Zim X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Authority-Analysis: v=2.4 cv=ctthk04i c=1 sm=1 tr=0 ts=67cd2b2a cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=0GabsJuRgD0JYX3L1DcA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 5dv-pOS7dVomANWlTjNqmEEn8m5YWPY9 X-Proofpoint-GUID: 5dv-pOS7dVomANWlTjNqmEEn8m5YWPY9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-09_02,2025-03-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 lowpriorityscore=0 phishscore=0 adultscore=0 mlxscore=0 impostorscore=0 mlxlogscore=886 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503090043 ELBI regitsers are optional registers and not been using in this platform. Having this register as required is not allowing to enable ECAM feature of the PCIe cleanly. ECAM feature needs to do single remap of entire 256MB which includes DBI and ELBI. Having optional ELBI registers in the devicetree and binding is causing resorce conflicts when enabling ECAM feature. So, make ELBI registers as optional one. Suggested-by: Manivannan Sadhasivam Signed-off-by: Krishna Chaitanya Chundru --- Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml index 76cb9fbfd476..326059a59b61 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml @@ -19,17 +19,17 @@ properties: const: qcom,pcie-sc7280 reg: - minItems: 5 + minItems: 4 maxItems: 6 reg-names: - minItems: 5 + minItems: 4 items: - const: parf # Qualcomm specific registers - const: dbi # DesignWare PCIe registers - - const: elbi # External local bus interface registers - const: atu # ATU address space - const: config # PCIe configuration space + - const: elbi # External local bus interface registers - const: mhi # MHI registers clocks: @@ -94,10 +94,9 @@ examples: compatible = "qcom,pcie-sc7280"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, <0 0x40001000 0 0x1000>, <0 0x40100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + reg-names = "parf", "dbi", "atu", "config"; ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; -- 2.34.1