Devicetree
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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
	 manivannan.sadhasivam@linaro.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org,  vkoul@kernel.org,
	kishon@kernel.org, andersson@kernel.org, konradybcio@kernel.org,
	 dmitry.baryshkov@linaro.org, neil.armstrong@linaro.org,
	abel.vesa@linaro.org,  quic_qianyu@quicinc.com,
	quic_krichai@quicinc.com, johan+linaro@kernel.org,
	 linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org,  linux-kernel@vger.kernel.org,
	linux-phy@lists.infradead.org
Subject: Re: [PATCH v3 2/4] arm64: dts: qcom: qcs615: enable pcie
Date: Mon, 10 Mar 2025 09:38:16 +0100	[thread overview]
Message-ID: <20250310-neon-wealthy-sheep-2da4cd@krzk-bin> (raw)
In-Reply-To: <20250310065613.151598-3-quic_ziyuzhan@quicinc.com>

On Mon, Mar 10, 2025 at 02:56:11PM +0800, Ziyue Zhang wrote:
> From: Krishna chaitanya chundru <quic_krichai@quicinc.com>
> 
> Add configurations in devicetree for PCIe0, including registers, clocks,
> interrupts and phy setting sequence.
> 
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 142 +++++++++++++++++++++++++++
>  1 file changed, 142 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index f4abfad474ea..282072084435 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -1001,6 +1001,148 @@ mmss_noc: interconnect@1740000 {
>  			qcom,bcm-voters = <&apps_bcm_voter>;
>  		};
>  
> +	pcie: pcie@1c08000 {

Incorrect indentation (I am not going to look at anything else here).

Binding wasn't tested (you expect community to be the tools), this has
obvious style issue, so I really do not believe you performed internal
review.

Quality of patches recently coming from quicinc is really poor. That's
one more example. I raised it internally and it seems it reaches people
slow, so here you have a public nagging.

Do the internal review before you post.

Best regards,
Krzysztof


  reply	other threads:[~2025-03-10  8:38 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-10  6:56 [PATCH v3 0/4] pci: qcom: Add QCS615 PCIe support Ziyue Zhang
2025-03-10  6:56 ` [PATCH v3 1/4] dt-bindings: PCI: qcom: Document the QCS615 PCIe Controller Ziyue Zhang
2025-03-10  7:18   ` Krzysztof Kozlowski
2025-03-10  8:35     ` Krzysztof Kozlowski
2025-03-10  8:23   ` Rob Herring (Arm)
2025-03-10  6:56 ` [PATCH v3 2/4] arm64: dts: qcom: qcs615: enable pcie Ziyue Zhang
2025-03-10  8:38   ` Krzysztof Kozlowski [this message]
2025-03-11  9:48   ` Konrad Dybcio
2025-03-10  6:56 ` [PATCH v3 3/4] arm64: dts: qcom: qcs615-ride: Enable PCIe interface Ziyue Zhang
2025-03-11  9:06   ` kernel test robot
2025-03-10  6:56 ` [PATCH v3 4/4] PCI: qcom: Add support for QCS615 SoC Ziyue Zhang
2025-03-10 14:36 ` [PATCH v3 0/4] pci: qcom: Add QCS615 PCIe support Rob Herring (Arm)

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