[PATCH v3 0/3] Add AST2600 LPC PCC support

[PATCH v3 0/3] Add AST2600 LPC PCC support

[Kevin Chen]

--
v3
aspeed-lpc-pcc.c:
 -- Add ida_free and fix the dev usage with removing some debug messages.
aspeed-lpc.yaml:
 -- Add description about the pcc-ports usage.

v2:
 -- Change driver path to drivers/misc

Kevin Chen (3):
  dt-binding: aspeed: Add LPC PCC controller
  ARM: dts: aspeed-g6: Add AST2600 LPC PCC support
  soc: aspeed: lpc-pcc: Add PCC controller support

 .../devicetree/bindings/mfd/aspeed-lpc.yaml   |  38 ++
 arch/arm/boot/dts/aspeed/aspeed-g6.dtsi       |   7 +
 drivers/misc/Kconfig                          |  10 +
 drivers/misc/Makefile                         |   1 +
 drivers/misc/aspeed-lpc-pcc.c                 | 440 ++++++++++++++++++
 5 files changed, 496 insertions(+)
 create mode 100644 drivers/misc/aspeed-lpc-pcc.c

-- 
2.34.1

[PATCH v3 1/3] dt-binding: aspeed: Add LPC PCC controller

[Kevin Chen]

Add dt-bindings for Aspeed for Aspeed LPC POST code capture controller.

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 .../devicetree/bindings/mfd/aspeed-lpc.yaml   | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
index 5dfe77aca167..178c151a19ba 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
@@ -149,6 +149,37 @@ patternProperties:
       - interrupts
       - snoop-ports
 
+  "^lpc-pcc@[0-9a-f]+$":
+    type: object
+    additionalProperties: false
+
+    description:
+      The LPC pcc interface allows the BMC to listen on and record the data
+      bytes written by the Host to the targeted LPC I/O pots.
+
+    properties:
+      compatible:
+        items:
+          - enum:
+              - aspeed,ast2600-lpc-pcc
+
+      reg:
+        maxItems: 1
+
+      interrupts:
+        maxItems: 1
+
+      pcc-ports:
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        description:
+          As a device handshake with a host using the port-mmaped I/O in x86
+          architecture, need to handle specific which port I/O address for use.
+
+    required:
+      - compatible
+      - interrupts
+      - pcc-ports
+
   "^uart-routing@[0-9a-f]+$":
     $ref: /schemas/soc/aspeed/uart-routing.yaml#
     description: The UART routing control under LPC register space
@@ -176,6 +207,13 @@ examples:
         #size-cells = <1>;
         ranges = <0x0 0x1e789000 0x1000>;
 
+        lpc_pcc: lpc-pcc@0 {
+            compatible = "aspeed,ast2600-lpc-pcc";
+            reg = <0x0 0x140>;
+            interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+            pcc-ports = <0x80>;
+        };
+
         lpc_ctrl: lpc-ctrl@80 {
             compatible = "aspeed,ast2600-lpc-ctrl";
             reg = <0x80 0x80>;
-- 
2.34.1

Re: [PATCH v3 1/3] dt-binding: aspeed: Add LPC PCC controller

[Krzysztof Kozlowski]

On 10/03/2025 12:48, Kevin Chen wrote:
> Add dt-bindings for Aspeed for Aspeed LPC POST code capture controller.


<form letter>
This is a friendly reminder during the review process.

It seems my or other reviewer's previous comments were not fully
addressed. Maybe the feedback got lost between the quotes, maybe you
just forgot to apply it. Please go back to the previous discussion and
either implement all requested changes or keep discussing them.

Thank you.
</form letter>

> 
> Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
> ---
>  .../devicetree/bindings/mfd/aspeed-lpc.yaml   | 38 +++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> index 5dfe77aca167..178c151a19ba 100644
> --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> @@ -149,6 +149,37 @@ patternProperties:
>        - interrupts
>        - snoop-ports
>  
> +  "^lpc-pcc@[0-9a-f]+$":
> +    type: object
> +    additionalProperties: false
> +
> +    description:
> +      The LPC pcc interface allows the BMC to listen on and record the data
> +      bytes written by the Host to the targeted LPC I/O pots.
> +
> +    properties:
> +      compatible:
> +        items:
> +          - enum:
> +              - aspeed,ast2600-lpc-pcc
> +
> +      reg:
> +        maxItems: 1
> +
> +      interrupts:
> +        maxItems: 1
> +
> +      pcc-ports:
> +        $ref: /schemas/types.yaml#/definitions/uint32-array
> +        description:
> +          As a device handshake with a host using the port-mmaped I/O in x86
> +          architecture, need to handle specific which port I/O address for use.

<form letter>
This is a friendly reminder during the review process.

It seems my or other reviewer's previous comments were not fully
addressed. Maybe the feedback got lost between the quotes, maybe you
just forgot to apply it. Please go back to the previous discussion and
either implement all requested changes or keep discussing them.

Thank you.
</form letter>



Best regards,
Krzysztof

[PATCH v3 2/3] ARM: dts: aspeed-g6: Add AST2600 LPC PCC support

[Kevin Chen]

The AST2600 has PCC controller in LPC, placed in LPC node.

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
index 8ed715bd53aa..87dcacb78692 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
@@ -626,6 +626,13 @@ lpc_snoop: lpc-snoop@80 {
 					status = "disabled";
 				};
 
+				lpc_pcc: lpc-pcc@0 {
+					compatible = "aspeed,ast2600-lpc-pcc";
+					reg = <0x0 0x140>;
+					interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+					status = "disabled";
+				};
+
 				lhc: lhc@a0 {
 					compatible = "aspeed,ast2600-lhc";
 					reg = <0xa0 0x24 0xc8 0x8>;
-- 
2.34.1

[PATCH v3 3/3] soc: aspeed: lpc-pcc: Add PCC controller support

[Kevin Chen]

Add LPC PCC controller driver to support POST code capture.

Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
 drivers/misc/Kconfig          |  10 +
 drivers/misc/Makefile         |   1 +
 drivers/misc/aspeed-lpc-pcc.c | 440 ++++++++++++++++++++++++++++++++++
 3 files changed, 451 insertions(+)
 create mode 100644 drivers/misc/aspeed-lpc-pcc.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 56bc72c7ce4a..35c1d2e0c271 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -50,6 +50,16 @@ config AD525X_DPOT_SPI
 	  To compile this driver as a module, choose M here: the
 	  module will be called ad525x_dpot-spi.
 
+config ASPEED_LPC_PCC
+	tristate "Aspeed Post Code Capture support"
+	select REGMAP
+	select MFD_SYSCON
+	default ARCH_ASPEED
+	help
+	  Provides a driver to control the LPC PCC interface,
+	  allowing the BMC to capture post code written by the
+	  the host to an arbitrary LPC I/O port.
+
 config DUMMY_IRQ
 	tristate "Dummy IRQ handler"
 	help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 545aad06d088..4762da7804bf 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_IBMVMC)		+= ibmvmc.o
 obj-$(CONFIG_AD525X_DPOT)	+= ad525x_dpot.o
 obj-$(CONFIG_AD525X_DPOT_I2C)	+= ad525x_dpot-i2c.o
 obj-$(CONFIG_AD525X_DPOT_SPI)	+= ad525x_dpot-spi.o
+obj-$(CONFIG_ASPEED_LPC_PCC)	+= aspeed-lpc-pcc.o
 obj-$(CONFIG_ATMEL_SSC)		+= atmel-ssc.o
 obj-$(CONFIG_DUMMY_IRQ)		+= dummy-irq.o
 obj-$(CONFIG_ICS932S401)	+= ics932s401.o
diff --git a/drivers/misc/aspeed-lpc-pcc.c b/drivers/misc/aspeed-lpc-pcc.c
new file mode 100644
index 000000000000..9ed4b453d199
--- /dev/null
+++ b/drivers/misc/aspeed-lpc-pcc.c
@@ -0,0 +1,440 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+#include <linux/interrupt.h>
+#include <linux/fs.h>
+#include <linux/kfifo.h>
+#include <linux/mfd/syscon.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/poll.h>
+#include <linux/regmap.h>
+#include <linux/dma-mapping.h>
+#include <linux/sizes.h>
+
+#define DEVICE_NAME "aspeed-lpc-pcc"
+
+static DEFINE_IDA(aspeed_pcc_ida);
+
+#define HICR5	0x80
+#define HICR5_EN_SNP0W			BIT(0)
+#define HICR5_EN_SNP1W			BIT(2)
+#define HICR6	0x084
+#define   HICR6_EN2BMODE		BIT(19)
+#define SNPWADR	0x090
+#define PCCR6	0x0c4
+#define   PCCR6_DMA_CUR_ADDR		GENMASK(27, 0)
+#define PCCR4	0x0d0
+#define   PCCR4_DMA_ADDRL_MASK		GENMASK(31, 0)
+#define   PCCR4_DMA_ADDRL_SHIFT		0
+#define PCCR5	0x0d4
+#define   PCCR5_DMA_ADDRH_MASK		GENMASK(27, 24)
+#define   PCCR5_DMA_ADDRH_SHIFT		24
+#define   PCCR5_DMA_LEN_MASK		GENMASK(23, 0)
+#define   PCCR5_DMA_LEN_SHIFT		0
+#define HICRB	0x100
+#define   HICRB_ENSNP0D			BIT(14)
+#define   HICRB_ENSNP1D			BIT(15)
+#define PCCR0	0x130
+#define   PCCR0_EN_DMA_INT		BIT(31)
+#define   PCCR0_EN_DMA_MODE		BIT(14)
+#define   PCCR0_ADDR_SEL_MASK		GENMASK(13, 12)
+#define   PCCR0_ADDR_SEL_SHIFT		12
+#define   PCCR0_RX_TRIG_LVL_MASK	GENMASK(10, 8)
+#define   PCCR0_RX_TRIG_LVL_SHIFT	8
+#define   PCCR0_CLR_RX_FIFO		BIT(7)
+#define   PCCR0_MODE_SEL_MASK		GENMASK(5, 4)
+#define   PCCR0_MODE_SEL_SHIFT		4
+#define   PCCR0_EN_RX_TMOUT_INT		BIT(2)
+#define   PCCR0_EN_RX_AVAIL_INT		BIT(1)
+#define   PCCR0_EN			BIT(0)
+#define PCCR1	0x134
+#define   PCCR1_BASE_ADDR_MASK		GENMASK(15, 0)
+#define   PCCR1_BASE_ADDR_SHIFT		0
+#define   PCCR1_DONT_CARE_BITS_MASK	GENMASK(21, 16)
+#define   PCCR1_DONT_CARE_BITS_SHIFT	16
+#define PCCR2	0x138
+#define   PCCR2_INT_STATUS_PATTERN_B	BIT(16)
+#define   PCCR2_INT_STATUS_PATTERN_A	BIT(8)
+#define   PCCR2_INT_STATUS_DMA_DONE	BIT(4)
+#define   PCCR2_INT_STATUS_DATA_RDY	PCCR2_INT_STATUS_DMA_DONE
+#define   PCCR2_INT_STATUS_RX_OVER	BIT(3)
+#define   PCCR2_INT_STATUS_RX_TMOUT	BIT(2)
+#define   PCCR2_INT_STATUS_RX_AVAIL	BIT(1)
+#define PCCR3	0x13c
+#define   PCCR3_FIFO_DATA_MASK		GENMASK(7, 0)
+
+#define PCC_DMA_BUFSZ	(256 * SZ_1K)
+
+enum pcc_fifo_threshold {
+	PCC_FIFO_THR_1_BYTE,
+	PCC_FIFO_THR_1_EIGHTH,
+	PCC_FIFO_THR_2_EIGHTH,
+	PCC_FIFO_THR_3_EIGHTH,
+	PCC_FIFO_THR_4_EIGHTH,
+	PCC_FIFO_THR_5_EIGHTH,
+	PCC_FIFO_THR_6_EIGHTH,
+	PCC_FIFO_THR_7_EIGHTH,
+	PCC_FIFO_THR_8_EIGHTH,
+};
+
+enum pcc_record_mode {
+	PCC_REC_1B,
+	PCC_REC_2B,
+	PCC_REC_4B,
+	PCC_REC_FULL,
+};
+
+enum pcc_port_hbits_select {
+	PCC_PORT_HBITS_SEL_NONE,
+	PCC_PORT_HBITS_SEL_45,
+	PCC_PORT_HBITS_SEL_67,
+	PCC_PORT_HBITS_SEL_89,
+};
+
+struct aspeed_pcc_dma {
+	uint32_t rptr;
+	uint8_t *virt;
+	dma_addr_t addr;
+	uint32_t size;
+};
+
+struct aspeed_pcc_ctrl {
+	struct device *dev;
+	struct regmap *regmap;
+	int irq;
+	uint32_t port;
+	struct aspeed_pcc_dma dma;
+	struct kfifo fifo;
+	wait_queue_head_t wq;
+	struct miscdevice mdev;
+	int mdev_id;
+};
+
+static inline bool is_valid_rec_mode(uint32_t mode)
+{
+	return (mode > PCC_REC_FULL) ? false : true;
+}
+
+static inline bool is_valid_high_bits_select(uint32_t sel)
+{
+	return (sel > PCC_PORT_HBITS_SEL_89) ? false : true;
+}
+
+static ssize_t aspeed_pcc_file_read(struct file *file, char __user *buffer,
+				    size_t count, loff_t *ppos)
+{
+	int rc;
+	unsigned int copied;
+	struct aspeed_pcc_ctrl *pcc = container_of(file->private_data,
+					      struct aspeed_pcc_ctrl,
+					      mdev);
+
+	if (kfifo_is_empty(&pcc->fifo)) {
+		if (file->f_flags & O_NONBLOCK)
+			return -EAGAIN;
+
+		rc = wait_event_interruptible(pcc->wq,
+					      !kfifo_is_empty(&pcc->fifo));
+		if (rc == -ERESTARTSYS)
+			return -EINTR;
+	}
+
+	rc = kfifo_to_user(&pcc->fifo, buffer, count, &copied);
+
+	return rc ? rc : copied;
+}
+
+static __poll_t aspeed_pcc_file_poll(struct file *file,
+				     struct poll_table_struct *pt)
+{
+	struct aspeed_pcc_ctrl *pcc = container_of(file->private_data,
+					      struct aspeed_pcc_ctrl,
+					      mdev);
+
+	poll_wait(file, &pcc->wq, pt);
+
+	return !kfifo_is_empty(&pcc->fifo) ? POLLIN : 0;
+}
+
+static const struct file_operations pcc_fops = {
+	.owner = THIS_MODULE,
+	.read = aspeed_pcc_file_read,
+	.poll = aspeed_pcc_file_poll,
+};
+
+static irqreturn_t aspeed_pcc_dma_isr(int irq, void *arg)
+{
+	uint32_t reg, rptr, wptr;
+	struct aspeed_pcc_ctrl *pcc = (struct aspeed_pcc_ctrl *)arg;
+	struct kfifo *fifo = &pcc->fifo;
+
+	regmap_write_bits(pcc->regmap, PCCR2, PCCR2_INT_STATUS_DMA_DONE, PCCR2_INT_STATUS_DMA_DONE);
+
+	regmap_read(pcc->regmap, PCCR6, &reg);
+	wptr = (reg & PCCR6_DMA_CUR_ADDR) - (pcc->dma.addr & PCCR6_DMA_CUR_ADDR);
+	rptr = pcc->dma.rptr;
+
+	do {
+		if (kfifo_is_full(fifo))
+			kfifo_skip(fifo);
+
+		kfifo_put(fifo, pcc->dma.virt[rptr]);
+
+		rptr = (rptr + 1) % pcc->dma.size;
+	} while (rptr != wptr);
+
+	pcc->dma.rptr = rptr;
+
+	wake_up_interruptible(&pcc->wq);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t aspeed_pcc_isr(int irq, void *arg)
+{
+	uint32_t sts;
+	struct aspeed_pcc_ctrl *pcc = (struct aspeed_pcc_ctrl *)arg;
+
+	regmap_read(pcc->regmap, PCCR2, &sts);
+
+	if (!(sts & (PCCR2_INT_STATUS_RX_TMOUT |
+		     PCCR2_INT_STATUS_RX_AVAIL |
+		     PCCR2_INT_STATUS_DMA_DONE)))
+		return IRQ_NONE;
+
+	return aspeed_pcc_dma_isr(irq, arg);
+}
+
+/*
+ * A2600-15 AP note
+ *
+ * SW workaround to prevent generating Non-Fatal-Error (NFE)
+ * eSPI response when PCC is used for port I/O byte snooping
+ * over eSPI.
+ */
+static int aspeed_a2600_15(struct aspeed_pcc_ctrl *pcc, struct device *dev)
+{
+	u32 hicr5_en, hicrb_en;
+
+	/* abort if snoop is enabled */
+	regmap_read(pcc->regmap, HICR5, &hicr5_en);
+	if (hicr5_en & (HICR5_EN_SNP0W | HICR5_EN_SNP1W)) {
+		dev_err(dev, "A2600-15 should be applied with snoop disabled\n");
+		return -EPERM;
+	}
+
+	/* set SNPWADR of snoop device */
+	regmap_write(pcc->regmap, SNPWADR, pcc->port | ((pcc->port + 2) << 16));
+
+	/* set HICRB[15:14]=11b to enable ACCEPT response for SNPWADR */
+	hicrb_en = HICRB_ENSNP0D | HICRB_ENSNP1D;
+	regmap_update_bits(pcc->regmap, HICRB, hicrb_en, hicrb_en);
+
+	/* set HICR6[19] to extend SNPWADR to 2x range */
+	regmap_update_bits(pcc->regmap, HICR6, HICR6_EN2BMODE, HICR6_EN2BMODE);
+
+	return 0;
+}
+
+static int aspeed_pcc_enable(struct aspeed_pcc_ctrl *pcc, struct device *dev)
+{
+	int rc;
+
+	rc = aspeed_a2600_15(pcc, dev);
+	if (rc)
+		return rc;
+
+	/* record mode: Set 2-Byte mode. */
+	regmap_update_bits(pcc->regmap, PCCR0,
+			   PCCR0_MODE_SEL_MASK,
+			   PCC_REC_2B << PCCR0_MODE_SEL_SHIFT);
+
+	/* port address */
+	regmap_update_bits(pcc->regmap, PCCR1,
+			   PCCR1_BASE_ADDR_MASK,
+			   pcc->port << PCCR1_BASE_ADDR_SHIFT);
+
+	/* Set address high bits selection to 0b01 for address bit[5:4] */
+	regmap_update_bits(pcc->regmap, PCCR0,
+			   PCCR0_ADDR_SEL_MASK,
+			   PCC_PORT_HBITS_SEL_45 << PCCR0_ADDR_SEL_SHIFT);
+
+	/* Set LPC don't care address to 0x3 for port 80~83h */
+	regmap_update_bits(pcc->regmap, PCCR1,
+			   PCCR1_DONT_CARE_BITS_MASK,
+			   0x3 << PCCR1_DONT_CARE_BITS_SHIFT);
+
+	/* set DMA ring buffer size and enable interrupts */
+	regmap_write(pcc->regmap, PCCR4, pcc->dma.addr & 0xffffffff);
+#ifdef CONFIG_ARM64
+	regmap_update_bits(pcc->regmap, PCCR5, PCCR5_DMA_ADDRH_MASK,
+			   (pcc->dma.addr >> 32) << PCCR5_DMA_ADDRH_SHIFT);
+#endif
+	regmap_update_bits(pcc->regmap, PCCR5, PCCR5_DMA_LEN_MASK,
+			   (pcc->dma.size / 4) << PCCR5_DMA_LEN_SHIFT);
+	regmap_update_bits(pcc->regmap, PCCR0,
+			   PCCR0_EN_DMA_INT | PCCR0_EN_DMA_MODE,
+			   PCCR0_EN_DMA_INT | PCCR0_EN_DMA_MODE);
+
+	regmap_update_bits(pcc->regmap, PCCR0, PCCR0_EN, PCCR0_EN);
+
+	return 0;
+}
+
+static int aspeed_pcc_disable(struct aspeed_pcc_ctrl *pcc)
+{
+	/* Disable PCC and DMA Mode for safety */
+	regmap_update_bits(pcc->regmap, PCCR0, PCCR0_EN |  PCCR0_EN_DMA_MODE, 0);
+
+	/* Clear Rx FIFO. */
+	regmap_update_bits(pcc->regmap, PCCR0, PCCR0_CLR_RX_FIFO, 1);
+
+	/* Clear All interrupts status. */
+	regmap_write(pcc->regmap, PCCR2,
+		     PCCR2_INT_STATUS_RX_OVER | PCCR2_INT_STATUS_DMA_DONE |
+		     PCCR2_INT_STATUS_PATTERN_A | PCCR2_INT_STATUS_PATTERN_B);
+
+	return 0;
+}
+
+static int aspeed_pcc_probe(struct platform_device *pdev)
+{
+	int rc;
+	struct aspeed_pcc_ctrl *pcc;
+	struct device *dev = &pdev->dev;
+	uint32_t fifo_size = PAGE_SIZE;
+
+	pcc = devm_kzalloc(dev, sizeof(*pcc), GFP_KERNEL);
+	if (!pcc)
+		return -ENOMEM;
+
+	pcc->regmap = syscon_node_to_regmap(dev->parent->of_node);
+	if (IS_ERR(pcc->regmap)) {
+		dev_err(dev, "Couldn't get regmap\n");
+		return -ENODEV;
+	}
+
+	rc = of_property_read_u32(dev->of_node, "pcc-ports", &pcc->port);
+	if (rc) {
+		dev_err(dev, "no pcc ports configured\n");
+		return -ENODEV;
+	}
+
+	rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
+	if (rc) {
+		dev_err(dev, "cannot set 64-bits DMA mask\n");
+		return rc;
+	}
+
+	pcc->dma.size = PCC_DMA_BUFSZ;
+	pcc->dma.virt = dmam_alloc_coherent(dev,
+					    pcc->dma.size,
+					    &pcc->dma.addr,
+					    GFP_KERNEL);
+	if (!pcc->dma.virt) {
+		dev_err(dev, "cannot allocate DMA buffer\n");
+		return -ENOMEM;
+	}
+
+	fifo_size = roundup(pcc->dma.size, PAGE_SIZE);
+	rc = kfifo_alloc(&pcc->fifo, fifo_size, GFP_KERNEL);
+	if (rc) {
+		return -ENOMEM;
+	}
+
+	/* Disable PCC to clean up DMA buffer before request IRQ. */
+	rc = aspeed_pcc_disable(pcc);
+	if (rc) {
+		dev_err(dev, "Couldn't disable PCC\n");
+		goto err_free_kfifo;
+	}
+
+	pcc->irq = platform_get_irq(pdev, 0);
+	if (pcc->irq < 0) {
+		rc = pcc->irq;
+		goto err_free_kfifo;
+	}
+
+	rc = devm_request_irq(dev, pcc->irq, aspeed_pcc_isr, 0, DEVICE_NAME, pcc);
+	if (rc < 0) {
+		dev_err(dev, "Couldn't request IRQ %d\n", pcc->irq);
+		goto err_free_kfifo;
+	}
+
+	init_waitqueue_head(&pcc->wq);
+
+	pcc->mdev_id = ida_alloc(&aspeed_pcc_ida, GFP_KERNEL);
+	if (pcc->mdev_id < 0) {
+		dev_err(dev, "Couldn't allocate ID\n");
+		goto err_free_kfifo;
+	}
+
+	pcc->mdev.parent = dev;
+	pcc->mdev.minor = MISC_DYNAMIC_MINOR;
+	pcc->mdev.name = devm_kasprintf(dev, GFP_KERNEL, "%s%d", DEVICE_NAME,
+					pcc->mdev_id);
+	pcc->mdev.fops = &pcc_fops;
+	rc = misc_register(&pcc->mdev);
+	if (rc) {
+		dev_err(dev, "Couldn't register misc device\n");
+		goto err_free_ida;
+	}
+
+	rc = aspeed_pcc_enable(pcc, dev);
+	if (rc) {
+		dev_err(dev, "Couldn't enable PCC\n");
+		goto err_dereg_mdev;
+	}
+
+	dev_set_drvdata(dev, pcc);
+
+	return 0;
+
+err_dereg_mdev:
+	misc_deregister(&pcc->mdev);
+
+err_free_ida:
+	ida_free(&aspeed_pcc_ida, pcc->mdev_id);
+
+err_free_kfifo:
+	kfifo_free(&pcc->fifo);
+
+	return rc;
+}
+
+static void aspeed_pcc_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct aspeed_pcc_ctrl *pcc = dev_get_drvdata(dev);
+
+	kfifo_free(&pcc->fifo);
+	ida_free(&aspeed_pcc_ida, pcc->mdev_id);
+	misc_deregister(&pcc->mdev);
+}
+
+static const struct of_device_id aspeed_pcc_table[] = {
+	{ .compatible = "aspeed,ast2600-lpc-pcc" },
+};
+
+static struct platform_driver aspeed_pcc_driver = {
+	.driver = {
+		.name = "aspeed-pcc",
+		.of_match_table = aspeed_pcc_table,
+	},
+	.probe = aspeed_pcc_probe,
+	.remove = aspeed_pcc_remove,
+};
+
+module_platform_driver(aspeed_pcc_driver);
+
+MODULE_AUTHOR("Chia-Wei Wang <chiawei_wang@aspeedtech.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Driver for Aspeed Post Code Capture");
-- 
2.34.1

Re: [PATCH v3 3/3] soc: aspeed: lpc-pcc: Add PCC controller support

[Krzysztof Kozlowski]

On 10/03/2025 12:48, Kevin Chen wrote:
> +static int aspeed_pcc_probe(struct platform_device *pdev)
> +{
> +	int rc;
> +	struct aspeed_pcc_ctrl *pcc;
> +	struct device *dev = &pdev->dev;
> +	uint32_t fifo_size = PAGE_SIZE;
> +
> +	pcc = devm_kzalloc(dev, sizeof(*pcc), GFP_KERNEL);
> +	if (!pcc)
> +		return -ENOMEM;
> +
> +	pcc->regmap = syscon_node_to_regmap(dev->parent->of_node);
> +	if (IS_ERR(pcc->regmap)) {
> +		dev_err(dev, "Couldn't get regmap\n");

return dev_err_probe() is not suitable?

> +		return -ENODEV;

Why overriding error code?

> +	}
> +
> +	rc = of_property_read_u32(dev->of_node, "pcc-ports", &pcc->port);
> +	if (rc) {
> +		dev_err(dev, "no pcc ports configured\n");
> +		return -ENODEV;

Why overriding error code?

You got this comment already at v2.

> +	}
> +
> +	rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
> +	if (rc) {
> +		dev_err(dev, "cannot set 64-bits DMA mask\n");
> +		return rc;
> +	}
> +
> +	pcc->dma.size = PCC_DMA_BUFSZ;
> +	pcc->dma.virt = dmam_alloc_coherent(dev,
> +					    pcc->dma.size,
> +					    &pcc->dma.addr,
> +					    GFP_KERNEL);
> +	if (!pcc->dma.virt) {
> +		dev_err(dev, "cannot allocate DMA buffer\n");
> +		return -ENOMEM;
> +	}
> +
> +	fifo_size = roundup(pcc->dma.size, PAGE_SIZE);
> +	rc = kfifo_alloc(&pcc->fifo, fifo_size, GFP_KERNEL);
> +	if (rc) {

Drop {}

> +		return -ENOMEM;
> +	}
> +

Please run scripts/checkpatch.pl and fix reported warnings. After that,
run also `scripts/checkpatch.pl --strict` and (probably) fix more
warnings. Some warnings can be ignored, especially from --strict run,
but the code here looks like it needs a fix. Feel free to get in touch
if the warning is not clear.



Best regards,
Krzysztof

RE: [PATCH v3 3/3] soc: aspeed: lpc-pcc: Add PCC controller support

[Kevin Chen]

> On 10/03/2025 12:48, Kevin Chen wrote:
> > +static int aspeed_pcc_probe(struct platform_device *pdev) {
> > +	int rc;
> > +	struct aspeed_pcc_ctrl *pcc;
> > +	struct device *dev = &pdev->dev;
> > +	uint32_t fifo_size = PAGE_SIZE;
> > +
> > +	pcc = devm_kzalloc(dev, sizeof(*pcc), GFP_KERNEL);
> > +	if (!pcc)
> > +		return -ENOMEM;
> > +
> > +	pcc->regmap = syscon_node_to_regmap(dev->parent->of_node);
> > +	if (IS_ERR(pcc->regmap)) {
> > +		dev_err(dev, "Couldn't get regmap\n");
> 
> return dev_err_probe() is not suitable?
Agree. Change to " dev_err_probe(dev, PTR_ERR(pcc->regmap),"Couldn't get regmap\n");"?

> 
> > +		return -ENODEV;
> 
> Why overriding error code?

> 
> > +	}
> > +
> > +	rc = of_property_read_u32(dev->of_node, "pcc-ports", &pcc->port);
> > +	if (rc) {
> > +		dev_err(dev, "no pcc ports configured\n");
> > +		return -ENODEV;
> 
> Why overriding error code?
Agree.

> 
> You got this comment already at v2.
Sorry, I already checked the comment in v2.

> 
> > +	}
> > +
> > +	rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
> > +	if (rc) {
> > +		dev_err(dev, "cannot set 64-bits DMA mask\n");
> > +		return rc;
> > +	}
> > +
> > +	pcc->dma.size = PCC_DMA_BUFSZ;
> > +	pcc->dma.virt = dmam_alloc_coherent(dev,
> > +					    pcc->dma.size,
> > +					    &pcc->dma.addr,
> > +					    GFP_KERNEL);
> > +	if (!pcc->dma.virt) {
> > +		dev_err(dev, "cannot allocate DMA buffer\n");
> > +		return -ENOMEM;
> > +	}
> > +
> > +	fifo_size = roundup(pcc->dma.size, PAGE_SIZE);
> > +	rc = kfifo_alloc(&pcc->fifo, fifo_size, GFP_KERNEL);
> > +	if (rc) {
> 
> Drop {}
Agree.
> 
> > +		return -ENOMEM;
> > +	}
> > +
> 
> Please run scripts/checkpatch.pl and fix reported warnings. After that, run also
> `scripts/checkpatch.pl --strict` and (probably) fix more warnings. Some
> warnings can be ignored, especially from --strict run, but the code here looks
> like it needs a fix. Feel free to get in touch if the warning is not clear.
Agree.

> 
> 
> 
> Best regards,
> Krzysztof

Re: [PATCH v3 3/3] soc: aspeed: lpc-pcc: Add PCC controller support

[kernel test robot]

Hi Kevin,

kernel test robot noticed the following build errors:

[auto build test ERROR on char-misc/char-misc-testing]
[also build test ERROR on char-misc/char-misc-next char-misc/char-misc-linus lee-leds/for-leds-next lee-mfd/for-mfd-next robh/for-next lee-mfd/for-mfd-fixes linus/master v6.14-rc6 next-20250314]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Kevin-Chen/dt-binding-aspeed-Add-LPC-PCC-controller/20250310-195011
base:   char-misc/char-misc-testing
patch link:    https://lore.kernel.org/r/20250310114839.3098148-4-kevin_chen%40aspeedtech.com
patch subject: [PATCH v3 3/3] soc: aspeed: lpc-pcc: Add PCC controller support
config: s390-randconfig-002-20250316 (https://download.01.org/0day-ci/archive/20250316/202503160530.EkUNSrkh-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250316/202503160530.EkUNSrkh-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503160530.EkUNSrkh-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/mfd/syscon.c:157:2: error: call to undeclared function 'iounmap'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           iounmap(base);
           ^
   arch/s390/include/asm/io.h:31:17: note: expanded from macro 'iounmap'
   #define iounmap iounmap
                   ^
   1 error generated.

Kconfig warnings: (for reference only)
   WARNING: unmet direct dependencies detected for MFD_SYSCON
   Depends on [n]: HAS_IOMEM [=n]
   Selected by [y]:
   - ASPEED_LPC_PCC [=y]


vim +/iounmap +157 drivers/mfd/syscon.c

87d687301f38072 Dong Aisheng        2012-09-05   39  
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05   40  static struct syscon *of_syscon_register(struct device_node *np, bool check_res)
87d687301f38072 Dong Aisheng        2012-09-05   41  {
a00406b71c5f08f Fabrice Gasnier     2018-12-12   42  	struct clk *clk;
bdb0066df96e74a Pankaj Dubey        2014-09-30   43  	struct regmap *regmap;
bdb0066df96e74a Pankaj Dubey        2014-09-30   44  	void __iomem *base;
db2fb60cd35d2d0 Damien Riegel       2015-11-30   45  	u32 reg_io_width;
bdb0066df96e74a Pankaj Dubey        2014-09-30   46  	int ret;
bdb0066df96e74a Pankaj Dubey        2014-09-30   47  	struct regmap_config syscon_config = syscon_regmap_config;
ca668f0edfae654 Philipp Zabel       2016-01-29   48  	struct resource res;
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05   49  	struct reset_control *reset;
bdb0066df96e74a Pankaj Dubey        2014-09-30   50  
805f7aaf7fee14a Rob Herring (Arm    2024-12-17   51) 	WARN_ON(!mutex_is_locked(&syscon_list_lock));
805f7aaf7fee14a Rob Herring (Arm    2024-12-17   52) 
82f898f47112bc7 Krzysztof Kozlowski 2024-07-07   53  	struct syscon *syscon __free(kfree) = kzalloc(sizeof(*syscon), GFP_KERNEL);
bdb0066df96e74a Pankaj Dubey        2014-09-30   54  	if (!syscon)
bdb0066df96e74a Pankaj Dubey        2014-09-30   55  		return ERR_PTR(-ENOMEM);
bdb0066df96e74a Pankaj Dubey        2014-09-30   56  
82f898f47112bc7 Krzysztof Kozlowski 2024-07-07   57  	if (of_address_to_resource(np, 0, &res))
82f898f47112bc7 Krzysztof Kozlowski 2024-07-07   58  		return ERR_PTR(-ENOMEM);
ca668f0edfae654 Philipp Zabel       2016-01-29   59  
452d07413954ef3 Hector Martin       2021-08-23   60  	base = of_iomap(np, 0);
82f898f47112bc7 Krzysztof Kozlowski 2024-07-07   61  	if (!base)
82f898f47112bc7 Krzysztof Kozlowski 2024-07-07   62  		return ERR_PTR(-ENOMEM);
bdb0066df96e74a Pankaj Dubey        2014-09-30   63  
ca4582c286aa446 Jason A. Donenfeld  2022-10-08   64  	/* Parse the device's DT node for an endianness specification */
ca4582c286aa446 Jason A. Donenfeld  2022-10-08   65  	if (of_property_read_bool(np, "big-endian"))
ca4582c286aa446 Jason A. Donenfeld  2022-10-08   66  		syscon_config.val_format_endian = REGMAP_ENDIAN_BIG;
ca4582c286aa446 Jason A. Donenfeld  2022-10-08   67  	else if (of_property_read_bool(np, "little-endian"))
ca4582c286aa446 Jason A. Donenfeld  2022-10-08   68  		syscon_config.val_format_endian = REGMAP_ENDIAN_LITTLE;
ca4582c286aa446 Jason A. Donenfeld  2022-10-08   69  	else if (of_property_read_bool(np, "native-endian"))
ca4582c286aa446 Jason A. Donenfeld  2022-10-08   70  		syscon_config.val_format_endian = REGMAP_ENDIAN_NATIVE;
ca4582c286aa446 Jason A. Donenfeld  2022-10-08   71  
db2fb60cd35d2d0 Damien Riegel       2015-11-30   72  	/*
db2fb60cd35d2d0 Damien Riegel       2015-11-30   73  	 * search for reg-io-width property in DT. If it is not provided,
db2fb60cd35d2d0 Damien Riegel       2015-11-30   74  	 * default to 4 bytes. regmap_init_mmio will return an error if values
db2fb60cd35d2d0 Damien Riegel       2015-11-30   75  	 * are invalid so there is no need to check them here.
db2fb60cd35d2d0 Damien Riegel       2015-11-30   76  	 */
db2fb60cd35d2d0 Damien Riegel       2015-11-30   77  	ret = of_property_read_u32(np, "reg-io-width", &reg_io_width);
db2fb60cd35d2d0 Damien Riegel       2015-11-30   78  	if (ret)
db2fb60cd35d2d0 Damien Riegel       2015-11-30   79  		reg_io_width = 4;
db2fb60cd35d2d0 Damien Riegel       2015-11-30   80  
3bafc09e779710a Baolin Wang         2017-12-25   81  	ret = of_hwspin_lock_get_id(np, 0);
3bafc09e779710a Baolin Wang         2017-12-25   82  	if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
3bafc09e779710a Baolin Wang         2017-12-25   83  		syscon_config.use_hwlock = true;
3bafc09e779710a Baolin Wang         2017-12-25   84  		syscon_config.hwlock_id = ret;
3bafc09e779710a Baolin Wang         2017-12-25   85  		syscon_config.hwlock_mode = HWLOCK_IRQSTATE;
3bafc09e779710a Baolin Wang         2017-12-25   86  	} else if (ret < 0) {
3bafc09e779710a Baolin Wang         2017-12-25   87  		switch (ret) {
3bafc09e779710a Baolin Wang         2017-12-25   88  		case -ENOENT:
3bafc09e779710a Baolin Wang         2017-12-25   89  			/* Ignore missing hwlock, it's optional. */
3bafc09e779710a Baolin Wang         2017-12-25   90  			break;
3bafc09e779710a Baolin Wang         2017-12-25   91  		default:
3bafc09e779710a Baolin Wang         2017-12-25   92  			pr_err("Failed to retrieve valid hwlock: %d\n", ret);
df561f6688fef77 Gustavo A. R. Silva 2020-08-23   93  			fallthrough;
3bafc09e779710a Baolin Wang         2017-12-25   94  		case -EPROBE_DEFER:
3bafc09e779710a Baolin Wang         2017-12-25   95  			goto err_regmap;
3bafc09e779710a Baolin Wang         2017-12-25   96  		}
3bafc09e779710a Baolin Wang         2017-12-25   97  	}
3bafc09e779710a Baolin Wang         2017-12-25   98  
7ff7d5ffb7259f7 Andy Shevchenko     2022-05-31   99  	syscon_config.name = kasprintf(GFP_KERNEL, "%pOFn@%pa", np, &res.start);
41673c66b3d0c09 Kunwu Chan          2023-12-04  100  	if (!syscon_config.name) {
41673c66b3d0c09 Kunwu Chan          2023-12-04  101  		ret = -ENOMEM;
41673c66b3d0c09 Kunwu Chan          2023-12-04  102  		goto err_regmap;
41673c66b3d0c09 Kunwu Chan          2023-12-04  103  	}
db2fb60cd35d2d0 Damien Riegel       2015-11-30  104  	syscon_config.reg_stride = reg_io_width;
db2fb60cd35d2d0 Damien Riegel       2015-11-30  105  	syscon_config.val_bits = reg_io_width * 8;
ca668f0edfae654 Philipp Zabel       2016-01-29  106  	syscon_config.max_register = resource_size(&res) - reg_io_width;
2e63d6fa113d362 Nishanth Menon      2024-09-03  107  	if (!syscon_config.max_register)
2e63d6fa113d362 Nishanth Menon      2024-09-03  108  		syscon_config.max_register_is_0 = true;
db2fb60cd35d2d0 Damien Riegel       2015-11-30  109  
bdb0066df96e74a Pankaj Dubey        2014-09-30  110  	regmap = regmap_init_mmio(NULL, base, &syscon_config);
56a1188159cb2b8 Limeng              2021-04-07  111  	kfree(syscon_config.name);
bdb0066df96e74a Pankaj Dubey        2014-09-30  112  	if (IS_ERR(regmap)) {
bdb0066df96e74a Pankaj Dubey        2014-09-30  113  		pr_err("regmap init failed\n");
bdb0066df96e74a Pankaj Dubey        2014-09-30  114  		ret = PTR_ERR(regmap);
bdb0066df96e74a Pankaj Dubey        2014-09-30  115  		goto err_regmap;
bdb0066df96e74a Pankaj Dubey        2014-09-30  116  	}
bdb0066df96e74a Pankaj Dubey        2014-09-30  117  
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  118  	if (check_res) {
a00406b71c5f08f Fabrice Gasnier     2018-12-12  119  		clk = of_clk_get(np, 0);
a00406b71c5f08f Fabrice Gasnier     2018-12-12  120  		if (IS_ERR(clk)) {
a00406b71c5f08f Fabrice Gasnier     2018-12-12  121  			ret = PTR_ERR(clk);
a00406b71c5f08f Fabrice Gasnier     2018-12-12  122  			/* clock is optional */
a00406b71c5f08f Fabrice Gasnier     2018-12-12  123  			if (ret != -ENOENT)
a00406b71c5f08f Fabrice Gasnier     2018-12-12  124  				goto err_clk;
a00406b71c5f08f Fabrice Gasnier     2018-12-12  125  		} else {
a00406b71c5f08f Fabrice Gasnier     2018-12-12  126  			ret = regmap_mmio_attach_clk(regmap, clk);
a00406b71c5f08f Fabrice Gasnier     2018-12-12  127  			if (ret)
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  128  				goto err_attach_clk;
a00406b71c5f08f Fabrice Gasnier     2018-12-12  129  		}
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  130  
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  131  		reset = of_reset_control_get_optional_exclusive(np, NULL);
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  132  		if (IS_ERR(reset)) {
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  133  			ret = PTR_ERR(reset);
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  134  			goto err_attach_clk;
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  135  		}
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  136  
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  137  		ret = reset_control_deassert(reset);
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  138  		if (ret)
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  139  			goto err_reset;
39233b7c611248c Paul Cercueil       2019-07-24  140  	}
a00406b71c5f08f Fabrice Gasnier     2018-12-12  141  
bdb0066df96e74a Pankaj Dubey        2014-09-30  142  	syscon->regmap = regmap;
bdb0066df96e74a Pankaj Dubey        2014-09-30  143  	syscon->np = np;
bdb0066df96e74a Pankaj Dubey        2014-09-30  144  
bdb0066df96e74a Pankaj Dubey        2014-09-30  145  	list_add_tail(&syscon->list, &syscon_list);
87d687301f38072 Dong Aisheng        2012-09-05  146  
82f898f47112bc7 Krzysztof Kozlowski 2024-07-07  147  	return_ptr(syscon);
bdb0066df96e74a Pankaj Dubey        2014-09-30  148  
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  149  err_reset:
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  150  	reset_control_put(reset);
7d1e3bd94828ad9 Jeremy Kerr         2023-01-05  151  err_attach_clk:
a00406b71c5f08f Fabrice Gasnier     2018-12-12  152  	if (!IS_ERR(clk))
a00406b71c5f08f Fabrice Gasnier     2018-12-12  153  		clk_put(clk);
a00406b71c5f08f Fabrice Gasnier     2018-12-12  154  err_clk:
a00406b71c5f08f Fabrice Gasnier     2018-12-12  155  	regmap_exit(regmap);
bdb0066df96e74a Pankaj Dubey        2014-09-30  156  err_regmap:
bdb0066df96e74a Pankaj Dubey        2014-09-30 @157  	iounmap(base);
bdb0066df96e74a Pankaj Dubey        2014-09-30  158  	return ERR_PTR(ret);
87d687301f38072 Dong Aisheng        2012-09-05  159  }
87d687301f38072 Dong Aisheng        2012-09-05  160  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki