From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from naesa05.arrow.com (naesa05.arrow.com [216.150.161.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6E41224AF7; Tue, 11 Mar 2025 07:35:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.26 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741678547; cv=none; b=TkuUDumllLuqmhtFTSNO9wLPIpV6Pcor78ZMpMbF72lL5o42Idag5XOLsKOaRl9JSMYySoJql2Bs+JtQixx1pN5tDBmkirwYzdfWS208nbE/TmqacTVbQOWUt9ho4t3dsR+jDyEY2OdnxAi+r4bqV9xTVgYfhA4cKVjBRbMFBus= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741678547; c=relaxed/simple; bh=rFFOc4JetP/QPixsfrXS6gb/c2VRdP/QXiDKL5gzO/c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=odkXxPnT/23khFTpCQLMF3vXa7j1abtQkwvfOJOjhUSH5454KlNm71fVTgt8Noa1rOU5FuusX8hh9X27pvIIFYhlM3pXAPkkAM2FNyGo4yOjmkAY36wJ66CGEIYXxB4F+ofMTdmGXFZRSoyudMw0WoFQ+u3FSY2HpKzzNnnhxUU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com; spf=pass smtp.mailfrom=einfochips.com; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b=kQeBRGR2; arc=none smtp.client-ip=216.150.161.26 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=einfochips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b="kQeBRGR2" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=einfochips.com; i=@einfochips.com; l=701; q=dns/txt; s=NAESA-Selector1; t=1741678546; x=1773214546; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rFFOc4JetP/QPixsfrXS6gb/c2VRdP/QXiDKL5gzO/c=; b=kQeBRGR2+F81cpzSfn9k5dhNWxGQjfwo36ppwoxkaWUR+FFK7B7eR5KK 7/2CncVDeDaTngT1gn6oeKJVr8vhmnVvPFxEXndPERZaHFyWheIrZIJm2 eJmyP6CfDM/KTK7T47Iy0RHDbNNdLLn2oWVQy5hKvDECysGJvHTYn66wp gXnq3OwKm/z4l9jb5Oxhcs65n0FQHAinn+hxI/k7xl+XlBiyImzUH1LTd BG2O+DVUQ5lCwL4pbqk+PFdDbNmNz6b2K1/jsFVOcwIb49HTfnX+CHQn1 FQtiusza7etKmnM+bxcKal1XhWUDo2WCXWH9XBFeXTu2DtcLzUubk1b7z A==; X-CSE-ConnectionGUID: /0SrXHFhQwuTOKTjXog5gA== X-CSE-MsgGUID: c76LeUkETeem86yvaGzGkg== X-IronPort-AV: E=Sophos;i="6.14,238,1736838000"; d="scan'208";a="20386371" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa05out.arrow.com with ESMTP; 11 Mar 2025 01:34:36 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Tue, 11 Mar 2025 13:04:32 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/10] riscv: Add Kconfig option for ESWIN platforms Date: Tue, 11 Mar 2025 13:04:24 +0530 Message-Id: <20250311073432.4068512-3-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250311073432.4068512-1-pinkesh.vaghela@einfochips.com> References: <20250311073432.4068512-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 11 Mar 2025 07:34:32.0782 (UTC) FILETIME=[081346E0:01DB9258] Create a config option to build ESWIN SoC specific resources Signed-off-by: Pinkesh Vaghela Reviewed-by: Samuel Holland --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1916cf7ba450..35594e365ca6 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,11 @@ menu "SoC selection" +config ARCH_ESWIN + bool "ESWIN SoCs" + help + This enables support for ESWIN SoC platform hardware, + including the ESWIN EIC7700 SoC. + config ARCH_MICROCHIP_POLARFIRE def_bool ARCH_MICROCHIP -- 2.25.1