[RFC PATCH 0/4] rtc: rzn1: support XTAL clk and SCMP method

[RFC PATCH 0/4] rtc: rzn1: support XTAL clk and SCMP method

[Wolfram Sang]

So far, the code and the binding for the RZ/N1D RTC assumed an input
clock of 32768Hz, so it was not explicitly described. It makes sense to
do this, though. For one reason, clocks with other frequencies might be
used which this RTC supports via the SCMP counting method. Also, the
upcoming R-Car Gen5 have only the SCMP method described, so we need to
use it there.

This series is for collecting comments about the approach. I am aware
that the DTS changes no to go in separately from the code changes. And
the last patch will be updated and resent once I have tested these
patches on hardware. That might take a while but I'd like the
preparational patches to go in earlier. They are benefitial for N1D,
after all.

The series has been tested on a Renesas RZ/N1D board with hacked
devicetree values.

Looking forward to comments.


Wolfram Sang (4):
  dt-bindings: rtc: rzn1: add optional second clock
  ARM: dts: renesas: r9a06g032: add second clock input to RTC
  rtc: rzn1: support input frequencies other than 32768Hz
  WIP rtc: rzn1: add driver support for R-Car Gen5

 .../bindings/rtc/renesas,rzn1-rtc.yaml        |  8 ++-
 .../dts/renesas/r9a06g032-rzn1d400-db.dts     |  4 ++
 arch/arm/boot/dts/renesas/r9a06g032.dtsi      |  4 +-
 drivers/rtc/rtc-rzn1.c                        | 67 ++++++++++++++++---
 4 files changed, 70 insertions(+), 13 deletions(-)

-- 
2.47.2

[RFC PATCH 1/4] dt-bindings: rtc: rzn1: add optional second clock

[Wolfram Sang]

The external crystal can be a second clock input. It is needed for the
SCMP counting method which allows using crystals different than 32768Hz.
It is also needed for an upcoming SoC which only supports the SCMP
method.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 .../devicetree/bindings/rtc/renesas,rzn1-rtc.yaml         | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml
index f6e0c613af67..f6fdcc7090b6 100644
--- a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml
@@ -33,10 +33,14 @@ properties:
       - const: pps
 
   clocks:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
 
   clock-names:
-    const: hclk
+    minItems: 1
+    items:
+      - const: hclk
+      - const: xtal
 
   power-domains:
     maxItems: 1
-- 
2.47.2

[RFC PATCH 2/4] ARM: dts: renesas: r9a06g032: add second clock input to RTC

[Wolfram Sang]

The external rtc clock is populated on the RZ/N1D module, so describe it
and add a reference to the RTC node.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---

For the non-RFC series, it makes probably sense to split this patch into
two.

 arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts | 4 ++++
 arch/arm/boot/dts/renesas/r9a06g032.dtsi            | 4 ++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
index 31cdca3e623c..c2311f761381 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
+++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
@@ -47,6 +47,10 @@ &eth_miic {
 	renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
 };
 
+&ext_rtc_clk {
+	clock-frequency = <32768>;
+};
+
 &gmac2 {
 	status = "okay";
 	phy-mode = "gmii";
diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index 7548291c8d7e..458dab9d3b7f 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -73,8 +73,8 @@ rtc0: rtc@40006000 {
 				     <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
 				     <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "alarm", "timer", "pps";
-			clocks = <&sysctrl R9A06G032_HCLK_RTC>;
-			clock-names = "hclk";
+			clocks = <&sysctrl R9A06G032_HCLK_RTC>, <&ext_rtc_clk>;
+			clock-names = "hclk", "xtal";
 			power-domains = <&sysctrl>;
 			status = "disabled";
 		};
-- 
2.47.2

Re: [RFC PATCH 1/4] dt-bindings: rtc: rzn1: add optional second clock

[Krzysztof Kozlowski]

On Thu, Mar 13, 2025 at 11:25:42AM +0100, Wolfram Sang wrote:
> The external crystal can be a second clock input. It is needed for the
> SCMP counting method which allows using crystals different than 32768Hz.
> It is also needed for an upcoming SoC which only supports the SCMP
> method.
>

Probably the binding was incomplete and you always had external crystal
connected. I assume you want to keep old DTS, so it is fine for me:

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [RFC PATCH 1/4] dt-bindings: rtc: rzn1: add optional second clock

[Wolfram Sang]

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> Probably the binding was incomplete and you always had external crystal
> connected. I assume you want to keep old DTS, so it is fine for me:

The documentation explicitly mentions how to wire clock lines if you are
not using the RTC and have no oscillator. But yeah, then the RTC DT node
should be disabled.

And yes, I want to be backwards compatible.

> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Thanks!


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Re: [RFC PATCH 2/4] ARM: dts: renesas: r9a06g032: add second clock input to RTC

[Geert Uytterhoeven]

Hi Wolfram,

On Thu, 13 Mar 2025 at 11:25, Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> The external rtc clock is populated on the RZ/N1D module, so describe it
> and add a reference to the RTC node.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

> For the non-RFC series, it makes probably sense to split this patch into
> two.

Indeed.

> --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
> +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
> @@ -47,6 +47,10 @@ &eth_miic {
>         renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
>  };
>
> +&ext_rtc_clk {
> +       clock-frequency = <32768>;
> +};

That's the mighty 0.033 MHz crystal X2_1? ;-)

This change is good for sure.

> +
>  &gmac2 {
>         status = "okay";
>         phy-mode = "gmii";
> diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> index 7548291c8d7e..458dab9d3b7f 100644
> --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> @@ -73,8 +73,8 @@ rtc0: rtc@40006000 {
>                                      <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
>                                      <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
>                         interrupt-names = "alarm", "timer", "pps";
> -                       clocks = <&sysctrl R9A06G032_HCLK_RTC>;
> -                       clock-names = "hclk";
> +                       clocks = <&sysctrl R9A06G032_HCLK_RTC>, <&ext_rtc_clk>;
> +                       clock-names = "hclk", "xtal";

This depends on whether we decide to provide direct access to ext_rtc_clk,
or through the system controller's clock provider.

>                         power-domains = <&sysctrl>;
>                         status = "disabled";
>                 };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds