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Tue, 18 Mar 2025 00:18:15 -0700 (PDT) Date: Tue, 18 Mar 2025 12:47:56 +0530 From: Manivannan Sadhasivam To: George Moussalem Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, andersson@kernel.org, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org, kishon@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, kw@linux.com, lpieralisi@kernel.org, p.zabel@pengutronix.de, quic_nsekar@quicinc.com, robh@kernel.org, robimarko@gmail.com, vkoul@kernel.org, quic_srichara@quicinc.com Subject: Re: [PATCH v3 5/6] arm64: dts: qcom: ipq5018: Add PCIe related nodes Message-ID: <20250318071756.uilfhwfzgr5gds3o@thinkpad> References: <20250305134239.2236590-1-george.moussalem@outlook.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, Mar 05, 2025 at 05:41:30PM +0400, George Moussalem wrote: > From: Sricharan Ramabadhran > > From: Nitheesh Sekar > > Add phy and controller nodes for a 2-lane Gen2 and > a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and > one global interrupt. > > Signed-off-by: Nitheesh Sekar > Signed-off-by: Sricharan R > Signed-off-by: George Moussalem > --- > arch/arm64/boot/dts/qcom/ipq5018.dtsi | 232 +++++++++++++++++++++++++- > 1 file changed, 230 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi > index 8914f2ef0bc4..301a044bdf6d 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi > @@ -147,6 +147,234 @@ usbphy0: phy@5b000 { > status = "disabled"; > }; > > + pcie1: pcie@78000 { > + compatible = "qcom,pcie-ipq5018"; > + reg = <0x00078000 0x3000>, > + <0x80000000 0xf1d>, > + <0x80000f20 0xa8>, > + <0x80001000 0x1000>, > + <0x80100000 0x1000>; > + reg-names = "parf", > + "dbi", > + "elbi", > + "atu", > + "config"; > + device_type = "pci"; > + linux,pci-domain = <0>; > + bus-range = <0x00 0xff>; > + num-lanes = <1>; > + max-link-speed = <2>; Why do you want to limit link speed? > + #address-cells = <3>; > + #size-cells = <2>; > + > + phys = <&pcie1_phy>; > + phy-names ="pciephy"; > + > + ranges = <0x81000000 0 0x80200000 0x80200000 0 0x00100000>, /* I/O */ > + <0x82000000 0 0x80300000 0x80300000 0 0x10000000>; /* MEM */ These ranges are wrong. Please check with other DT files. Same comments to other instance as well. > + > + msi-map = <0x0 &v2m0 0x0 0xff8>; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + ; > + interrupt-names = "msi0", > + "msi1", > + "msi2", > + "msi3", > + "msi4", > + "msi5", > + "msi6", > + "msi7", > + "global"; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ > + <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ > + <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ > + <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ > + > + clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, > + <&gcc GCC_PCIE1_AXI_M_CLK>, > + <&gcc GCC_PCIE1_AXI_S_CLK>, > + <&gcc GCC_PCIE1_AHB_CLK>, > + <&gcc GCC_PCIE1_AUX_CLK>, > + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>; > + clock-names = "iface", > + "axi_m", > + "axi_s", > + "ahb", > + "aux", > + "axi_bridge"; > + > + resets = <&gcc GCC_PCIE1_PIPE_ARES>, > + <&gcc GCC_PCIE1_SLEEP_ARES>, > + <&gcc GCC_PCIE1_CORE_STICKY_ARES>, > + <&gcc GCC_PCIE1_AXI_MASTER_ARES>, > + <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, > + <&gcc GCC_PCIE1_AHB_ARES>, > + <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>, > + <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>; > + reset-names = "pipe", > + "sleep", > + "sticky", > + "axi_m", > + "axi_s", > + "ahb", > + "axi_m_sticky", > + "axi_s_sticky"; > + > + status = "disabled"; > + > + pcie@0 { > + device_type = "pci"; > + reg = <0x0 0x0 0x0 0x0 0x0>; > + > + #address-cells = <3>; > + #size-cells = <2>; > + ranges; > + }; > + }; > + > + pcie1_phy: phy@7e000{ > + compatible = "qcom,ipq5018-uniphy-pcie-phy"; > + reg = <0x0007e000 0x800>; > + > + clocks = <&gcc GCC_PCIE1_PIPE_CLK>; > + > + resets = <&gcc GCC_PCIE1_PHY_BCR>, > + <&gcc GCC_PCIE1PHY_PHY_BCR>; > + > + #clock-cells = <0>; > + Please get rid of these newlines between -cells properties. - Mani -- மணிவண்ணன் சதாசிவம்