From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from naesa04.arrow.com (naesa04.arrow.com [216.150.161.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 732712253FE; Thu, 20 Mar 2025 10:56:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.24 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742468163; cv=none; b=TsOjLR4DE3o95FE2dD6gtOuQSaRQFc0FgV9jaoovbWso6oApiPHEp4rdXJCh8OuPY+91KdVoWoHOY3JyVXTOFdsDiV96wInILYbAJlKABRDA2q/pLQSozdy3RPGHTwOocXPdrovk43Q1PPKgzy9Ze5VCv5Lp4KUo4sWmq1YtaJo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742468163; c=relaxed/simple; bh=UqA7xvW45JJ2k7vIZdX/kp4Mb5++ZRHaADRZ/l5k7Zk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZDdGXosrkaZeC1ar6bWB4PrSnc1Rj0RjmwhcK7NGIe8fbS8mh4p76cU1+pw5QK3pApnd0ZrjQCgCKECqLQIbrWyWv/9X/Wof5rh2gaOoony1iPIDdu3M2LNf/egiIIIgUQFydKHdC9Ll67EgDORhzEyzR85iUIO3DzrbZsX45mg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com; spf=pass smtp.mailfrom=einfochips.com; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b=rfbuh/sf; arc=none smtp.client-ip=216.150.161.24 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=einfochips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b="rfbuh/sf" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=einfochips.com; i=@einfochips.com; l=754; q=dns/txt; s=NAESA-Selector1; t=1742468161; x=1774004161; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UqA7xvW45JJ2k7vIZdX/kp4Mb5++ZRHaADRZ/l5k7Zk=; b=rfbuh/sffcSShmZ6Qa+eLUp9LiahzbJ/eDke1++5pDSIQ0gYXu+ztRKt YWXNd8UEjK7dUGuiW1WqZkSMQR5QnHz4RBdWzmgvnxG5ZGvDsUOMjeAXO HooomGsBwPWdVQ+cPsrIUIbxwd11+JM2PFLht4bU+J8hcSnd/oHGp6xGk RkPRjz/PNKM0n/Jld+otiiwYBFvpjaY6cy6wzhvTumB301IjkHk98FVmc WzXpf1SSym7HjkzE8AaYkyZSuS3B6e3ddwhA5IlGcCBZax4KUeBDakP// cYyY189P8Jj19DURim/1RJQZ8kVqChSTjM4NZycvyxJzCFsx1UuOUzcXB g==; X-CSE-ConnectionGUID: JO4SxFVGRwuv8Ryy4l1vxw== X-CSE-MsgGUID: NR7rZqOtS46ICR3cMBVJiA== X-IronPort-AV: E=Sophos;i="6.14,261,1736838000"; d="scan'208";a="80263094" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa04out.arrow.com with ESMTP; 20 Mar 2025 04:54:53 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Thu, 20 Mar 2025 16:24:49 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/10] riscv: Add Kconfig option for ESWIN platforms Date: Thu, 20 Mar 2025 16:24:41 +0530 Message-Id: <20250320105449.2094192-3-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> References: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 20 Mar 2025 10:54:49.0788 (UTC) FILETIME=[807C9FC0:01DB9986] Create a config option to build ESWIN SoC specific resources Signed-off-by: Pinkesh Vaghela Reviewed-by: Samuel Holland Acked-by: Conor Dooley --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1916cf7ba450..35594e365ca6 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,11 @@ menu "SoC selection" +config ARCH_ESWIN + bool "ESWIN SoCs" + help + This enables support for ESWIN SoC platform hardware, + including the ESWIN EIC7700 SoC. + config ARCH_MICROCHIP_POLARFIRE def_bool ARCH_MICROCHIP -- 2.25.1