[PATCH 0/4] dt-bindings: edac: altera-s10: Convert to YAML

[PATCH 0/4] dt-bindings: edac: altera-s10: Convert to YAML

[Matthew Gerlach]

This patch set creates a YAML device tree binding for the Altera Stratix10
Error Detection and Correction component referred to as the ECC Manager. The
peripheral subcomponents are the same hardware as the Arria10 implementation;
so the YAML binding does not change compatible strings of the subcomponents.
This more accurate hardware description requires some minor driver and DTSI/DTS
changes.

Patch 1:
  Convert text device tree binding to YAML.

Patch 2:
  Update driver to allow the peripheral subcomponents to be child nodes of
  altr,socfpga-s10-ecc-manager.

Patch 3:
  Update Agilex DTSI to use correct compatible strings for peripheral
  subcomponents. 

Patch 4:
  Update Stratix10 DTSI/DTS to use correct compatibles strings.

Matthew Gerlach (4):
  dt-bindings: edac: altera-s10: Convert to YAML
  EDAC, altera: update driver to reflect hw/yaml
  arm64: dts: agilex: Update eccmgr in DTSI to reflect hw/yaml
  arm64: dts: startix10: Update eccmgr in DTSI/DTS to reflect hw/yaml

 .../edac/altr,socfpga-s10-ecc-manager.yaml    | 228 ++++++++++++++++++
 .../bindings/edac/socfpga-eccmgr.txt          | 150 ------------
 MAINTAINERS                                   |   5 +
 .../boot/dts/altera/socfpga_stratix10.dtsi    |  15 +-
 .../dts/altera/socfpga_stratix10_socdk.dts    |   3 +-
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |  18 +-
 drivers/edac/altera_edac.c                    |   3 +
 7 files changed, 248 insertions(+), 174 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml

-- 
2.35.3

[PATCH 1/4] dt-bindings: edac: altera-s10: Convert to YAML

[Matthew Gerlach]

Convert the device tree bindings for the Altera Stratix10 SoCFPGA ECC
Manager from text to yaml. The hardware for the device tree subnodes
have not changed since Arria10; so don't change the compatible strings
to include "-s10-".

Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 .../edac/altr,socfpga-s10-ecc-manager.yaml    | 228 ++++++++++++++++++
 .../bindings/edac/socfpga-eccmgr.txt          | 150 ------------
 MAINTAINERS                                   |   5 +
 3 files changed, 233 insertions(+), 150 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml

diff --git a/Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml b/Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
new file mode 100644
index 000000000000..ad057a63e88b
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
@@ -0,0 +1,228 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2025 Altera Corporation
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/altr,socfpga-s10-ecc-manager.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera Stratix10 SoCFPGA ECC Manager (ARM64)
+
+maintainers:
+  - Matthew Gerlach <matthew.gerlach@altera.com
+
+description: |
+  The Stratix10 implementation of the SoCFPGA ECC Manager counts and corrects
+  single bit errors. Double bit errors are treated as SErrors in ARM64. This
+  implementation requires access to registers only available to the Secure
+  Device Manager (SDM) via Secure Monitor Calls (SMC).
+
+properties:
+
+  compatible:
+    items:
+      - const: altr,socfpga-s10-ecc-manager
+
+  altr,sysmgr-syscon:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+
+  ranges: true
+
+  sdramedac:
+    type: object
+    additionalProperties: false
+    properties:
+      compatible:
+        const: altr,sdram-edac-s10
+      altr,sdr-syscon:
+        $ref: /schemas/types.yaml#/definitions/phandle
+        description: phandle to SDRAM parent
+      interrupts:
+        maxItems: 1
+    required:
+      - compatible
+      - altr,sdr-syscon
+      - interrupts
+
+  ocram-ecc@ff8cc000:
+    type: object
+    additionalProperties: false
+    properties:
+      compatible:
+        items:
+          - const: altr,socfpga-a10-ocram-ecc
+
+      reg:
+        maxItems: 1
+      altr,ecc-parent:
+        $ref: /schemas/types.yaml#/definitions/phandle
+        description: phandle to OCRAM parent
+      interrupts:
+        maxItems: 1
+    required:
+      - compatible
+      - reg
+      - altr,ecc-parent
+      - interrupts
+
+  usb0-ecc@ff8c4000:
+    type: object
+    additionalProperties: false
+    properties:
+      compatible:
+        items:
+          - const: altr,socfpga-usb-ecc
+      reg:
+        maxItems: 1
+      altr,ecc-parent:
+        $ref: /schemas/types.yaml#/definitions/phandle
+        description: phandle to USB parent
+      interrupts:
+        maxItems: 1
+    required:
+      - compatible
+      - reg
+      - altr,ecc-parent
+      - interrupts
+
+  emac0-rx-ecc@ff8c0000:
+    type: object
+    additionalProperties: false
+    properties:
+      compatible:
+        items:
+          - const: altr,socfpga-eth-mac-ecc
+      reg:
+        maxItems: 1
+      altr,ecc-parent:
+        $ref: /schemas/types.yaml#/definitions/phandle
+        description: phandle to ethernet parent
+      interrupts:
+        maxItems: 1
+    required:
+      - compatible
+      - reg
+      - altr,ecc-parent
+      - interrupts
+
+  emac0-tx-ecc@ff8c0400:
+    type: object
+    additionalProperties: false
+    properties:
+      compatible:
+        items:
+          - const: altr,socfpga-eth-mac-ecc
+      reg:
+        maxItems: 1
+      altr,ecc-parent:
+        $ref: /schemas/types.yaml#/definitions/phandle
+        description: phandle to ethernet parent
+      interrupts:
+        maxItems: 1
+    required:
+      - compatible
+      - reg
+      - altr,ecc-parent
+      - interrupts
+
+  sdmmca-ecc@ff8c8c00:
+    type: object
+    additionalProperties: false
+    properties:
+      compatible:
+        items:
+          - const: altr,socfpga-sdmmc-ecc
+      reg:
+        maxItems: 1
+      altr,ecc-parent:
+        $ref: /schemas/types.yaml#/definitions/phandle
+        description: phandle to ethernet parent
+      interrupts:
+        maxItems: 2
+    required:
+      - compatible
+      - reg
+      - altr,ecc-parent
+      - interrupts
+
+required:
+  - compatible
+  - altr,sysmgr-syscon
+  - "#address-cells"
+  - "#size-cells"
+  - interrupts
+  - interrupt-controller
+  - "#interrupt-cells"
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    eccmgr {
+        compatible = "altr,socfpga-s10-ecc-manager";
+        altr,sysmgr-syscon = <&sysmgr>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        ranges;
+
+        sdramedac {
+            compatible = "altr,sdram-edac-s10";
+            altr,sdr-syscon = <&sdr>;
+            interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        ocram-ecc@ff8cc000 {
+            compatible = "altr,socfpga-a10-ocram-ecc";
+            reg = <0xff8cc000 0x100>;
+            altr,ecc-parent = <&ocram>;
+            interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        usb0-ecc@ff8c4000 {
+            compatible = "altr,socfpga-usb-ecc";
+            reg = <0xff8c4000 0x100>;
+            altr,ecc-parent = <&usb0>;
+            interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        emac0-rx-ecc@ff8c0000 {
+            compatible = "altr,socfpga-eth-mac-ecc";
+            reg = <0xff8c0000 0x100>;
+            altr,ecc-parent = <&gmac0>;
+            interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        emac0-tx-ecc@ff8c0400 {
+            compatible = "altr,socfpga-eth-mac-ecc";
+            reg = <0xff8c0400 0x100>;
+            altr,ecc-parent = <&gmac0>;
+            interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        sdmmca-ecc@ff8c8c00 {
+            compatible = "altr,socfpga-sdmmc-ecc";
+            reg = <0xff8c8c00 0x100>;
+            altr,ecc-parent = <&mmc>;
+            interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+                         <15 IRQ_TYPE_LEVEL_HIGH>;
+        };
+    };
diff --git a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
index 8f52206cfd2a..4a1714f96bab 100644
--- a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
@@ -231,153 +231,3 @@ Example:
 				     <48 IRQ_TYPE_LEVEL_HIGH>;
 		};
 	};
-
-Stratix10 SoCFPGA ECC Manager (ARM64)
-The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
-in a shared register similar to the Arria10. However, Stratix10 ECC
-requires access to registers that can only be read from Secure Monitor
-with SMC calls. Therefore the device tree is slightly different. Note
-that only 1 interrupt is sent in Stratix10 because the double bit errors
-are treated as SErrors in ARM64 instead of IRQs in ARM32.
-
-Required Properties:
-- compatible : Should be "altr,socfpga-s10-ecc-manager"
-- altr,sysgr-syscon : phandle to Stratix10 System Manager Block
-	              containing the ECC manager registers.
-- interrupts : Should be single bit error interrupt.
-- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
-- #interrupt-cells : must be set to 2.
-- #address-cells: must be 1
-- #size-cells: must be 1
-- ranges : standard definition, should translate from local addresses
-
-Subcomponents:
-
-SDRAM ECC
-Required Properties:
-- compatible : Should be "altr,sdram-edac-s10"
-- interrupts : Should be single bit error interrupt.
-
-On-Chip RAM ECC
-Required Properties:
-- compatible      : Should be "altr,socfpga-s10-ocram-ecc"
-- reg             : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent OCRAM node.
-- interrupts      : Should be single bit error interrupt.
-
-Ethernet FIFO ECC
-Required Properties:
-- compatible      : Should be "altr,socfpga-s10-eth-mac-ecc"
-- reg             : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent Ethernet node.
-- interrupts      : Should be single bit error interrupt.
-
-NAND FIFO ECC
-Required Properties:
-- compatible      : Should be "altr,socfpga-s10-nand-ecc"
-- reg             : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent NAND node.
-- interrupts      : Should be single bit error interrupt.
-
-DMA FIFO ECC
-Required Properties:
-- compatible      : Should be "altr,socfpga-s10-dma-ecc"
-- reg             : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent DMA node.
-- interrupts      : Should be single bit error interrupt.
-
-USB FIFO ECC
-Required Properties:
-- compatible      : Should be "altr,socfpga-s10-usb-ecc"
-- reg             : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent USB node.
-- interrupts      : Should be single bit error interrupt.
-
-SDMMC FIFO ECC
-Required Properties:
-- compatible      : Should be "altr,socfpga-s10-sdmmc-ecc"
-- reg             : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent SD/MMC node.
-- interrupts      : Should be single bit error interrupt for port A
-		    and then single bit error interrupt for port B.
-
-Example:
-
-	eccmgr {
-		compatible = "altr,socfpga-s10-ecc-manager";
-		altr,sysmgr-syscon = <&sysmgr>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		interrupts = <0 15 4>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ranges;
-
-		sdramedac {
-			compatible = "altr,sdram-edac-s10";
-			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		ocram-ecc@ff8cc000 {
-			compatible = "altr,socfpga-s10-ocram-ecc";
-			reg = <ff8cc000 0x100>;
-			altr,ecc-parent = <&ocram>;
-			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		emac0-rx-ecc@ff8c0000 {
-			compatible = "altr,socfpga-s10-eth-mac-ecc";
-			reg = <0xff8c0000 0x100>;
-			altr,ecc-parent = <&gmac0>;
-			interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		emac0-tx-ecc@ff8c0400 {
-			compatible = "altr,socfpga-s10-eth-mac-ecc";
-			reg = <0xff8c0400 0x100>;
-			altr,ecc-parent = <&gmac0>;
-			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
-		};
-
-		nand-buf-ecc@ff8c8000 {
-			compatible = "altr,socfpga-s10-nand-ecc";
-			reg = <0xff8c8000 0x100>;
-			altr,ecc-parent = <&nand>;
-			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		nand-rd-ecc@ff8c8400 {
-			compatible = "altr,socfpga-s10-nand-ecc";
-			reg = <0xff8c8400 0x100>;
-			altr,ecc-parent = <&nand>;
-			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		nand-wr-ecc@ff8c8800 {
-			compatible = "altr,socfpga-s10-nand-ecc";
-			reg = <0xff8c8800 0x100>;
-			altr,ecc-parent = <&nand>;
-			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		dma-ecc@ff8c9000 {
-			compatible = "altr,socfpga-s10-dma-ecc";
-			reg = <0xff8c9000 0x100>;
-			altr,ecc-parent = <&pdma>;
-			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
-
-		usb0-ecc@ff8c4000 {
-			compatible = "altr,socfpga-s10-usb-ecc";
-			reg = <0xff8c4000 0x100>;
-			altr,ecc-parent = <&usb0>;
-			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		sdmmc-ecc@ff8c8c00 {
-			compatible = "altr,socfpga-s10-sdmmc-ecc";
-			reg = <0xff8c8c00 0x100>;
-			altr,ecc-parent = <&mmc>;
-			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
-				     <15 IRQ_TYPE_LEVEL_HIGH>;
-		};
-	};
diff --git a/MAINTAINERS b/MAINTAINERS
index 0c8fb060072b..236e23174719 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3191,6 +3191,11 @@ M:	Dinh Nguyen <dinguyen@kernel.org>
 S:	Maintained
 F:	drivers/clk/socfpga/
 
+ARM/SOCFPGA EDAC BINDINGS
+M:	Matthew Gerlach <matthew.gerlach@altera.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
+
 ARM/SOCFPGA EDAC SUPPORT
 M:	Dinh Nguyen <dinguyen@kernel.org>
 S:	Maintained
-- 
2.35.3

[PATCH 2/4] EDAC, altera: update driver to reflect hw/yaml

[Matthew Gerlach]

The device tree subnodes, and hardware, for the eccmgr are
the same for Arria10, Stratix10, and Agilex. Update driver
to allow the subnodes to be allowed for "altr,socfpga-s10-ecc-manager".

Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 drivers/edac/altera_edac.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 3e971f902363..895a5beb700f 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1030,6 +1030,9 @@ static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
 
 	np = of_find_compatible_node(NULL, NULL,
 				     "altr,socfpga-a10-ecc-manager");
+	if (!np)
+		np = of_find_compatible_node(NULL, NULL,
+					     "altr,socfpga-s10-ecc-manager");
 	if (!np) {
 		edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
 		return -ENODEV;
-- 
2.35.3

[PATCH 3/4] arm64: dts: agilex: Update eccmgr in DTSI to reflect hw/yaml

[Matthew Gerlach]

Update socfpga_agilex.dtsi to track the actual hardware description
provided in altr,socfpga-s10-ecc-manager.yaml.

Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 1235ba5a9865..708cb8e762b6 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -602,8 +602,7 @@ sdr: sdr@f8011100 {
 		};
 
 		eccmgr {
-			compatible = "altr,socfpga-s10-ecc-manager",
-				     "altr,socfpga-a10-ecc-manager";
+			compatible = "altr,socfpga-s10-ecc-manager";
 			altr,sysmgr-syscon = <&sysmgr>;
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -619,40 +618,35 @@ sdramedac {
 			};
 
 			ocram-ecc@ff8cc000 {
-				compatible = "altr,socfpga-s10-ocram-ecc",
-					     "altr,socfpga-a10-ocram-ecc";
+				compatible = "altr,socfpga-a10-ocram-ecc";
 				reg = <0xff8cc000 0x100>;
 				altr,ecc-parent = <&ocram>;
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			usb0-ecc@ff8c4000 {
-				compatible = "altr,socfpga-s10-usb-ecc",
-					     "altr,socfpga-usb-ecc";
+				compatible = "altr,socfpga-usb-ecc";
 				reg = <0xff8c4000 0x100>;
 				altr,ecc-parent = <&usb0>;
 				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			emac0-rx-ecc@ff8c0000 {
-				compatible = "altr,socfpga-s10-eth-mac-ecc",
-					     "altr,socfpga-eth-mac-ecc";
+				compatible = "altr,socfpga-eth-mac-ecc";
 				reg = <0xff8c0000 0x100>;
 				altr,ecc-parent = <&gmac0>;
 				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			emac0-tx-ecc@ff8c0400 {
-				compatible = "altr,socfpga-s10-eth-mac-ecc",
-					     "altr,socfpga-eth-mac-ecc";
+				compatible = "altr,socfpga-eth-mac-ecc";
 				reg = <0xff8c0400 0x100>;
 				altr,ecc-parent = <&gmac0>;
 				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
 			sdmmca-ecc@ff8c8c00 {
-				compatible = "altr,socfpga-s10-sdmmc-ecc",
-					     "altr,socfpga-sdmmc-ecc";
+				compatible = "altr,socfpga-sdmmc-ecc";
 				reg = <0xff8c8c00 0x100>;
 				altr,ecc-parent = <&mmc>;
 				interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.35.3

[PATCH 4/4] arm64: dts: startix10: Update eccmgr in DTSI/DTS to reflect hw/yaml

[Matthew Gerlach]

Update socfpga_stratix10.dtsi and socfpga_stratix10_socdk.dts to track the
actual hardware description provided in altr,socfpga-s10-ecc-manager.yaml.

Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 15 +++++----------
 .../boot/dts/altera/socfpga_stratix10_socdk.dts   |  3 +--
 2 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 0def0b0daaf7..647f4bb1e4a2 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -579,8 +579,7 @@ sdr: sdr@f8011100 {
 		};
 
 		eccmgr {
-			compatible = "altr,socfpga-s10-ecc-manager",
-				     "altr,socfpga-a10-ecc-manager";
+			compatible = "altr,socfpga-s10-ecc-manager";
 			altr,sysmgr-syscon = <&sysmgr>;
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -596,32 +595,28 @@ sdramedac {
 			};
 
 			ocram-ecc@ff8cc000 {
-				compatible = "altr,socfpga-s10-ocram-ecc",
-					     "altr,socfpga-a10-ocram-ecc";
+				compatible = "altr,socfpga-a10-ocram-ecc";
 				reg = <0xff8cc000 0x100>;
 				altr,ecc-parent = <&ocram>;
 				interrupts = <1 4>;
 			};
 
 			usb0-ecc@ff8c4000 {
-				compatible = "altr,socfpga-s10-usb-ecc",
-					     "altr,socfpga-usb-ecc";
+				compatible = "altr,socfpga-usb-ecc";
 				reg = <0xff8c4000 0x100>;
 				altr,ecc-parent = <&usb0>;
 				interrupts = <2 4>;
 			};
 
 			emac0-rx-ecc@ff8c0000 {
-				compatible = "altr,socfpga-s10-eth-mac-ecc",
-					     "altr,socfpga-eth-mac-ecc";
+				compatible = "altr,socfpga-eth-mac-ecc";
 				reg = <0xff8c0000 0x100>;
 				altr,ecc-parent = <&gmac0>;
 				interrupts = <4 4>;
 			};
 
 			emac0-tx-ecc@ff8c0400 {
-				compatible = "altr,socfpga-s10-eth-mac-ecc",
-					     "altr,socfpga-eth-mac-ecc";
+				compatible = "altr,socfpga-eth-mac-ecc";
 				reg = <0xff8c0400 0x100>;
 				altr,ecc-parent = <&gmac0>;
 				interrupts = <5 4>;
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 4eee777ef1a1..06b91c7c0a45 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -54,8 +54,7 @@ ref_033v: regulator-v-ref {
 	soc@0 {
 		eccmgr {
 			sdmmca-ecc@ff8c8c00 {
-				compatible = "altr,socfpga-s10-sdmmc-ecc",
-					     "altr,socfpga-sdmmc-ecc";
+				compatible = "altr,socfpga-sdmmc-ecc";
 				reg = <0xff8c8c00 0x100>;
 				altr,ecc-parent = <&mmc>;
 				interrupts = <14 4>,
-- 
2.35.3

Re: [PATCH 0/4] dt-bindings: edac: altera-s10: Convert to YAML

[Rob Herring (Arm)]

On Thu, 20 Mar 2025 09:46:18 -0700, Matthew Gerlach wrote:
> This patch set creates a YAML device tree binding for the Altera Stratix10
> Error Detection and Correction component referred to as the ECC Manager. The
> peripheral subcomponents are the same hardware as the Arria10 implementation;
> so the YAML binding does not change compatible strings of the subcomponents.
> This more accurate hardware description requires some minor driver and DTSI/DTS
> changes.
> 
> Patch 1:
>   Convert text device tree binding to YAML.
> 
> Patch 2:
>   Update driver to allow the peripheral subcomponents to be child nodes of
>   altr,socfpga-s10-ecc-manager.
> 
> Patch 3:
>   Update Agilex DTSI to use correct compatible strings for peripheral
>   subcomponents.
> 
> Patch 4:
>   Update Stratix10 DTSI/DTS to use correct compatibles strings.
> 
> Matthew Gerlach (4):
>   dt-bindings: edac: altera-s10: Convert to YAML
>   EDAC, altera: update driver to reflect hw/yaml
>   arm64: dts: agilex: Update eccmgr in DTSI to reflect hw/yaml
>   arm64: dts: startix10: Update eccmgr in DTSI/DTS to reflect hw/yaml
> 
>  .../edac/altr,socfpga-s10-ecc-manager.yaml    | 228 ++++++++++++++++++
>  .../bindings/edac/socfpga-eccmgr.txt          | 150 ------------
>  MAINTAINERS                                   |   5 +
>  .../boot/dts/altera/socfpga_stratix10.dtsi    |  15 +-
>  .../dts/altera/socfpga_stratix10_socdk.dts    |   3 +-
>  arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |  18 +-
>  drivers/edac/altera_edac.c                    |   3 +
>  7 files changed, 248 insertions(+), 174 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
> 
> --
> 2.35.3
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/altera/' for 20250320164622.6971-1-matthew.gerlach@altera.com:

arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dtb: eccmgr: sdmmca-ecc@ff8c8c00:compatible:0: 'altr,socfpga-sdmmc-ecc' was expected
	from schema $id: http://devicetree.org/schemas/altr,socfpga-s10-ecc-manager.yaml#
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dtb: eccmgr: sdmmca-ecc@ff8c8c00:compatible: ['altr,socfpga-s10-sdmmc-ecc', 'altr,socfpga-sdmmc-ecc'] is too long
	from schema $id: http://devicetree.org/schemas/altr,socfpga-s10-ecc-manager.yaml#

Re: [PATCH 1/4] dt-bindings: edac: altera-s10: Convert to YAML

[Rob Herring]

On Thu, Mar 20, 2025 at 09:46:19AM -0700, Matthew Gerlach wrote:
> Convert the device tree bindings for the Altera Stratix10 SoCFPGA ECC
> Manager from text to yaml. The hardware for the device tree subnodes
> have not changed since Arria10; so don't change the compatible strings
> to include "-s10-".

Nice to see this.

> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> ---
>  .../edac/altr,socfpga-s10-ecc-manager.yaml    | 228 ++++++++++++++++++
>  .../bindings/edac/socfpga-eccmgr.txt          | 150 ------------
>  MAINTAINERS                                   |   5 +
>  3 files changed, 233 insertions(+), 150 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
> 
> diff --git a/Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml b/Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
> new file mode 100644
> index 000000000000..ad057a63e88b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
> @@ -0,0 +1,228 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (C) 2025 Altera Corporation
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/altr,socfpga-s10-ecc-manager.yaml#

schemas/edac/...

> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera Stratix10 SoCFPGA ECC Manager (ARM64)
> +
> +maintainers:
> +  - Matthew Gerlach <matthew.gerlach@altera.com
> +
> +description: |

Don't need '|'.

> +  The Stratix10 implementation of the SoCFPGA ECC Manager counts and corrects
> +  single bit errors. Double bit errors are treated as SErrors in ARM64. This
> +  implementation requires access to registers only available to the Secure
> +  Device Manager (SDM) via Secure Monitor Calls (SMC).
> +
> +properties:
> +
> +  compatible:
> +    items:
> +      - const: altr,socfpga-s10-ecc-manager
> +
> +  altr,sysmgr-syscon:
> +    maxItems: 1

Vendor properties last (but before child nodes).

> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  "#interrupt-cells":
> +    const: 2
> +
> +  ranges: true
> +
> +  sdramedac:
> +    type: object
> +    additionalProperties: false

blank line

> +    properties:
> +      compatible:
> +        const: altr,sdram-edac-s10

blank line

> +      altr,sdr-syscon:
> +        $ref: /schemas/types.yaml#/definitions/phandle
> +        description: phandle to SDRAM parent

blank line

> +      interrupts:
> +        maxItems: 1

blank line

And similar on the rest.

> +    required:
> +      - compatible
> +      - altr,sdr-syscon
> +      - interrupts
> +
> +  ocram-ecc@ff8cc000:
> +    type: object
> +    additionalProperties: false
> +    properties:
> +      compatible:
> +        items:

You can drop 'items' if there's only 1 entry.

> +          - const: altr,socfpga-a10-ocram-ecc
> +
> +      reg:
> +        maxItems: 1
> +      altr,ecc-parent:
> +        $ref: /schemas/types.yaml#/definitions/phandle
> +        description: phandle to OCRAM parent
> +      interrupts:
> +        maxItems: 1
> +    required:
> +      - compatible
> +      - reg
> +      - altr,ecc-parent
> +      - interrupts
> +
> +  usb0-ecc@ff8c4000:
> +    type: object
> +    additionalProperties: false
> +    properties:
> +      compatible:
> +        items:
> +          - const: altr,socfpga-usb-ecc
> +      reg:
> +        maxItems: 1
> +      altr,ecc-parent:
> +        $ref: /schemas/types.yaml#/definitions/phandle
> +        description: phandle to USB parent
> +      interrupts:
> +        maxItems: 1
> +    required:
> +      - compatible
> +      - reg
> +      - altr,ecc-parent
> +      - interrupts
> +
> +  emac0-rx-ecc@ff8c0000:
> +    type: object
> +    additionalProperties: false
> +    properties:
> +      compatible:
> +        items:
> +          - const: altr,socfpga-eth-mac-ecc
> +      reg:
> +        maxItems: 1
> +      altr,ecc-parent:
> +        $ref: /schemas/types.yaml#/definitions/phandle
> +        description: phandle to ethernet parent
> +      interrupts:
> +        maxItems: 1
> +    required:
> +      - compatible
> +      - reg
> +      - altr,ecc-parent
> +      - interrupts
> +
> +  emac0-tx-ecc@ff8c0400:
> +    type: object
> +    additionalProperties: false
> +    properties:
> +      compatible:
> +        items:
> +          - const: altr,socfpga-eth-mac-ecc
> +      reg:
> +        maxItems: 1
> +      altr,ecc-parent:
> +        $ref: /schemas/types.yaml#/definitions/phandle
> +        description: phandle to ethernet parent
> +      interrupts:
> +        maxItems: 1
> +    required:
> +      - compatible
> +      - reg
> +      - altr,ecc-parent
> +      - interrupts
> +
> +  sdmmca-ecc@ff8c8c00:
> +    type: object
> +    additionalProperties: false
> +    properties:
> +      compatible:
> +        items:
> +          - const: altr,socfpga-sdmmc-ecc
> +      reg:
> +        maxItems: 1
> +      altr,ecc-parent:
> +        $ref: /schemas/types.yaml#/definitions/phandle
> +        description: phandle to ethernet parent
> +      interrupts:
> +        maxItems: 2
> +    required:
> +      - compatible
> +      - reg
> +      - altr,ecc-parent
> +      - interrupts
> +
> +required:
> +  - compatible
> +  - altr,sysmgr-syscon
> +  - "#address-cells"
> +  - "#size-cells"
> +  - interrupts
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +  - ranges
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    eccmgr {
> +        compatible = "altr,socfpga-s10-ecc-manager";
> +        altr,sysmgr-syscon = <&sysmgr>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-controller;
> +        #interrupt-cells = <2>;
> +        ranges;
> +
> +        sdramedac {
> +            compatible = "altr,sdram-edac-s10";
> +            altr,sdr-syscon = <&sdr>;
> +            interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
> +        };
> +
> +        ocram-ecc@ff8cc000 {
> +            compatible = "altr,socfpga-a10-ocram-ecc";
> +            reg = <0xff8cc000 0x100>;
> +            altr,ecc-parent = <&ocram>;
> +            interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
> +        };
> +
> +        usb0-ecc@ff8c4000 {
> +            compatible = "altr,socfpga-usb-ecc";
> +            reg = <0xff8c4000 0x100>;
> +            altr,ecc-parent = <&usb0>;
> +            interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
> +        };
> +
> +        emac0-rx-ecc@ff8c0000 {
> +            compatible = "altr,socfpga-eth-mac-ecc";
> +            reg = <0xff8c0000 0x100>;
> +            altr,ecc-parent = <&gmac0>;
> +            interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
> +        };
> +
> +        emac0-tx-ecc@ff8c0400 {
> +            compatible = "altr,socfpga-eth-mac-ecc";
> +            reg = <0xff8c0400 0x100>;
> +            altr,ecc-parent = <&gmac0>;
> +            interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
> +        };
> +
> +        sdmmca-ecc@ff8c8c00 {
> +            compatible = "altr,socfpga-sdmmc-ecc";
> +            reg = <0xff8c8c00 0x100>;
> +            altr,ecc-parent = <&mmc>;
> +            interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
> +                         <15 IRQ_TYPE_LEVEL_HIGH>;
> +        };
> +    };

Re: [PATCH 3/4] arm64: dts: agilex: Update eccmgr in DTSI to reflect hw/yaml

[Rob Herring]

On Thu, Mar 20, 2025 at 09:46:21AM -0700, Matthew Gerlach wrote:
> Update socfpga_agilex.dtsi to track the actual hardware description
> provided in altr,socfpga-s10-ecc-manager.yaml.
> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> ---
>  arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 18 ++++++------------
>  1 file changed, 6 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> index 1235ba5a9865..708cb8e762b6 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> @@ -602,8 +602,7 @@ sdr: sdr@f8011100 {
>  		};
>  
>  		eccmgr {
> -			compatible = "altr,socfpga-s10-ecc-manager",
> -				     "altr,socfpga-a10-ecc-manager";
> +			compatible = "altr,socfpga-s10-ecc-manager";

You are breaking the ABI here. Before this series, the driver required 
altr,socfpga-a10-ecc-manager.

>  			altr,sysmgr-syscon = <&sysmgr>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
> @@ -619,40 +618,35 @@ sdramedac {
>  			};
>  
>  			ocram-ecc@ff8cc000 {
> -				compatible = "altr,socfpga-s10-ocram-ecc",
> -					     "altr,socfpga-a10-ocram-ecc";
> +				compatible = "altr,socfpga-a10-ocram-ecc";

AIUI, nothing used altr,socfpga-s10-ocram-ecc, so this change is okay I 
guess. Normally, we'd require both because there might be some 
difference you find later on, but here you could just look at the parent 
node compatible.

If it were me, I'd just add the compatible string in the schema and 
avoid the .dts change. That would have been less work...

Rob

Re: [PATCH 1/4] dt-bindings: edac: altera-s10: Convert to YAML

[Gerlach, Matthew]

On 3/20/2025 12:27 PM, Rob Herring wrote:
> On Thu, Mar 20, 2025 at 09:46:19AM -0700, Matthew Gerlach wrote:
> > Convert the device tree bindings for the Altera Stratix10 SoCFPGA ECC
> > Manager from text to yaml. The hardware for the device tree subnodes
> > have not changed since Arria10; so don't change the compatible strings
> > to include "-s10-".
>
> Nice to see this.
I am looking forward to seeing all the socfpga schema check errors gone.
>
> > Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> > ---
> >  .../edac/altr,socfpga-s10-ecc-manager.yaml    | 228 ++++++++++++++++++
> >  .../bindings/edac/socfpga-eccmgr.txt          | 150 ------------
> >  MAINTAINERS                                   |   5 +
> >  3 files changed, 233 insertions(+), 150 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml b/Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
> > new file mode 100644
> > index 000000000000..ad057a63e88b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/edac/altr,socfpga-s10-ecc-manager.yaml
> > @@ -0,0 +1,228 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +# Copyright (C) 2025 Altera Corporation
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/altr,socfpga-s10-ecc-manager.yaml#
>
> schemas/edac/...
I will add the /edac to the patch.
>
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Altera Stratix10 SoCFPGA ECC Manager (ARM64)
> > +
> > +maintainers:
> > +  - Matthew Gerlach <matthew.gerlach@altera.com
> > +
> > +description: |
>
> Don't need '|'.
I will remove the '|'
>
> > +  The Stratix10 implementation of the SoCFPGA ECC Manager counts and corrects
> > +  single bit errors. Double bit errors are treated as SErrors in ARM64. This
> > +  implementation requires access to registers only available to the Secure
> > +  Device Manager (SDM) via Secure Monitor Calls (SMC).
> > +
> > +properties:
> > +
> > +  compatible:
> > +    items:
> > +      - const: altr,socfpga-s10-ecc-manager
> > +
> > +  altr,sysmgr-syscon:
> > +    maxItems: 1
>
> Vendor properties last (but before child nodes).
I will move the vendor property accordingly.
>
> > +
> > +  "#address-cells":
> > +    const: 1
> > +
> > +  "#size-cells":
> > +    const: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  interrupt-controller: true
> > +
> > +  "#interrupt-cells":
> > +    const: 2
> > +
> > +  ranges: true
> > +
> > +  sdramedac:
> > +    type: object
> > +    additionalProperties: false
>
> blank line
>
> > +    properties:
> > +      compatible:
> > +        const: altr,sdram-edac-s10
>
> blank line
>
> > +      altr,sdr-syscon:
> > +        $ref: /schemas/types.yaml#/definitions/phandle
> > +        description: phandle to SDRAM parent
>
> blank line
>
> > +      interrupts:
> > +        maxItems: 1
>
> blank line
>
> And similar on the rest.
I will add the suggested blank lines to all the subnodes.
>
> > +    required:
> > +      - compatible
> > +      - altr,sdr-syscon
> > +      - interrupts
> > +
> > +  ocram-ecc@ff8cc000:
> > +    type: object
> > +    additionalProperties: false
> > +    properties:
> > +      compatible:
> > +        items:
>
> You can drop 'items' if there's only 1 entry.

Thanks for the tip and the review,

Matthew Gerlach

>
> > +          - const: altr,socfpga-a10-ocram-ecc
> > +
> > +      reg:
> > +        maxItems: 1
> > +      altr,ecc-parent:
> > +        $ref: /schemas/types.yaml#/definitions/phandle
> > +        description: phandle to OCRAM parent
> > +      interrupts:
> > +        maxItems: 1
> > +    required:
> > +      - compatible
> > +      - reg
> > +      - altr,ecc-parent
> > +      - interrupts
> > +
> > +  usb0-ecc@ff8c4000:
> > +    type: object
> > +    additionalProperties: false
> > +    properties:
> > +      compatible:
> > +        items:
> > +          - const: altr,socfpga-usb-ecc
> > +      reg:
> > +        maxItems: 1
> > +      altr,ecc-parent:
> > +        $ref: /schemas/types.yaml#/definitions/phandle
> > +        description: phandle to USB parent
> > +      interrupts:
> > +        maxItems: 1
> > +    required:
> > +      - compatible
> > +      - reg
> > +      - altr,ecc-parent
> > +      - interrupts
> > +
> > +  emac0-rx-ecc@ff8c0000:
> > +    type: object
> > +    additionalProperties: false
> > +    properties:
> > +      compatible:
> > +        items:
> > +          - const: altr,socfpga-eth-mac-ecc
> > +      reg:
> > +        maxItems: 1
> > +      altr,ecc-parent:
> > +        $ref: /schemas/types.yaml#/definitions/phandle
> > +        description: phandle to ethernet parent
> > +      interrupts:
> > +        maxItems: 1
> > +    required:
> > +      - compatible
> > +      - reg
> > +      - altr,ecc-parent
> > +      - interrupts
> > +
> > +  emac0-tx-ecc@ff8c0400:
> > +    type: object
> > +    additionalProperties: false
> > +    properties:
> > +      compatible:
> > +        items:
> > +          - const: altr,socfpga-eth-mac-ecc
> > +      reg:
> > +        maxItems: 1
> > +      altr,ecc-parent:
> > +        $ref: /schemas/types.yaml#/definitions/phandle
> > +        description: phandle to ethernet parent
> > +      interrupts:
> > +        maxItems: 1
> > +    required:
> > +      - compatible
> > +      - reg
> > +      - altr,ecc-parent
> > +      - interrupts
> > +
> > +  sdmmca-ecc@ff8c8c00:
> > +    type: object
> > +    additionalProperties: false
> > +    properties:
> > +      compatible:
> > +        items:
> > +          - const: altr,socfpga-sdmmc-ecc
> > +      reg:
> > +        maxItems: 1
> > +      altr,ecc-parent:
> > +        $ref: /schemas/types.yaml#/definitions/phandle
> > +        description: phandle to ethernet parent
> > +      interrupts:
> > +        maxItems: 2
> > +    required:
> > +      - compatible
> > +      - reg
> > +      - altr,ecc-parent
> > +      - interrupts
> > +
> > +required:
> > +  - compatible
> > +  - altr,sysmgr-syscon
> > +  - "#address-cells"
> > +  - "#size-cells"
> > +  - interrupts
> > +  - interrupt-controller
> > +  - "#interrupt-cells"
> > +  - ranges
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +    eccmgr {
> > +        compatible = "altr,socfpga-s10-ecc-manager";
> > +        altr,sysmgr-syscon = <&sysmgr>;
> > +        #address-cells = <1>;
> > +        #size-cells = <1>;
> > +        interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> > +        interrupt-controller;
> > +        #interrupt-cells = <2>;
> > +        ranges;
> > +
> > +        sdramedac {
> > +            compatible = "altr,sdram-edac-s10";
> > +            altr,sdr-syscon = <&sdr>;
> > +            interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
> > +        };
> > +
> > +        ocram-ecc@ff8cc000 {
> > +            compatible = "altr,socfpga-a10-ocram-ecc";
> > +            reg = <0xff8cc000 0x100>;
> > +            altr,ecc-parent = <&ocram>;
> > +            interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
> > +        };
> > +
> > +        usb0-ecc@ff8c4000 {
> > +            compatible = "altr,socfpga-usb-ecc";
> > +            reg = <0xff8c4000 0x100>;
> > +            altr,ecc-parent = <&usb0>;
> > +            interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
> > +        };
> > +
> > +        emac0-rx-ecc@ff8c0000 {
> > +            compatible = "altr,socfpga-eth-mac-ecc";
> > +            reg = <0xff8c0000 0x100>;
> > +            altr,ecc-parent = <&gmac0>;
> > +            interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
> > +        };
> > +
> > +        emac0-tx-ecc@ff8c0400 {
> > +            compatible = "altr,socfpga-eth-mac-ecc";
> > +            reg = <0xff8c0400 0x100>;
> > +            altr,ecc-parent = <&gmac0>;
> > +            interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
> > +        };
> > +
> > +        sdmmca-ecc@ff8c8c00 {
> > +            compatible = "altr,socfpga-sdmmc-ecc";
> > +            reg = <0xff8c8c00 0x100>;
> > +            altr,ecc-parent = <&mmc>;
> > +            interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
> > +                         <15 IRQ_TYPE_LEVEL_HIGH>;
> > +        };
> > +    };

Re: [PATCH 3/4] arm64: dts: agilex: Update eccmgr in DTSI to reflect hw/yaml

[Gerlach, Matthew]

On 3/20/2025 12:34 PM, Rob Herring wrote:
> On Thu, Mar 20, 2025 at 09:46:21AM -0700, Matthew Gerlach wrote:
> > Update socfpga_agilex.dtsi to track the actual hardware description
> > provided in altr,socfpga-s10-ecc-manager.yaml.
> > 
> > Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> > ---
> >  arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 18 ++++++------------
> >  1 file changed, 6 insertions(+), 12 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> > index 1235ba5a9865..708cb8e762b6 100644
> > --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
> > @@ -602,8 +602,7 @@ sdr: sdr@f8011100 {
> >  		};
> >  
> >  		eccmgr {
> > -			compatible = "altr,socfpga-s10-ecc-manager",
> > -				     "altr,socfpga-a10-ecc-manager";
> > +			compatible = "altr,socfpga-s10-ecc-manager";
>
> You are breaking the ABI here. Before this series, the driver required
> altr,socfpga-a10-ecc-manager.
Yes, breaking the ABI required the change in PATCH 2/4, which is 
suboptimal.
>
> >  			altr,sysmgr-syscon = <&sysmgr>;
> >  			#address-cells = <1>;
> >  			#size-cells = <1>;
> > @@ -619,40 +618,35 @@ sdramedac {
> >  			};
> >  
> >  			ocram-ecc@ff8cc000 {
> > -				compatible = "altr,socfpga-s10-ocram-ecc",
> > -					     "altr,socfpga-a10-ocram-ecc";
> > +				compatible = "altr,socfpga-a10-ocram-ecc";
>
> AIUI, nothing used altr,socfpga-s10-ocram-ecc, so this change is okay I
> guess. Normally, we'd require both because there might be some
> difference you find later on, but here you could just look at the parent
> node compatible.
>
> If it were me, I'd just add the compatible string in the schema and
> avoid the .dts change. That would have been less work...
Less work sounds better. I will look at just creating the yaml, with no 
dtsi/dts and no driver changes.
>
> Rob


Thanks for the feedback,

Matthew Gerlach

Re: [PATCH 3/4] arm64: dts: agilex: Update eccmgr in DTSI to reflect hw/yaml

[Krzysztof Kozlowski]

On 21/03/2025 00:24, Gerlach, Matthew wrote:
> 
> On 3/20/2025 12:34 PM, Rob Herring wrote:
>> On Thu, Mar 20, 2025 at 09:46:21AM -0700, Matthew Gerlach wrote:
>>> Update socfpga_agilex.dtsi to track the actual hardware description
>>> provided in altr,socfpga-s10-ecc-manager.yaml.
>>>
>>> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
>>> ---
>>>  arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 18 ++++++------------
>>>  1 file changed, 6 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
>>> index 1235ba5a9865..708cb8e762b6 100644
>>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
>>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
>>> @@ -602,8 +602,7 @@ sdr: sdr@f8011100 {
>>>  		};
>>>  
>>>  		eccmgr {
>>> -			compatible = "altr,socfpga-s10-ecc-manager",
>>> -				     "altr,socfpga-a10-ecc-manager";
>>> +			compatible = "altr,socfpga-s10-ecc-manager";
>>
>> You are breaking the ABI here. Before this series, the driver required
>> altr,socfpga-a10-ecc-manager.
> Yes, breaking the ABI required the change in PATCH 2/4, which is 
> suboptimal.


It's still ABI break for no good reason.

Best regards,
Krzysztof

Re: [PATCH 2/4] EDAC, altera: update driver to reflect hw/yaml

[Borislav Petkov]

On Thu, Mar 20, 2025 at 09:46:20AM -0700, Matthew Gerlach wrote:
> The device tree subnodes, and hardware, for the eccmgr are
> the same for Arria10, Stratix10, and Agilex. Update driver
> to allow the subnodes to be allowed for "altr,socfpga-s10-ecc-manager".
> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> ---
>  drivers/edac/altera_edac.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
> index 3e971f902363..895a5beb700f 100644
> --- a/drivers/edac/altera_edac.c
> +++ b/drivers/edac/altera_edac.c
> @@ -1030,6 +1030,9 @@ static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
>  
>  	np = of_find_compatible_node(NULL, NULL,
>  				     "altr,socfpga-a10-ecc-manager");
> +	if (!np)
> +		np = of_find_compatible_node(NULL, NULL,
> +					     "altr,socfpga-s10-ecc-manager");

Please slap a comment above this here - one can see the difference between the
two calls only after staring at them for a couple of minutes and wonder
where's Waldo.

:-P

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH 2/4] EDAC, altera: update driver to reflect hw/yaml

[Gerlach, Matthew]

On 3/21/2025 2:12 PM, Borislav Petkov wrote:
> On Thu, Mar 20, 2025 at 09:46:20AM -0700, Matthew Gerlach wrote:
> > The device tree subnodes, and hardware, for the eccmgr are
> > the same for Arria10, Stratix10, and Agilex. Update driver
> > to allow the subnodes to be allowed for "altr,socfpga-s10-ecc-manager".
> > 
> > Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> > ---
> >  drivers/edac/altera_edac.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
> > index 3e971f902363..895a5beb700f 100644
> > --- a/drivers/edac/altera_edac.c
> > +++ b/drivers/edac/altera_edac.c
> > @@ -1030,6 +1030,9 @@ static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
> >  
> >  	np = of_find_compatible_node(NULL, NULL,
> >  				     "altr,socfpga-a10-ecc-manager");
> > +	if (!np)
> > +		np = of_find_compatible_node(NULL, NULL,
> > +					     "altr,socfpga-s10-ecc-manager");
>
> Please slap a comment above this here - one can see the difference between the
> two calls only after staring at them for a couple of minutes and wonder
> where's Waldo.

Adding a comment is a very good suggestion. On the other hand, Rob 
Herring and Krzysztof Kozlowski pointed out that this change represents 
a change in the ABI which should be avoided. This change won't be part 
of v2.

>
> :-P
>
> Thx.


Thanks for the feedback,

Matthew Gerlach