From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 707B04A0C; Fri, 21 Mar 2025 22:37:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742596656; cv=none; b=CnHy5cxcQs2DpQCUKmTZ+qOiKzpt6YUR7hDr5bJBkmwjU//GmnYK9nqwd8TNgelNMRXI/0Q6wjMaoGMISQv2tMNx8KXL8MYxuwiIxwN3i5ffgI5PJz/u8PxfHD3m1SsBECH4cI2QUOG//oip/tlfRK6hXTP2qa+Jcj5GmbmNAHI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742596656; c=relaxed/simple; bh=ramSATIM6Gfyw9DQk/rIg5hUgUc4Aq61YIxEdbWpWAc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=kbhvrZ1heUvoJRqXueUHhxPyAg18caQg5qoIe2QP6yJe+sGehLySt5eISC1KBqUzNKao1eufYh24Lp1qaUH8HWhEjHFJJfVsyv725SP6/Fgx2tp9Pr/eCLkzEJrK3qH9/RdxtbVAQ3zzgWb1sjExzTH5uqieiJOfKeVKLroZdes= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=u/b5e3Xw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="u/b5e3Xw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8BD08C4CEE3; Fri, 21 Mar 2025 22:37:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742596655; bh=ramSATIM6Gfyw9DQk/rIg5hUgUc4Aq61YIxEdbWpWAc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=u/b5e3XwA10wQ0+gzZsAmrh+PYEPBTqOTPwQCOEJmGQ72ZsBAs4AUVs6sGkyH/oCm OWh72S7LLTL5DxzFvdSVgJM05lo4MiYSGkdaANNFI7HR/8FtIQh08BqBmmYhZP/ldO U3oL9HVf6BXs+eapmm7aKRLfGJQhcMI2zTLB7ahA4kLIvR71WujKLPNXhhxJ09PWNH dLlWWMcr/3JOadEK6bvLKreEPEgWRHTlPVHQKyqypBDzcPN1PYgvavIhgMIqlbIe4a Y26LDPTZ5wsqjo3Tn2S6/fmAZ82NZi6oHL8CNGEyRnkbS2KBvmAFiFSMTSn7PLiEhS 6vAgxK49Xc4wA== Date: Fri, 21 Mar 2025 17:37:34 -0500 From: Rob Herring To: Christian Marangi Cc: Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Lorenzo Bianconi , Greg Kroah-Hartman , Daniel Danzberger , Arnd Bergmann , Alexander Sverdlin , Nikita Shubin , Linus Walleij , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: Re: [PATCH v2 03/11] dt-bindings: clock: en7523: add Documentation for Airoha AN7581 SCU SSR Message-ID: <20250321223734.GA6837-robh@kernel.org> References: <20250320130054.4804-1-ansuelsmth@gmail.com> <20250320130054.4804-4-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250320130054.4804-4-ansuelsmth@gmail.com> On Thu, Mar 20, 2025 at 02:00:26PM +0100, Christian Marangi wrote: > The Airoha AN7581 SoC have in the SCU register space particular > address that control how some peripheral are configured. > > These are toggeled in the System Status Register and are used to > toggle Serdes port for USB 3.0 mode or HSGMII, USB 3.0 mode or PCIe2 > or setup port for PCIe mode or Ethrnet mode (HSGMII/USXGMII). > > Modes are mutually exclusive and selecting one mode cause the > other feature to not work (example a mode in USB 3.0 cause PCIe > port 2 to not work) This depends also on what is physically > connected to the Hardware and needs to correctly reflect the > System Status Register bits. > > Special care is needed for PCIe port 0 in 2 line mode that > requires both WiFi1 and WiFi2 Serdes port set to PCIe0 2 Line > mode. > > Expose these configuration as an enum of strings in the SCU node and > also add dt-bindings header to reference each serdes port in DT. > > Signed-off-by: Christian Marangi > --- > .../bindings/clock/airoha,en7523-scu.yaml | 101 ++++++++++++++++-- > MAINTAINERS | 7 ++ > include/dt-bindings/soc/airoha,scu-ssr.h | 11 ++ > 3 files changed, 110 insertions(+), 9 deletions(-) > create mode 100644 include/dt-bindings/soc/airoha,scu-ssr.h > > diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml > index fe2c5c1baf43..637ce0e06619 100644 > --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml > +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml > @@ -9,6 +9,7 @@ title: EN7523 Clock > maintainers: > - Felix Fietkau > - John Crispin > + - Christian Marangi > > description: | > This node defines the System Control Unit of the EN7523 SoC, > @@ -26,6 +27,23 @@ description: | > > The clocks are provided inside a system controller node. > > + The System Control Unit may also set different mode for the Serdes ports > + present on the SoC. > + > + These are toggeled in the System Status Register and are used to > + toggle Serdes port for USB 3.0 mode or HSGMII, USB 3.0 mode or PCIe2 > + or setup port for PCIe mode or Ethernet mode (HSGMII/USXGMII). > + > + Modes are mutually exclusive and selecting one mode cause the > + other feature to not work (example a mode in USB 3.0 cause PCIe > + port 2 to not work) This depends also on what is physically > + connected to the Hardware and needs to correctly reflect the > + System Status Register bits. > + > + Special care is needed for PCIe port 0 in 2 line mode that > + requires both WiFi1 and WiFi2 Serdes port set to PCIe0 2 Line > + mode. > + > properties: > compatible: > items: > @@ -49,6 +67,40 @@ properties: > description: ID of the controller reset line > const: 1 > > + airoha,serdes-wifi1: > + description: Configure the WiFi1 Serdes port > + $ref: /schemas/types.yaml#/definitions/string > + enum: > + - pcie0_x2 > + - pcie0_x1 > + - ethernet > + default: pcie0_x1 > + > + airoha,serdes-wifi2: > + description: Configure the WiFi2 Serdes port > + $ref: /schemas/types.yaml#/definitions/string > + enum: > + - pcie0_x2 > + - pcie1_x1 > + - ethernet > + default: pcie1_x1 > + > + airoha,serdes-usb1: > + description: Configure the USB1 Serdes port > + $ref: /schemas/types.yaml#/definitions/string > + enum: > + - usb3 > + - ethernet > + default: usb3 > + > + airoha,serdes-usb2: > + description: Configure the USB2 Serdes port > + $ref: /schemas/types.yaml#/definitions/string > + enum: > + - usb3 > + - pcie2_x1 > + default: usb3 Couldn't you make this a phy provider and use the mode flags in the phy cells? > + > required: > - compatible > - reg > @@ -64,6 +116,12 @@ allOf: > reg: > minItems: 2 > > + airoha,serdes-wifi1: false > + airoha,serdes-wifi2: false > + > + airoha,serdes-usb1: false > + airoha,serdes-usb2: false > + > '#reset-cells': false > > - if: > @@ -75,6 +133,24 @@ allOf: > reg: > maxItems: 1 > > + - if: > + properties: > + airoha,serdes-wifi1: > + const: pcie0_x2 This is also true if airoha,serdes-wifi1 is not present. Probably not what you intended. > + then: > + properties: > + airoha,serdes-wifi2: > + const: pcie0_x2 > + > + - if: > + properties: > + airoha,serdes-wifi2: > + const: pcie0_x2 > + then: > + properties: > + airoha,serdes-wifi1: > + const: pcie0_x2 > + > additionalProperties: false