From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84AFF212D8D; Fri, 28 Mar 2025 08:11:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743149482; cv=none; b=m9sKRNqo0CdE5HB1oAQFNHYS0an5xLgETfhZU8GRlquRMyV701ViFq34f4aKjwuk8t/CvzY/LXgH423gY0DkEt3RVe6HzEx3cDBgCKnSlS70ZBDhdrd2gkM2M+Tm9XsxMwplTKiQCvx6Fbq22c6yiN99S0xqpBnCj/I1dMjoF8s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743149482; c=relaxed/simple; bh=CRPlWJM2tA1Y+X2msMtTS+SlW5MlQ7mYsR7+wX8qQSg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Hfe46lfyUjvk6NZf4RC6CDZXQGC3A3RRr1grs6RBeT5ljW6HvOp5pBhCZ/F4T/Jc/EqyWFKSUVspoGQmPwqsz0H1BYP9Db8bva8wHG2wetGNqqXjJx34YzUX3c+zraewLLZcMGmPgfWqW07bYLnVXcV+RI4YINIiBBglH71k95I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2D16FC4CEEE; Fri, 28 Mar 2025 08:11:20 +0000 (UTC) Date: Fri, 28 Mar 2025 09:11:18 +0100 From: Krzysztof Kozlowski To: Jagadeesh Kona Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Vladimir Zapolskiy , Dmitry Baryshkov , Ajit Pandey , Imran Shaik , Taniya Das , Satya Priya Kakitapalli , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue Subject: Re: [PATCH v3 03/18] dt-bindings: clock: qcom: sm8450-camcc: Allow to specify two power domains Message-ID: <20250328-cautious-glorious-chupacabra-b42cc0@krzk-bin> References: <20250327-videocc-pll-multi-pd-voting-v3-0-895fafd62627@quicinc.com> <20250327-videocc-pll-multi-pd-voting-v3-3-895fafd62627@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20250327-videocc-pll-multi-pd-voting-v3-3-895fafd62627@quicinc.com> On Thu, Mar 27, 2025 at 03:22:23PM +0530, Jagadeesh Kona wrote: > From: Vladimir Zapolskiy > > To configure the camera PLLs and enable the camera GDSCs on SM8450, SM8475, > SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX. > Therefore, update the camcc bindings to include the MXC power domain on > these platforms. > > Fixes: 9cbc64745fc6 ("dt-bindings: clock: qcom: Add SM8550 camera clock controller") > Signed-off-by: Vladimir Zapolskiy > Signed-off-by: Jagadeesh Kona > --- > .../devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 18 ++++++++++++------ > 1 file changed, 12 insertions(+), 6 deletions(-) Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof