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Date: Fri, 28 Mar 2025 09:10:51 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Jagadeesh Kona <quic_jkona@quicinc.com>
Cc: Bjorn Andersson <andersson@kernel.org>, 
	Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, 
	Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, 
	Konrad Dybcio <konradybcio@kernel.org>, Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>, 
	Dmitry Baryshkov <lumag@kernel.org>, Ajit Pandey <quic_ajipan@quicinc.com>, 
	Imran Shaik <quic_imrashai@quicinc.com>, Taniya Das <quic_tdas@quicinc.com>, 
	Satya Priya Kakitapalli <quic_skakitap@quicinc.com>, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, 
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, 
	Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Subject: Re: [PATCH v3 01/18] dt-bindings: clock: qcom,sm8450-videocc: Add
 MXC power domain
Message-ID: <20250328-solid-horse-of-refinement-b9f7a3@krzk-bin>
References: <20250327-videocc-pll-multi-pd-voting-v3-0-895fafd62627@quicinc.com>
 <20250327-videocc-pll-multi-pd-voting-v3-1-895fafd62627@quicinc.com>
 <20250328-wise-chocolate-marten-bdccd6@krzk-bin>
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In-Reply-To: <20250328-wise-chocolate-marten-bdccd6@krzk-bin>

On Fri, Mar 28, 2025 at 09:09:00AM +0100, Krzysztof Kozlowski wrote:
> On Thu, Mar 27, 2025 at 03:22:21PM +0530, Jagadeesh Kona wrote:
> > To configure the video PLLs and enable the video GDSCs on SM8450,
> > SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along
> 
> Either your patches are not ordered correctly or you forgot that
> SC8280xp also gets MXC.

Ah, no, that's videocc, I mixed up devices.

It's fine.

Best regards,
Krzysztof