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AJvYcCW8jTGLD6Y1ceQxiUH8Bk4EfgQXuH0f6qVPZVirFog5R+N+EO2/AmYterSpLloIPDtxwnvLX7ZqoMlv@vger.kernel.org X-Gm-Message-State: AOJu0YyFj97kzA/IRsmeBI70Cjn/9upMmi2wpP/Ac5pGmATSybhbPiAt fJPF4xEv8pvf2Um5b9KsQBdGLMmOuHdzBOatGJsKY97gIKQ3CQ0qXRn6QjejeOP7H9zYxFrDb1f qxEtGI/uzX2/FSTsOfFy91BooLA== X-Google-Smtp-Source: AGHT+IGFOOhmWr3Z6viGq+ulkQ92nT2eBCuYGsXtiOmRX4Ho8ivQC5UMWY8LfRMuamRE7HQJon2Mz8MvCxGpPT2O6fQ= X-Received: from pjbee12.prod.google.com ([2002:a17:90a:fc4c:b0:2ff:4be0:c675]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:3b50:b0:2fe:a0ac:5fcc with SMTP id 98e67ed59e1d1-3053215c05cmr20698254a91.34.1743636886898; Wed, 02 Apr 2025 16:34:46 -0700 (PDT) Date: Wed, 2 Apr 2025 16:33:53 -0700 In-Reply-To: <20250402233407.2452429-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250402233407.2452429-1-willmcvicker@google.com> X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog Message-ID: <20250402233407.2452429-3-willmcvicker@google.com> Subject: [PATCH v2 2/7] clocksource/drivers/exynos_mct: Don't register as a sched_clock on arm64 From: Will McVicker To: Catalin Marinas , Will Deacon , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Daniel Lezcano , Thomas Gleixner , Saravana Kannan , Krzysztof Kozlowski Cc: Will McVicker , Donghoon Yu , Hosung Kim , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Youngmin Nam , linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" To use the MCT as a sched_clock, the timer value has to be accessed vi an MCT register which is extremely slow. To improve performance on Arm64 SoCs, use the Arm architected timer as the default clocksource. Note, we can't completely disable the MCT on Arm64 since it needs to be used as the wakeup source for the arch_timer to exit the "c2" idle state. Since ARM SoCs don't have an architectured timer, the MCT will continue to be the default clocksource. Detailed discussion on this topic can be found at [1]. [1] https://lore.kernel.org/linux-samsung-soc/1400188079-21832-1-git-send-email-chirantan@chromium.org/ Signed-off-by: Donghoon Yu Signed-off-by: Youngmin Nam [Original commit from https://android.googlesource.com/kernel/gs/+/630817f7080e92c5e0216095ff52f6eb8dd00727 Signed-off-by: Will McVicker Reviewed-by: Youngmin Nam --- drivers/clocksource/exynos_mct.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index da09f467a6bb..96361d5dc57d 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -219,12 +219,18 @@ static struct clocksource mct_frc = { .resume = exynos4_frc_resume, }; +/* + * Since ARM devices do not have an architected timer, they need to continue + * using the MCT as the main clocksource for timekeeping, sched_clock, and the + * delay timer. For AARCH64 SoCs, the architected timer is the preferred + * clocksource due to it's superior performance. + */ +#if defined(CONFIG_ARM) static u64 notrace exynos4_read_sched_clock(void) { return exynos4_read_count_32(); } -#if defined(CONFIG_ARM) static struct delay_timer exynos4_delay_timer; static cycles_t exynos4_read_current_timer(void) @@ -250,12 +256,13 @@ static int __init exynos4_clocksource_init(bool frc_shared) exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; exynos4_delay_timer.freq = clk_rate; register_current_timer_delay(&exynos4_delay_timer); + + sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); #endif if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name); - sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); return 0; } -- 2.49.0.472.ge94155a9ec-goog