From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 944B64A1E; Tue, 8 Apr 2025 03:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744083138; cv=none; b=CIMud0jxAiLtgvO9vnDyKR7xJwmt3k863km4OiCJmnYve58FYUQirlB9RLLyz7EXdNhB4sg2HgvhQL4wRsTpfl1X4YMA19eBWUXX31YQiVarCMNHNQtIkS+pDkwPrF2cghyMe6SxhX7VqdcyUfXQBkM0uCgLu7TZYhYyCxX4XjA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744083138; c=relaxed/simple; bh=UpOGkLgC74S7224Y+s/tMj0WzfeO2qPrQXn/c/XvLLQ=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=qTJfdvF52HMo1OIYgtVvNGM6+goTo+ncHeLwmEf1/vt6FIGd23TGUCzwPjXYS3wufDcMpE6IZOsl75urGc6cubUvryvpnm4g3qlhbZ7JhKobxANaorpEuLPwlJ1xgS0rMgqZChAbyHa13bs9PQY1oJQ2ApDExiPrkoBPFF+MBS8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=WR9mIc/7; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="WR9mIc/7" X-UUID: 0e2951c4142a11f08eb9c36241bbb6fb-20250408 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=9eqgYOtigqWCLfmEGHqanxE7xtbmmobsCv5n5TI9WPQ=; b=WR9mIc/7Et63oPw3q6GpGCVppTkAewEBTdqaCC3CQnUCdVO61mprKN3Jl8AojkkUxBrQramK2YyJvpB8Ca/TuumKVSfeWiHOv+3oMpyEwBYTwKS0GAffGkN45vXk0ZMSHmNB/FT3Yrw1t0rWb+3UKFxXpAO/wRCMF+4iz19LT8Q=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:96b66c1c-44da-4203-aa9f-7a12db2bbde3,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f,CLOUDID:ac5c558d-f5b8-47d5-8cf3-b68fe7530c9a,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0|50,EDM:-3,IP:ni l,URL:1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-UUID: 0e2951c4142a11f08eb9c36241bbb6fb-20250408 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 291893348; Tue, 08 Apr 2025 11:32:10 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Tue, 8 Apr 2025 11:32:09 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Tue, 8 Apr 2025 11:32:08 +0800 From: Friday Yang To: Yong Wu , Krzysztof Kozlowski , "Rob Herring" , Conor Dooley , "Matthias Brugger" , AngeloGioacchino Del Regno , Philipp Zabel CC: Friday Yang , , , , , Subject: [PATCH v6 0/3] Add SMI reset and clamp for MediaTek MT8188 SoC Date: Tue, 8 Apr 2025 11:31:53 +0800 Message-ID: <20250408033206.12176-1-friday.yang@mediatek.com> X-Mailer: git-send-email 2.46.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Based on tag: next-20250407, linux-next/master On the MediaTek MT8188 SoC platform, we encountered power-off failures and SMI bus hang issues during camera stress tests. The issue arises because bus glitches are sometimes produced when MTCMOS powers on or off. While this is fairly normal, the software must handle these glitches to avoid mistaking them for transaction signals. What's more, this issue emerged only after the initial upstreaming of SMI driver. The software solutions can be summarized as follows: 1. Use CLAMP to disable the SMI sub-common port after turning off the LARB CG and before turning off the LARB MTCMOS. 2. Use CLAMP to disable/enable the SMI sub-common port. 3. Implement an AXI reset for SMI LARBs. Changes v6: - Fix code comments style. - Add another patch to replace 'pm_runtime_enable' with 'devm_pm_runtime_enable'. v5: https://lore.kernel.org/lkml/20250311122327.20685-2-friday.yang@mediatek.com/ https://lore.kernel.org/lkml/20250311122327.20685-3-friday.yang@mediatek.com/ Friday Yang (3): dt-bindings: memory: mediatek: Add SMI reset and clamp for MT8188 memory: mtk-smi: mt8188: Add SMI reset and clamp for MT8188 memory: mtk-smi: mt8188: Use devm_pm_runtime_enable .../mediatek,smi-common.yaml | 2 + .../memory-controllers/mediatek,smi-larb.yaml | 19 +++ drivers/memory/mtk-smi.c | 150 +++++++++++++++++- 3 files changed, 164 insertions(+), 7 deletions(-) -- 2.46.0