From: Conor Dooley <conor@kernel.org>
To: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Paul Walmsley <paul.walmsley@sifive.com>,
Samuel Holland <samuel.holland@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Min Lin <linmin@eswincomputing.com>,
Pritesh Patel <pritesh.patel@einfochips.com>,
Yangyu Chen <cyy@cyyself.name>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Yu Chien Peter Lin <peterlin@andestech.com>,
Charlie Jenkins <charlie@rivosinc.com>,
Kanak Shilledar <kanakshilledar@gmail.com>,
Darshan Prajapati <darshan.prajapati@einfochips.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Heiko Stuebner <heiko@sntech.de>,
Aradhya Bhatia <a-bhatia1@ti.com>,
rafal@milecki.pl, Anup Patel <anup@brainfault.org>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility
Date: Fri, 11 Apr 2025 17:25:47 +0100 [thread overview]
Message-ID: <20250411-backward-mountain-3dd2b913f9f9@spud> (raw)
In-Reply-To: <20250410152519.1358964-6-pinkesh.vaghela@einfochips.com>
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On Thu, Apr 10, 2025 at 08:55:14PM +0530, Pinkesh Vaghela wrote:
> From: Pritesh Patel <pritesh.patel@einfochips.com>
>
> This cache controller is also used on the ESWIN EIC7700 SoC.
> However, it have 256KB private L2 Cache and shared L3 Cache of 4MB.
> So add dedicated compatible string for it.
>
> Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
This and the cache driver patch have already been applied.
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next prev parent reply other threads:[~2025-04-11 16:25 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-10 15:25 [PATCH v3 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 01/10] dt-bindings: riscv: Add SiFive P550 CPU compatible Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 02/10] riscv: Add Kconfig option for ESWIN platforms Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 03/10] dt-bindings: vendor-prefixes: add eswin Pinkesh Vaghela
2025-04-10 17:33 ` Rob Herring (Arm)
2025-04-11 8:09 ` Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 04/10] dt-bindings: riscv: Add SiFive HiFive Premier P550 board Pinkesh Vaghela
2025-04-26 14:38 ` Jisheng Zhang
2025-05-23 10:04 ` 林敏
2025-04-10 15:25 ` [PATCH v3 05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility Pinkesh Vaghela
2025-04-11 16:25 ` Conor Dooley [this message]
2025-04-10 15:25 ` [PATCH v3 06/10] cache: sifive_ccache: Add ESWIN EIC7700 support Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 07/10] dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 08/10] dt-bindings: timer: Add ESWIN EIC7700 CLINT Pinkesh Vaghela
2025-05-14 15:18 ` Daniel Lezcano
2025-04-10 15:25 ` [PATCH v3 09/10] riscv: dts: add initial support for EIC7700 SoC Pinkesh Vaghela
2025-04-10 15:25 ` [PATCH v3 10/10] riscv: dts: eswin: add HiFive Premier P550 board device tree Pinkesh Vaghela
2025-04-14 12:55 ` Ariel D'Alessandro
2025-04-14 16:00 ` Samuel Holland
2025-04-15 7:39 ` Sjoerd Simons
2025-04-16 19:50 ` Ariel D'Alessandro
2025-04-26 14:32 ` [PATCH v3 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC Jisheng Zhang
2025-05-19 13:32 ` [External] " Pinkesh Vaghela
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