* [PATCH v5 1/3] spi: dt-bindings: snps,dw-apb-ssi: Merge duplicate compatible entry
2025-04-22 2:27 [PATCH v5 0/3] Add basic SPI support for SOPHGO SG2042 SoC Zixian Zeng
@ 2025-04-22 2:27 ` Zixian Zeng
2025-04-24 7:33 ` Krzysztof Kozlowski
2025-04-22 2:27 ` [PATCH v5 2/3] spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC Zixian Zeng
2025-04-22 2:27 ` [PATCH v5 3/3] riscv: sophgo: dts: Add spi controller for SG2042 Zixian Zeng
2 siblings, 1 reply; 6+ messages in thread
From: Zixian Zeng @ 2025-04-22 2:27 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Chen Wang, Inochi Amaoto,
Alexandre Ghiti, Mark Brown, Inochi Amaoto, Geert Uytterhoeven,
Magnus Damm
Cc: devicetree, linux-riscv, linux-kernel, linux-spi, sophgo,
chao.wei, xiaoguang.xing, dlan, linux-renesas-soc, Zixian Zeng
Microsemi Ocelot/Jaguar2, Renesas RZ/N1 and T-HEAD TH1520
SoC-specific compatibles, which eventually fallback to the
generic DW ssi compatible, it's better to combine them in single entry
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
---
.../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 18 ++++++------------
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index bccd00a1ddd0ad92b437eed5b525a6ea1963db57..a43d2fb9942d85b1482a52782c0a97cd5c6edd99 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -56,19 +56,17 @@ properties:
enum:
- snps,dw-apb-ssi
- snps,dwc-ssi-1.01a
- - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller
- items:
- - enum:
- - mscc,ocelot-spi
- - mscc,jaguar2-spi
- - const: snps,dw-apb-ssi
- description: Microchip Sparx5 SoC SPI Controller
const: microchip,sparx5-spi
- description: Amazon Alpine SPI Controller
const: amazon,alpine-dw-apb-ssi
- - description: Renesas RZ/N1 SPI Controller
+ - description: Vendor controllers which use snps,dw-apb-ssi as fallback
items:
- - const: renesas,rzn1-spi
+ - enum:
+ - mscc,ocelot-spi
+ - mscc,jaguar2-spi
+ - renesas,rzn1-spi
+ - thead,th1520-spi
- const: snps,dw-apb-ssi
- description: Intel Keem Bay SPI Controller
const: intel,keembay-ssi
@@ -88,10 +86,6 @@ properties:
- renesas,r9a06g032-spi # RZ/N1D
- renesas,r9a06g033-spi # RZ/N1S
- const: renesas,rzn1-spi # RZ/N1
- - description: T-HEAD TH1520 SoC SPI Controller
- items:
- - const: thead,th1520-spi
- - const: snps,dw-apb-ssi
reg:
minItems: 1
--
2.49.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v5 1/3] spi: dt-bindings: snps,dw-apb-ssi: Merge duplicate compatible entry
2025-04-22 2:27 ` [PATCH v5 1/3] spi: dt-bindings: snps,dw-apb-ssi: Merge duplicate compatible entry Zixian Zeng
@ 2025-04-24 7:33 ` Krzysztof Kozlowski
0 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2025-04-24 7:33 UTC (permalink / raw)
To: Zixian Zeng
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Chen Wang, Inochi Amaoto,
Alexandre Ghiti, Mark Brown, Inochi Amaoto, Geert Uytterhoeven,
Magnus Damm, devicetree, linux-riscv, linux-kernel, linux-spi,
sophgo, chao.wei, xiaoguang.xing, dlan, linux-renesas-soc
On Tue, Apr 22, 2025 at 10:27:08AM GMT, Zixian Zeng wrote:
> Microsemi Ocelot/Jaguar2, Renesas RZ/N1 and T-HEAD TH1520
> SoC-specific compatibles, which eventually fallback to the
> generic DW ssi compatible, it's better to combine them in single entry
>
> Suggested-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
> ---
> .../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 18 ++++++------------
> 1 file changed, 6 insertions(+), 12 deletions(-)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 2/3] spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC
2025-04-22 2:27 [PATCH v5 0/3] Add basic SPI support for SOPHGO SG2042 SoC Zixian Zeng
2025-04-22 2:27 ` [PATCH v5 1/3] spi: dt-bindings: snps,dw-apb-ssi: Merge duplicate compatible entry Zixian Zeng
@ 2025-04-22 2:27 ` Zixian Zeng
2025-04-22 8:50 ` Krzysztof Kozlowski
2025-04-22 2:27 ` [PATCH v5 3/3] riscv: sophgo: dts: Add spi controller for SG2042 Zixian Zeng
2 siblings, 1 reply; 6+ messages in thread
From: Zixian Zeng @ 2025-04-22 2:27 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Chen Wang, Inochi Amaoto,
Alexandre Ghiti, Mark Brown, Inochi Amaoto, Geert Uytterhoeven,
Magnus Damm
Cc: devicetree, linux-riscv, linux-kernel, linux-spi, sophgo,
chao.wei, xiaoguang.xing, dlan, linux-renesas-soc, Zixian Zeng
Sophgo SG2042 ships an SPI controller [1] compatible with the Synopsys
DW-SPI IP. Add SoC-specific compatible string and use the generic one
as fallback.
Link: https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/SPI.rst [1]
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index a43d2fb9942d85b1482a52782c0a97cd5c6edd99..d32380a2e5b18f61ed66715b4ac67c04fbda10ef 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -67,6 +67,7 @@ properties:
- mscc,jaguar2-spi
- renesas,rzn1-spi
- thead,th1520-spi
+ - sophgo,sg2042-spi
- const: snps,dw-apb-ssi
- description: Intel Keem Bay SPI Controller
const: intel,keembay-ssi
--
2.49.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v5 2/3] spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC
2025-04-22 2:27 ` [PATCH v5 2/3] spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC Zixian Zeng
@ 2025-04-22 8:50 ` Krzysztof Kozlowski
0 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2025-04-22 8:50 UTC (permalink / raw)
To: Zixian Zeng
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Chen Wang, Inochi Amaoto,
Alexandre Ghiti, Mark Brown, Inochi Amaoto, Geert Uytterhoeven,
Magnus Damm, devicetree, linux-riscv, linux-kernel, linux-spi,
sophgo, chao.wei, xiaoguang.xing, dlan, linux-renesas-soc
On Tue, Apr 22, 2025 at 10:27:09AM GMT, Zixian Zeng wrote:
> Sophgo SG2042 ships an SPI controller [1] compatible with the Synopsys
> DW-SPI IP. Add SoC-specific compatible string and use the generic one
> as fallback.
>
> Link: https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/SPI.rst [1]
>
> Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
> ---
> Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index a43d2fb9942d85b1482a52782c0a97cd5c6edd99..d32380a2e5b18f61ed66715b4ac67c04fbda10ef 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -67,6 +67,7 @@ properties:
> - mscc,jaguar2-spi
> - renesas,rzn1-spi
> - thead,th1520-spi
> + - sophgo,sg2042-spi
Messed order. s goes before t.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 3/3] riscv: sophgo: dts: Add spi controller for SG2042
2025-04-22 2:27 [PATCH v5 0/3] Add basic SPI support for SOPHGO SG2042 SoC Zixian Zeng
2025-04-22 2:27 ` [PATCH v5 1/3] spi: dt-bindings: snps,dw-apb-ssi: Merge duplicate compatible entry Zixian Zeng
2025-04-22 2:27 ` [PATCH v5 2/3] spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC Zixian Zeng
@ 2025-04-22 2:27 ` Zixian Zeng
2 siblings, 0 replies; 6+ messages in thread
From: Zixian Zeng @ 2025-04-22 2:27 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Chen Wang, Inochi Amaoto,
Alexandre Ghiti, Mark Brown, Inochi Amaoto, Geert Uytterhoeven,
Magnus Damm
Cc: devicetree, linux-riscv, linux-kernel, linux-spi, sophgo,
chao.wei, xiaoguang.xing, dlan, linux-renesas-soc, Zixian Zeng
Add spi controllers for SG2042.
SG2042 uses the upstreamed Synopsys DW SPI IP.
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index aa8b7fcc125d71eec12b09493964d90f5dfed27c..ddde4c613c4734db191de500b016b322a9602efc 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -537,6 +537,32 @@ uart0: serial@7040000000 {
status = "disabled";
};
+ spi0: spi@7040004000 {
+ compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
+ reg = <0x70 0x40004000 0x00 0x1000>;
+ clocks = <&clkgen GATE_CLK_APB_SPI>;
+ interrupt-parent = <&intc>;
+ interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <2>;
+ resets = <&rstgen RST_SPI0>;
+ status = "disabled";
+ };
+
+ spi1: spi@7040005000 {
+ compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
+ reg = <0x70 0x40005000 0x00 0x1000>;
+ clocks = <&clkgen GATE_CLK_APB_SPI>;
+ interrupt-parent = <&intc>;
+ interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <2>;
+ resets = <&rstgen RST_SPI1>;
+ status = "disabled";
+ };
+
emmc: mmc@704002a000 {
compatible = "sophgo,sg2042-dwcmshc";
reg = <0x70 0x4002a000 0x0 0x1000>;
--
2.49.0
^ permalink raw reply related [flat|nested] 6+ messages in thread