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(fttx-pool-217.61.156.53.bambit.de [217.61.156.53]) by mxbox4.masterlogin.de (Postfix) with ESMTPSA id 504B0801F5; Tue, 22 Apr 2025 13:24:55 +0000 (UTC) From: Frank Wunderlich To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , Daniel Golle , Sean Wang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org Subject: [PATCH v4 7/8] arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2 Date: Tue, 22 Apr 2025 15:24:30 +0200 Message-ID: <20250422132438.15735-8-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422132438.15735-1-linux@fw-web.de> References: <20250422132438.15735-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mail-ID: 3df57c91-f0e1-43d9-be6f-95cea4f19eca From: Frank Wunderlich First usb and third pcie controller on mt7988 need a xs-phy to work properly. Signed-off-by: Frank Wunderlich --- v3: - drop unneeded properties and compatibles from topmisc - change offset to have clean syscon (without power controller) v4: - fix unit adress of topmisc --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 88b56a24efca..a59f8708f0ef 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -334,6 +334,8 @@ usb@11190000 { <&infracfg CLK_INFRA_133M_USB_HCK>, <&infracfg CLK_INFRA_USB_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + phys = <&xphyu2port0 PHY_TYPE_USB2>, + <&xphyu3port0 PHY_TYPE_USB3>; status = "disabled"; }; @@ -398,6 +400,9 @@ pcie2: pcie@11280000 { pinctrl-0 = <&pcie2_pins>; status = "disabled"; + phys = <&xphyu3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &pcie_intc2 0>, @@ -548,6 +553,37 @@ tphyu3port0: usb-phy@11c50700 { }; }; + + topmisc: system-controller@11d10084 { + compatible = "mediatek,mt7988-topmisc", + "syscon"; + reg = <0 0x11d10084 0 0xff80>; + }; + + xs-phy@11e10000 { + compatible = "mediatek,mt7988-xsphy", + "mediatek,xsphy"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + xphyu2port0: usb-phy@11e10000 { + reg = <0 0x11e10000 0 0x400>; + clocks = <&infracfg CLK_INFRA_USB_UTMI>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + xphyu3port0: usb-phy@11e13000 { + reg = <0 0x11e13400 0 0x500>; + clocks = <&infracfg CLK_INFRA_USB_PIPE>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,syscon-type = <&topmisc 0x194 0>; + }; + }; + clock-controller@11f40000 { compatible = "mediatek,mt7988-xfi-pll"; reg = <0 0x11f40000 0 0x1000>; -- 2.43.0